CXA3026Q
8-bit 120MSPS Flash A/D Converter
Description
The CXA3026Q is an 8-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1: 2 demultiplexed output.
48 pin QFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING
DVEE3
6
VRB
7
AGND
VIN
8
AVCC
VRM2
9
VRM1
VRM3
AVCC
AGND
12 11 10
VRT
Pin Configuration (Top View)
DGND3
Features
• Differential linearity error: ±0.5LSB or less
Structure
• Integral linearity error: ±0.5LSB or less
Bipolar silicon monolithic IC
• High-speed operation with a maximum conversion
rate of 120MSPS
Applications
• Low input capacitance: 21pF
• Magnetic recording (PRML)
• Wide analog input bandwidth: 150MHz
• Communications (QPSK, QAM)
• Low power consumption: 760mW
• LCDs
• Low error rate
• Digital oscilloscopes
• Excellent temperature characteristics
• 1: 2 demultiplexed output
• 1/2 frequency divided clock output
(with reset function)
• Compatible with ECL, PECL and TTL digital input levels
• Single +5V power supply operation available
• Surface mounting package
5
4
3
2
1
CLK/E 13
48 RESETN/E
CLKN/E 14
47
RESET/E
46 RESETN/T
CLK/T 15
N.C. 16
45 SELECT
N.C. 17
44 INV
N.C. 18
43 CLKOUT
DVCC2 19
42 DVCC2
DGND2 20
41 DGND2
P2D0 21
40 P1D7
P2D1 22
39 P1D6
P2D2 23
38 P1D5
P2D3 24
37 P1D4
P1D3
P1D2
P1D1
P1D0
DGND2
DVCC1
DVCC2
DGND1
P2D7
P2D6
P2D4
P2D5
25 26 27 28 29 30 31 32 33 34 35 36
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94711D92
CXA3026Q
Absolute Maximum Ratings (Ta = 25°C)
•
•
•
•
•
•
Unit
Supply voltage
AVCC, DVCC1, DVCC2
–0.5 to +7.0
V
DGND3
–0.5 to +7.0
V
DVEE3
–7.0 to +0.5
V
DGND3 – DVEE3
–0.5 to +7.0
V
VRT – 2.7 to AVCC
V
Analog input voltage
VIN
Reference input voltage
VRT
2.7 to AVCC
V
VIN – 2.7 to AVCC
V
VRB
|VRT – VRB|
2.5
V
Digital input voltage
ECL (∗∗∗/E∗1)
DVEE3 to +0.5
V
PECL (∗∗∗/E)
–0.5 to DGND3
V
TTL (∗∗∗/T, INV)
–0.5 to DVCC1
V
V
other (SELECT)
–0.5 to DVCC1
∗
∗∗∗
∗∗∗
2
VID (| /E –
N/E|)
2.7
V
Storage temperature
Tstg
–65 to +150
°C
Allowable power dissipation PD
2
W
(when mounted on a glass fabric base epoxy board with 50mm x 50mm, 1.6mm thick)
Recommended Operating Conditions
•
•
•
•
•
•
With a single power supply With dual power supplies Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Supply voltage
DVCC1, DVCC2, AVCC
+4.75
+5.0
+5.25 +4.75
+5.0
+5.25
V
DGND1, DGND2, AGND –0.05
0
+0.05 –0.05
0
+0.05
V
DGND3
+4.75
+5.0
+5.25 –0.05
0
+0.05
V
–0.05
0
+0.05
–5.5
–5.0
–4.75
V
DVEE3
Analog input voltage
VIN
VRB
VRT
VRB
VRT
V
Reference input voltage VRT
+2.9
+4.1
+2.9
+4.1
V
VRB
+1.4
+2.6
+1.4
+2.6
V
|VRT – VRB|
1.5
2.1
1.5
2.1
V
Digital input voltage
ECL (∗∗∗/E)
: VIH
DGND3 – 1.05
DGND3 – 0.5 V
: VIL
DGND3 – 3.2
DGND3 – 1.4 V
PECL (∗∗∗/E)
: VIH DGND3 – 1.05 DGND3 – 0.5
V
: VIL DGND3 – 3.2
DGND3 – 1.4
V
TTL (∗∗∗/T, INV) : VIH
2.0
2.0
V
: VIL
0.8
0.8
V
other (SELECT) : VIH
DVCC1
DVCC1
V
: VIL
DGND1
DGND1
V
VID∗2 (|∗∗∗/E – ∗∗∗N/E|)
0.4
0.8
0.4
0.8
V
Maximum conversion rate Fc
(Straight mode)
100
100
MSPS
(DMUX mode)
120
120
MSPS
Ambient temperature
Ta
–20
+75
–20
+75
°C
∗1 ∗∗∗/E and ∗∗∗/T indicate CLK/E and CLK/T, etc. for the pin name.
∗2 VID: Input Voltage Differential
ECL and PECL switching level
DGND3
VIH (max.)
VIL
VTH (DGND3 – 1.2V)
VID
VIH
VIL (min.)
–2–
CXA3026Q
Block Diagram
AVCC
5
8
INV
DVCC1
44
30
DVCC2
DGND3
19 31 42
12
VRT 11
r1
r/2
(MSB)
r
40 P1D7
1
r
39 P1D6
2
6bits
38 P1D5
63
8bits
r
VRM3 9
64
TTLOUT
•
•
•
LATCHA
r
37 P1D4
36 P1D3
r
35 P1D2
65
6bits
•
•
•
126
127
r
VRM2 7
VIN 6
128
r
ENCODER
r
129
r
•
•
•
6bits
34 P1D1
6-bit LATCH + ENCODER
r
33 P1D0
(LSB)
8bits
(MSB)
28 P2D7
27 P2D6
191
r
26 P2D5
LATCHB
192
r
193
r
•
•
•
TTLOUT
VRM1 4
25 P2D4
24 P2D3
6bits
23 P2D2
254
r
22 P2D1
255
r2
VRB 2
21 P2D0
r/2
(LSB)
16
CLK/T 15
17
Delay
CLK/E 13
N. C.
18
CLKN/E 14
D
Q
Q
RESETN/T 46
Select
43 CLKOUT
RESETN/E 48
RESET/E 47
3 10
AGND
45
29
SELECT DGND1
–3–
20 32 41
DGND2
1
DVEE3
CXA3026Q
Pin Description and I/O Pin Equivalent Circuit
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
3, 10
AGND
GND
Analog ground.
Separated from the digital ground.
5, 8
AVCC
+5V
(typ.)
Analog power supply.
Separated from the digital power
supply.
20, 29 DGND1
32, 41 DGND2
GND
Digital ground.
19, 30 DVCC1
31, 42 DVCC2
+5V
(typ.)
Digital power supply.
12
+5V (Typ.)
(With a
single
power
supply)
DGND3
Digital power supply.
Ground for ECL input.
+5V for PECL and TTL input.
GND
(With dual
power
supplies)
1
GND
(With a
single
power
supply)
DVEE3
Digital power supply.
–5V for ECL input.
Ground for PECL and TTL input.
–5V (Typ.)
(With dual
power
supplies)
No connected pin.
Not connected with the internal
circuits.
16, 17
N.C.
18
13
CLK/E
I
Clock input.
I
CLK/E complementary input.
When left open, this pin goes to the
threshold potential.
Only CLK/E can be used for
operation, but complementary input
is recommended to attain fast and
stable operation.
DGND3
14
CLKN/E
r
r
13 48
ECL/
PECL
RESETN/E
I
1.2V
48
14 47
RESET/E
r
RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
DVEE3
47
r
Reset input.
When the input is set to low level,
the built-in CLK frequency divider
circuit can be reset.
I
–4–
CXA3026Q
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
DVCC1
r/2
15
CLK/T
I
Clock input.
TTL
15 46
1.5V
r
46
RESETN/T
I
DGND1
DVEE3
Reset input.
When left open, this input goes to
high level. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
DVCC1
44
INV
I
TTL
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
44
DGND1
DVEE3
DVCC1
45
Vcc
or
GND
SELECT
Data output mode selection.
(See Table 2. Operating Mode
Table.)
45
DGND1
DVEE3
11
VRT
I
4.0V
(typ.)
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
r1
11
r/2
r
9
VRB +
VRM3
Comparator 1
3 (VRT – VRB)
4
r
r
9
7
4
VRM1
2
(VRT – VRB)
4
7
VRB +
4
Comparator 63
Comparator 64
VRB +
VRM2
r
Comparator 127
Comparator 128
r
Comparator 191
Comparator 192
1
(VRT – VRB)
4
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
r
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
Comparator 255
2
VRB
I
2.0V
(typ.)
r/2
2
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
r2
–5–
CXA3026Q
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
AVCC
Description
Comparator
AVCC
6
VIN
I
VRT
to
VRB
Analog input.
DVEE3
33
to
40
P1D0
to
P1D7
O
21
to
28
P2D0
to
P2D7
O
Vref
6
AGND
Port 1 side data output.
DVCC1
DVCC2
21 to 28
TTL
100K
33 to 40
DGND1
43
CLKOUT
Port 2 side data output.
43
DGND2
DVEE3
Clock output.
(See Table 2. Operating Mode Table.)
O
–6–
CXA3026Q
Electrical Characteristics
(DVCC1, 2, AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Resolution
EIL
EDL
Analog input
Analog input capacitance
Analog input resistance
Analog input current
CIN
RIN
IIN
Reference input
Reference resistance
Reference current
Offset voltage VRT side
VRB side
Rref∗3
Iref∗4
EOT
EOB
Digital input (ECL, PECL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
Digital input (TTL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
VIH = 3.5V
VIL = 0.2V
–50
–500
VOH
VOL
IOH = –2mA
IOL = 1mA
2.4
Fc
Taj
Tds
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
Tf
DMUX mode
120
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Clock high pulse width
Clock low pulse width
RESETN_CLK setup
RESETN_CLK hold time
CLKOUT output delay
Data output delay
Output rise time
Output fall time
Max.
8
DC characteristics
Integral linearity error
Differential linearity error
Digital output (TTL)
Digital output voltage : High
: Low
Typ.
VIN = 2Vp-p, Fc = 5MSPS
VIN = +3.0V + 0.07Vrms
bits
±0.5
±0.5
LSB
LSB
50
500
pF
kΩ
µA
155
28
15
10
Ω
mA
mV
mV
DGND3 – 0.5
DGND3 – 1.4
V
V
V
µA
µA
pF
21
4
0
75
9.7
2
2
115
17.4
DGND3 – 1.05
DGND3 – 3.2
DGND3 – 1.2
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
–50
–75
+50
0
5
0
0
5
V
V
V
µA
µA
pF
0.5
V
V
2.0
0.8
1.5
CLK
CLK
RESETN – CLK
RESETN – CLK
DMUX mode
0.8 to 2.0V
0.8 to 2.0V
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
∗ These characteristics are for PECL input,unless otherwise specified.
–7–
3
3.2
3.2
3.5
0
4.5
T∗5
6.5
10
4.5
7
T+1
8
2
2
Unit
6
8
T+2
10
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CXA3026Q
Item
Symbol
Conditions
Dynamic characteristics
Input bandwidth
S/N ratio
Min.
VIN = 2Vp-p, –3dB
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Error > 16LSB
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Error > 16LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
Straight mode
Error > 16LSB
ICC
IEE
Pd∗7
125
0.4
660
∗3 Rref: Resistance value between VRT and VRB
∗4 Iref = VRT – VRB
Rref
∗5 T = 1
Fc
∗6 TPS: Times Per Sample
2
∗7 Pd = (ICC + IEE) · VCC + (VRT – VRB)
Rref
INV
VIN
Step
1
D7
VRT
VRM2
VRB
255
254
..
.
128
127
..
.
1
0
1 1 1 1 1
1 1 1 1 1
..
.
1 0 0 0 0
0 1 1 1 1
..
.
0 0 0 0 0
0 0 0 0 0
0
D0 D7
1 1 1
1 1 0
0 0 0
1 1 1
0 0 1
0 0 0
D0
0 0 0 0 0
0 0 0 0 0
..
.
0 1 1 1 1
1 0 0 0 0
..
.
1 1 1 1 1
1 1 1 1 1
Table 1. I/O Correspondence Table
–8–
0 0 0
0 0 1
1 1 1
0 0 0
1 1 0
1 1 1
Unit
46
MHz
dB
40
dB
{
{
{
Power supply
Supply current
Supply current
Power consumption
Max.
150
{
{
Error rate
Typ.
145
0.6
760
10–12
TPS∗6
10–9
TPS
10–9
TPS
185
0.8
960
mA
mA
mW
CXA3026Q
Electrical Characteristics Measurement Circuit
Sampling Delay Measurement Circuit
Aperture Jitter Measurement Circuit
Current Consumption Measurement Circuit
100MHz
5V
5V
Icc
4V
IEE
AVCC
DVCC1
DVCC2
VRT
Amp
OSC1
φ: Variable
DGND3
VIN
fr
8
Logic
Analizer
CXA3026Q
CLK
1.95V
VIN
CLK/E
5MHz PECL
1024
samples
OSC2
ECL
Buffer
DGND2
DGND1
AGND
VRB
2V
100MHz
DVEE3
Aperture Jitter Measurement Method
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
+V
VRT
VIN
VRM2
S2
VRB
S1: ON when A < B
S2: ON when A > B
S1
CLK
VIN
A<B A>B
Comparator
VIN
CXA3026Q
8
A8
to
A1
B8
to
B1
A0
B0
“0”
8
Buffer
CLK
000···00
to
111···10
Controller
Where σ (LSB) is the deviation of the output codes when
the largest slew rate point is sampled at the clock which
has exactly the same frequency as the analog input
signal, the aperture jitter Taj is:
Taj = σ/
Error Rate Measurement Circuit
VIN
Fc
–1kHz
4
2Vp-p Sin Wave
8
CLK
B
CLK
+
16LSB
Signal
Source
∆υ
∆t
= σ/ ( 256 × 2πf )
2
A
Latch
CXA3026Q
σ (LSB)
Sampling timing fluctuation
(= aperture jitter)
“1”
DVM
Signal
Source
129
128
127
126
125
∆υ
∆t
–V
1/8
Fc
–9–
Latch
Comparator
A>B
Pulse
Counter
CXA3026Q
Description of Operating Modes
The CXA3026Q has two types of operating modes which are selected with Pin 45 (SELECT).
Operating
mode
SELECT
Maximum
conversion rate
Data output
Clock output
DMUX mode
VCC
120MSPS
Demultiplexed output
60Mbps
The input clock is 1/2 frequency divided
and output.
60MHz
Straight mode
GND
100MSPS
Straight output
100Mbps
The input clock is inverted and output.
100MHz
Table 2. Operating Mode Table
1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)
Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock,
which has adequate setup time and hold time for the output data, is output from the CLKOUT pin.
When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the
RESETN pin (Pin 46or 48). The RESET signal requires the setup time (T_rs ≥ 3.5ns) and hold time (T_rh ≥
0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET
signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge.
The reset period can be extended by making the low level period of the RESET signal longer because the
clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start
timing is regarded as not important, the timing where the RESET signal is set from high to low is not so
consequence. However, when the reset is released this timing must become significant because the timing is
used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at FC (min.) = 120MSPS in this mode.
– 10 –
CXA3026Q
When the RESET signal is not used.
AAA
AAA
AAA
AAA
AAA
CLK
CXA3026Q
CLK
CLK
A A
CLKOUT
8bits
DATA
RESETN
CXA3026Q
CLK
B B
CLKOUT
8bits
DATA
RESETN
When the RESET signal is used.
AAA
AAA
AAA
AAA
AAA
CLK
RESET signal
CXA3026Q
CLK
A
CLK
CLKOUT
DATA
RESETN
CXA3026Q
B
CLK
RESET signal
RESETN
(Reset period)
8bits
CLKOUT
(Reset period)
8bits
DATA
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3026Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
RESET signals) level.
Digital input level
DVEE3
DGND3
ECL
PECL
TTL
–5V
0V
0V
0V
+5V
+5V
Supply voltage Application circuits
±5V
+5V
+5V
Table 3. Logic Input Level and Power Supply Settings
– 11 –
(1) (4)
(2) (5)
(3) (6)
CXA3026Q
Application Circuit 1
(1) DMUX ECL input
+5V(D)
DG
4V
DG AG AG
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
8-bit Digital Data
P1D0 to P1D7
8-bit Digital Data
Latch
DG
36
2
+5V(D)
1
DG
2V
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
+5V(A)
–5V(D)
AG AG
AG
ECL RESET signal
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
Latch
13 14 15 16 17 18 19 20 21 22 23 24
ECL-CLK
DG
+5V(D)
(2) DMUX PECL input
+5V(D)
DG
PECL RESET signal
34
33
4V
+5V(D)
AG AG
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
8-bit Digital Data
Latch
DG
3
4
P1D0 to P1D7
8-bit Digital Data
+5V(D)
35
DG
36
2
+5V(A)
2V
+5V(A)
AG AG DG
AG
48 47 46 45 44 43 42 41 40 39 38 37
1
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
Latch
13 14 15 16 17 18 19 20 21 22 23 24
PECL-CLK
DG
+5V(D)
(3) DMUX TTL input
+5V(D)
DG
4V
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
TTL-CLK
DG
+5V(D)
– 12 –
P1D0 to P1D7
8-bit Digital Data
8-bit Digital Data
Latch
DG
36
2
+5V(D)
+5V(D)
+5V(A)
AG AG
1
DG
2V
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
AG
AG AG DG
TTL RESET signal
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
Latch
CXA3026Q
(4) Straight ECL input
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
P1D0 to P1D7
8-bit Digital Data
8-bit Digital Data
Latch
DG
36
2
+5V(D)
1
DG
2V
4V
+5V(A)
DG AG AG
+5V(D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
AG
–5V(D)
AG AG
DG
13 14 15 16 17 18 19 20 21 22 23 24
ECL-CLK
ECL → TTL
DG
+5V(D)
(5) Straight PECL input
DG
+5V(D)
DG
4V
+5V(D)
AG AG
3
34
4
33
5
32
6
31
7
30
8
29
9
28
P1D0 to P1D7
8-bit Digital Data
8-bit Digital Data
Latch
DG
35
+5V(D)
36
2
DG
+5V(A)
2V
+5V(A)
AG AG DG
AG
48 47 46 45 44 43 42 41 40 39 38 37
1
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
PECL-CLK
PECL → TTL
DG
+5V(D)
(6) Straight TTL input
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
TTL-CLK
DG
+5V(D)
– 13 –
P1D0 to P1D7
8-bit Digital Data
DG
36
2
+5V(D)
1
DG
2V
4V
+5V(D)
AG AG
+5V(D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
+5V(A)
+5V(A)
AG AG DG
AG
DG
8-bit Digital Data
Latch
CXA3026Q
Application Circuit 2
Straight Mode TTL I/O (When a single power supply is used)
A
AG
Analog
input
AG
4V
+5V (A)
AG
2V
1µF
1µF
AG
AG
short
10µF
10µF
11
10
9
8
7
6
5
4
3
2
VRT
AGND
VRM3
AVCC
VRM2
VIN
AVCC
VRM1
AGND
VRB
13 CLK/E
12
DGND3
short
1
DVEE3
+5V
(D) DG
RESETN/E 48
14 CLKN/E
RESET/E 47
RESETN/T 46
15 CLK/T
17 N.C.
INV 44
18 N.C.
CLKOUT 43
19 DVCC2
DVCC2 42
20 DGND2
DGND2 41
P1D3
32
33
34
35
36
P1D3
31
P1D2
30
P1D2
29
P1D1
28
P1D1
27
P1D0
DVCC2
26
(LSB) P1D0
DVCC1
25
DGND2
DGND1
P1D4 37
P2D7
24 P2D3
(MSB) P2D7
P1D5 38
P2D6
23 P2D2
P2D6
P1D6 39
P2D5
22 P2D1
P2D5
P1D7 40
P2D4
21 P2D0
P1D6
(MSB) P1D7
SELECT 45
P1D4
P1D5
16 N.C.
P2D4
P2D2
P2D3
(LSB) P2D0
P2D1
TTL CLK
Short the analog system and digital system at one point immediately
under the A/D converter. See the Notes on Operation.
is the chip capacitor of 0.1µF.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 14 –
CXA3026Q
DMUX Mode Timing Chart (Select = VCC)
Tds
N–1
N+6
4.5ns (typ.)
N+5
VIN
N+3
N
T
N+7
N+4
N+2
N+1
CLK
Tpw1
Tpw0
Tdo2; 8ns (typ.)
6.5ns (min.)
10ns (max.)
P1D0 to D7
2.0V
N+1
N+3
0.8V
2.0V
N
P2D0 to D7
N+2
0.8V
Tdo1
Td_clk; 7ns (typ.)
T + 1ns (typ.)
8ns (max.)
AA
AA
AA
AA AAAA
4.5ns (min.)
CLK OUT
(Reset period)
2.0V
2.0V
2.0V
0.8V
0.8V
0.8V
4.5ns (min.)
8ns (max.)
T_rh
T_rs
T_rh
T_rs
Td_clk
RESET signal
– 15 –
≈T
≈T
CXA3026Q
Straight Mode Timing Chart (Select = GND)
N+2
N–1
N+1
VIN
N+3
Tds
4.5ns (typ.)
N
T
CLK
Tpw1
Tpw0
Tdo2; 8ns (typ.)
6.5ns (min.)
10ns (max.)
P1D0 to D7
N–4
2.0V
N–3
N–2
N–1
N
N–4
N–3
N–2
N–1
0.8V
P2D0 to D7
N–5
2.0V
0.8V
Td_clk; 7ns (typ.)
4.5ns (min.)
8ns (max.)
CLK OUT
(CLK is inverted and output.)
2.0V
0.8V
RESET signal
– 16 –
CXA3026Q
Timing of A/D Converter and Peripheral Circuit
In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is
described in detail as below.
For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data
delay are showed in the following specification, i.e.
Td_clk
4.5ns (min.) to 8.0ns (max.)
Tdo2
6.5ns (min.) to 10ns (max.)
These values are considered in all the temperature change and power supply variation. When the maximum
clock rate 120MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the
3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be
changed in same trend at the same condition of the temperature change and power supply variation. As a
result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also,
0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay
can be omitted in this case.
When Ta = 25°C, VCC = +5V, the clock delay and data delay are
Td_clk
5.0ns (min.) to 7.5ns (max.)
Tdo2
7.0ns (min.) to 9.5ns (max.)
The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the
set-up time for the data latching can be obtained as ts (min.) = 3.5ns. The output delay change of the DATA OUT
and CLK OUT due to the temperature change and the power supply variation should have the same trend of
the delay change, the minimum ts = 3.5ns can be guaranteed at any temperature change and power supply
variation.
Analog input R
Analog input G
Analog input B
CLK
RESET
CXA3026Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
CXA3026Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
CXA3026Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
8bit
8bit
Gate Array
Latch
8bit
8bit
8bit
8bit
8ns
( = 1/120MSPS)
CLK
th-reset
RESET signal
Td_clk (min.)
5.0ns
<4.5ns>
CLK OUT
Td_clk (max.)
7.5ns
<8.0ns>
Tdo2 (min.)
7.0ns
<6.5ns>
Tdo2 (min.)
9.5ns
<10ns>
ts (min.)
3.5ns
th (min.)
7.5ns
P1D/out
P2D/out
16ns
Note: In the timing chart, the values in the brackets < > are included all the temperature change and the
power supply variation.
– 17 –
CXA3026Q
Notes on Operation
• The CXA3026Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input.
Characteristic impedance should be properly matched to ensure optimum performance during high-speed
operation.
• The power supply and grounding have a profound influence on converter performance. The power supply
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
ground patterns wider at an inner layer using a multi-layer board.
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one
place immediately under the A/D converter improves A/D converter performance.
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
to AGND with approximately 1µF tantal capacitor and, 0.1µF chip capacitor as short as possible.
• If the CLK/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as threshold
voltage VBB as it is too weak.
• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When
the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.
– 18 –
CXA3026Q
Example of Representative Characteristics
Current consumption vs.
Ambient temperature characteristics
Current consumption vs.
Conversion rate characteristics response
170
Current consumption [mA]
Current consumption [mA]
170
160
150
140
160
fin =
150
fCLK
– 1kHz
4
DMUX mode
CL = 5pF
140
130
130
–25
25
75
60
0
Ta – Ambient temperature [°C]
Fc – Conversion rate [MSPS]
Analog input current vs.
Analog input voltage characteristics
Reference current vs.
Ambient temperature characteristics
120
20
Reference current [mA]
Analog input current [µA]
200
VRT = 4V
VRB = 2V
100
15
10
0
2
3
4
–25
Analog input voltage [V]
25
Ta – Ambient temperature [°C]
– 19 –
75
CXA3026Q
SNR vs. Input frequency response
Error rate vs. Conversion rate characteristics
50
10–6
10–7
Error Rate [TPS]
SNR [dB]
40
30
Fc = 120MSPS
fin =
fCLK
– 1kHz
4
Error > 16LSB
10–8
10–9
10–10
20
1
3
10
5
30
50
Input frequency [MHz]
Fc – Maximum conversion rate [MSPS]
170
fCLK
– 1kHz
4
Error > 16LSB
Error rate: 10–9 TPS
fin =
150
140
130
–25
25
140
Fc – Conversion rate [MSPS]
Maximum conversion rate vs.
Ambient temperature characteristics
160
120
75
Ta – Ambient temperature [°C]
– 20 –
160
CXA3026Q
CXA3026Q Evaluation Board
Description
The CXA3026Q Evaluation Board is a special board designed to maximize and facilitate the evaluation
performance of the CXA3026Q. After latching the CXA3026Q output data with a frequency divided clock, the
analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be
extracted externally via a 24-pin cable connector.
Features
• Resolution:
• Maximum conversion rate:
• Supply voltage:
• Dual analog input pins:
8 bits
120MSPS (min.)
±5.0V
DIR.IN: AC coupling input pin
AMP.IN: Operational amplifier input pin
• Clock frequency division: 1/1 to 1/16
Absolute Maximum Ratings
• Supply voltage VCC
VEE
+AMP
–AMP
–0.5 to +7.0
–7.0 to +0.5
–0.5 to +7.0
–7.0 to +0.5
Recommended Operating Conditions
• Supply voltage VCC
GND
VEE
+AMP
–AMP
| (+AMP) – (–AMP) |
• Analog input
AMP. IN
DIR. IN
• Clock input
CLK. IN
V
V
V
V
Min.
+4.75
–5.50
+3
–7
9
–0.75
1.5
0.8
– 21 –
Typ.
+5.0
0
–5.0
+5
–5
10
0
2.0
1.0
Max.
+5.25
–4.75
+7
–3
11
+1.05
2.2
1.2
V
V
V
V
V
V
V
Vp-p
Vp-p
CLK IN
AMP IN
DIR IN
DGND
51Ω
AGND
82Ω
AGND
51Ω
– AMP + AMP
DGND
CON3
AGND
CON1
AGND
CON2
CON6
VEE
0.1µF
1kΩ
VBB
× (–2)
VCC
1kΩ
390Ω
AGND
GND
130Ω
270Ω
Vrt
Vrb
Vrb
Vrt
B
S1
A
(PECL)
4
(PECL)
OFFSET
OFFSET. R3
SW1
P1D0 to D7
VRB
S2
CLKOUT
P2D0 to D7
(TTL)
4
CLK
INV
D/A
INV
SW3
NORM
SW2
A/D
INV
VIN CXA3026Q
VRT
Straight
SELECT
DMUX
P1 side DATA
CON7
(TTL)
(TTL)
8
(TTL)
8
LATCH
LATCH
VRT. R2
Counter
P2 side DATA
CON8
(TTL)
8
(TTL)
8
TTL/ECL
TTL/ECL
VRB. R1
PECL/TTL
– 22 –
TTL/ECL
(ECL)
(ECL)
8
(ECL)
8
AGND
CON5
AGND
CON4
D/A OUT
(–1.0V)
P2 side OUT
P1 side OUT
D/A OUT
(–1.0V)
FULL SCALE. R4 FULL SCALE. R5
DAC
DAC
Block Diagram
CXA3026Q
CXA3026Q
Pin Description and I/O Level
Pin No.
Symbol
I/O
Standard
I/O level
Current
Description
CON1
AMP. IN
I
0.95Vp-p
Doubles the analog input signal amplitude using the
operational amplifier. The input impedance is 50Ω.
CON2
DIR. IN
I
2.0Vp-p
AC coupling input. Suitable for sine waves and other
repeating waveforms. The input impedance is 50Ω.
CON3
CLK. IN
I
1.0Vp-p
The CXA3026Q operates at the PECL level clock
using the sine wave-to-PECL conversion circuit.
The input impedance is 50Ω.
CON4
P1 side OUT
O
0 to –1V
Allows the D/A converted waveform of the
CXA3026Q port 1 side data to be observed.
The output impedance is 50Ω.
CON5
P2 side OUT
O
0 to –1V
Allows the D/A converted waveform of the
CXA3026Q port 2 side data to be observed.
The output impedance is 50Ω.
VCC
I
+5.0V
GND
I
0V
VEE
I
–5.0V
–0.6A
+AMP
I
+5.0V
40mA
+ side power supply for the operation amplifier.
–AMP
I
–5.0V
–40mA
– side power supply for the operation amplifier.
CON7
P1 side DATA
O
TTL
The CXA3026Q port 1 side data output is latched at
the frequency divided clock and then output.
CON8
P2 side DATA
O
TTL
The CXA3026Q port 2 side data output is latched at
the frequency divided clock and then output.
CON6
0.8A
The inside of the board is divided into analog and
digital systems.
Board Adjustments and Settings
1. VRB.R1:
CXA3026Q VRB voltage adjusting volume.
2.
3.
VRT.R2:
OFFSET.R3:
4.
5.
6.
FULL SCALE.R4:
FULL SCALE.R5:
S1:
CXA3026Q VRT voltage adjusting volume.
Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the
CXA3026Q input range.
Full-scale adjusting volume for the port 1 D/A output. (–1V: Typ.)
Full-scale adjusting volume for the port 2 D/A output. (–1V: Typ.)
Switching junction for the dual analog input pins.
Set as follows according to the input pins used.
Junction
A
B
AMP.IN
OPEN
SHORT
DIR.IN
0.1µF
10kΩ
Symbol
7.
S2:
8. SW1 SELECT:
9. SW2 A/D INV:
10. SW3 D/A INV:
Setting junction for the clock frequency division ratio. The operating speed after
latching is determined by the frequency division ratio set here.
When set to CLK OUT, it operates according to the CXA3026Q clock output.
CXA3026Q output mode selector switch.
CXA3026Q output polarity inversion switch.
D/A converter output polarity inversion switch.
– 23 –
CXA3026Q
Notes on Board Operation
1.
The factory settings for the CXA3026Q Evaluation Board are as follows.
VRB.R1 = 1.5V
VRT.R2 = 3.0V
OFFSET.R3 = 2.25V
FULL SCALE.R4 = –1V
FULL SCALE.R5 = –1V
S1 A ... OPEN, B ... SHORT
S2 8 ... SHORT (1/8 frequency division)
When using the board in this condition, the input signals should be input at the amplitudes shown below.
(The frequency is set as desired.)
Analog input signal: CON1 (AMP.IN)
0V center, 800mVp-p or less
Clock input signal: CON3 (CLK.IN)
0V center, 1.0Vp-p
2.
When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range
of the A/D converter's analog input signal according to the +AMP and –AMP supply voltages. The power
supply for the operational amplifier can also be shifted to +AMP = +7.0V and –AMP = –3.0V to allow use
with a wider input dynamic range.
3.
When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the
CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited by the +AMP
and –AMP supply voltages, but the VRT level may be limited by IC3:NJM3403A. Therefore, the power
supply for the operational amplifier should be shifted in the same manner as in 2. above.
4.
In the evaluation board of the CXA3026Q, CLC404 (Comlinear) is employed for IC2 to drive the analog
input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little
change in the peripheral circuit in this case.
– 24 –
CXA3026Q
CXA3026Q Evaluation Board Timing Chart
N
N+3
N+1
CON2
DIR IN
2Vp-p
0V
N+2
CON3
CLK IN
CXA3026Q
CLK
1Vp-p
0V
(PECL)
CXA3026Q
P1 side DATA
N–4
N–3
N–2
N–1
(TTL)
Approximately 6.0ns
CON7
P1 side DATA
CLK
(TTL)
CON7
P1 side DATA
DATA
(TTL)
Approximately 9.0ns
N–6
N–4
N–2
N–6
CON4
P1 side OUT
N–4
N–2
(Analog regeneration waveform)
0 to –1V
Operating Conditions
CXA3026Q operating mode : Straight mode
: DIR IN pin input
Analog input
: 1/2 frequency divided clock
S2 setting
– 25 –
CXA3026Q
Circuit Diagram
CON6
–AMP
+AMP
VEE
L1
C1
33µF
–AMP
C2
33µF
+AMP
GND
L2
L3
C3
33µF
VCC
L4
L5
C4
33µF
AVEE
DVEE
C5
33µF
AGND
DGND
L6
C6
33µF
AVCC
DVCC
SW3
DGND
D/A INV
SW2
C28
0.1µF
A/D INV
SW1
DVCC
DGND
DVCC
SELECT
AGND
–AMP
AGND
C29
0.1µF
–AMP
D/A INV
CLKOUT
C7
1µF
C16
0.1µF
C8
1µF
C17
0.1µF
P1D7
P1D6
P1D5
AGND
P1D4
P1D3
4
R13
82
AGND
2
3
R14
130
AGND
R16
4 270
6
R17
43
AGND
C12
1µF
IC3C
NJM3403A
10
8
9
C24
0.1µF
C26
0.1µF
C21
0.1µF
DVCC
C27
0.1µF
C18
0.1µF
C10
1µF
P1D4
P1D5
P1D6
P1D7
DVCC2
DGND2
INV
CLKOUT
SELECT
DGND1 29
9 VRM3
P2D7 28
10 AGND
P2D6 27
11 VRT
P2D5 26
12 DGND3
P2D4 25
C19
0.1µF
DGND
C34 0.1µF
P2D7
P2D6
P2D5
13 14 15 16 17 18 19 20 21 22 23 24
AGND
+AMP
AGND
P2D4
+AMP
P2D3
C30
0.1µF
DVCC
P2D2
DVCC
R28 R29
82 82
CON3
CLK IN
DGND
IC4B
10H116 (PECL)
C15
0.1µ
R19
51
DGND
7
6
10
9
R20
1k
R21
390
R23
82
R22
1k
IC4A
10H116 (PECL)
5
4
3
2
13
12
R30
82
15
14
P2D1
P2D0
DGND
R27
130
R24
130
DGND
11
IC4D
10H116 (PECL)
IC4C
10H116 (PECL)
DGND
DVCC
DVCC1 30
8 AVCC
DGND
C9
1µF
C33 0.1µF
DVCC2 31
IC1
CXA3026Q
7 VRM2
AGND C22
0.1µF
IC2
7 CLC404
DGND2 32
6 VIN
AVCC
S1
P1D0 33
5 AVCC
P2D3
CON1
AMP IN
P1D1 34
4 VRM1
P2D2
AVCC
P1D2 35
3 AGND
P2D1
B
P1D3 36
P2D0
AGND
C23
C25
0.1µF 0.1µF
AGND
P1D0
2 VRB
DGND2
A
P1D1
1 DVEE3
DVCC2
CON2
DIR IN
C20
0.1µF
N.C.
R15
270
C11
1µF
R18
51
N.C.
R6
51
AGND
N.C.
IC3A
NJM3403A
AGND
RESET/E
1
DGND
RESETN/T
11
2
3
R11
200k
IC3B
NJM3403A
6
7
5
CLK/T
R10
22k
R12
390k
RESETN/E
R8
510
R2
1k
R3
10k
P1D2
48 47 46 45 44 43 42 41 40 39 38 37
CLKN/E
D1
TL431CP
R9
7.5k
CLK/E
R7
510
R1
2k
R25 R26
130 130
13 CLK
Cout 4
DGND
DVCC
9 S1
7 S2
IC5
10H136 (PECL)
12 D0
Q3 3
11 D1
Q2 2
6 D2
Q1 15
5 D3
Q0 14
1/16
1/8
1/4
1/2
CLK
CLKN
– 26 –
CXA3026Q
DGND DVcc
1
2
C35
0.1µF
IC14
74ALS34
3
4
P1D7
P1D6
5
6
P1D5
9
8
P1D4
11
10
P1D3
13
12
P1D2
P1D1
1
3
2
4
P1D0
5
6
IC14
74ALS34
1
2
CON7
P1 side DATA
IC15
74ALS34
25 26
DGND
DGND
C43
0.1µF
DGND
R47
620
1 OC
AGND
16 S
11 CLK
DVEE
P1D7
P1D6
P1D5
2 1D
1Q 19
3 2D
2Q 18
4 3D
P1D4
P1D3
P1D2
P1D1
P1D0
IC6
74AS574
3Q 17
5 4D
4Q 16
6 5D
5Q 15
7 6D
6Q 14
8 7D
7Q 13
9 8D
8Q 12
P1D7
P1D6
P1D5
11 IN8
OUT8 10
1 MSB
AGND 28
12 IN7
OUT7 9
2 D2
VREF 27
OUT6 8
3 D3
AVEE 26
OUT5 7
4 D4
NC 25
17 IN4
OUT4 4
5 D5
NC 24
13 IN6
P1D4
IC9
MB767
14 IN5
P1D3
P1D2
P1D1
P1D0
18 IN3
OUT3 3
6 D6
19 IN2
OUT2 2
7 D7
20 IN1
OUT1 1
8 D8
R48
620
C44
0.1µF
R37
82
C13
1µF AVEE
NC 21
AGND
CON4
P1 side OUT
NC 19
10 LSB
DVEE
C52
0.1µF
NC 22
OUT 20
9 D9
R43
270
D2
TL431CP
NC 23
IC12
CX20201-1
R4 R42
2k 1k
C51
0.1µF
11 NC
AGND 18
12 NC
DGND 17
AGND
DGND
C53
0.1µF
INV 16
13 CLKN
DVEE 15
14 CLK
DVEE
DGND
R38
82
R49
620
C45
0.1µF
DGND
1 OC
16 S
11 CLK
DVEE
P2D7
P2D6
P2D5
2 1D
1Q 19
3 2D
2Q 18
4 3D
P2D4
P2D3
P2D2
P2D1
P2D0
IC7
74AS574
P2D7
P2D6
P2D5
3Q 17
5 4D
4Q 16
6 5D
5Q 15
7 6D
6Q 14
8 7D
7Q 13
9 8D
8Q 12
11 IN8
OUT8 10
1 MSB
AGND 28
OUT7 9
2 D2
VREF 27
OUT6 8
3 D3
AVEE 26
OUT5 7
4 D4
NC 25
17 IN4
OUT4 4
5 D5
NC 24
IC10
MB767
14 IN5
P2D3
P2D2
P2D1
P2D0
AGND
12 IN7
13 IN6
P2D4
R39
130
R40
130 DVEE
18 IN3
OUT3 3
6 D6
19 IN2
OUT2 2
7 D7
20 IN1
OUT1 1
8 D8
9 D9
10 LSB
DVEE
D/A INV
CLKOUT
R50
620
C46
0.1µF
19 OE
DGND
1 D0N
1/16
22 D1N
21 D2
20 D2N
1/4
16 D3
IC8
100390
DGND 17
AGND
DGND
C56
0.1µF
INV 16
DVEE 15
DVEE
14 D4
CLK
12 D5
11 D5N
DVCC
7 A2
1/4
10 A3
R32 82
R35 130
R36 130
DGND
Y2 3
C50
0.1µF
Y3 15
Y3 12
DGND
R41
620
Y4 14
11 A4
1/2
Y4 13
Q4 9
DVEE
1/1
DVCC
Q5 10
1
2
S2
P2D7
IC15
74ALS34
8
9
P2D6
11
10
P2D5
13
12
P2D4
1
2
P2D3
3
4
P2D2
5
6
P2D1
9
8
P2D0
11
10
R34 130
R33 82
Y2 1
IC11
10H124
Q3 8
13 D4N
CLKN
1/8
Y1 4
Q2 4
15 D3N
1/2
5 A1
Q1 3
23 D1
1/8
DGND
12 NC
Y1 2
1/16
C39
0.1µF
CON8
P2 side DATA
IC16
74ALS34
25 26
DGND
– 27 –
CON5
P2 side OUT
NC 19
6 B
CLKOUT
Q0 2
24 D0
DGND
C32
0.1µF
AGND
17 VBB
R46
620
R31 82
NC 21
OUT 20
AGND 18
14 CLK
C14
1µF AVEE
NC 22
11 NC
13 CLKN
DGND
R45
270
D3
TL431CP
C55
0.1µF
NC 23
IC13
CX20201-1
R5 R44
2k 1k
C54
0.1µF
CXA3026Q
Component List
No.
Product name
IC1
CXA3026Q
IC2
CLC404AJE
IC3
NJM3403AM
IC4
MC10H116L
IC5
MC10H136L
IC6, 7
74AS574N
IC8
100390
IC9, 10
MB767P
IC11
MC10H124L
IC12, 13
CXA20201A-1
IC14 to 16
74ALS34
D1 to 3
TL431CP
SW1 to 3
ATE1D-2F3-10
S1, 2
JX-1
CON1 to 5
01K0315
CON6
TJ-563
CON7, 8
(FAP-2601-1202)
L1 to 6
ZBF503D-00
C1 to 6
Tantal capacitor
C7 to 12
Tantal capacitor
C15
Ceramic capacitor
All parts other than those listed above
Chip capacitor
Function
8-bit A/D converter
OP-AMP
OP-AMP
ECL Buffer
ECL Countor
TTL Latch
PECL → TTL conversion
TTL → ECL conversion
TTL → ECL conversion
10-bit D/A converter
TTL Buffer
Shunt regulator
Toggle switch
Short pin
BNC connector
Power supply connector
Flat cable connector
Ferrite-bead filter
33µF
1µF
0.1µF
No.
R2
R1, 4, 5
R3
R46 to 50
Product name
RJ-5W-1K
RJ-5W-2K
RJ-5W-10K
RGLD4X621J
Function
1kΩ volume resistor
2kΩ volume resistor
10kΩ volume resistor
620Ω network resistor
R6, 18, 19
R7.8
R9
R10
R11
R12
R13, 23, 28 to 33, 37, 38
R14, 24 to 27, 34 to 36, 39, 40
R15, 16, 43, 45
R17
R20, 22, 42, 44
R21
R41
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
51Ω
510Ω
7.5kΩ
22kΩ
200kΩ
390kΩ
82Ω
130Ω
270Ω
43Ω
1kΩ
390Ω
620Ω
0.1µF
∗ CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.)
CXA3026Q/AQ EVALUATION BOARD
Component side silk diagram
– 28 –
74ALS34
74ALS34
74ALS34
CXA3026Q/AQ
CXA3026Q
Component side pattern diagram
Solder side pattern diagram
– 29 –
CXA3026Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
SONY CODE
QFP-48P-L04
LEAD TREATMENT
EIAJ CODE
∗QFP048-P-1212-B
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 30 –