SONY CXA3106AQ

CXA3106AQ
PLL IC for LCD Monitor/Projector
Description
The CXA3106AQ is a PLL IC for LCD monitors/
projectors with built-in phase detector, charge pump,
VCO and counter.
The various internal settings are performed by
serial data via a 3-line bus.
Applicable LCD monitor/projector resolution are
NTSC, PAL, VGA, SVGA, XGA, and SXGA etc.
48 pin QFP (Plastic)
Functions
• Phase detector enable
• UNLOCK output
• Output TTL disable function
• Power save function (2 steps)
TTLGND
TTLVCC
PECLVCC
IOGND
CLK/2L
CLK/2H
CLKL
Applications
• CRT displays
• LCD projectors
• LCD monitors
• Multi-media
CLKH
DSYNCL
DSYNCH
VBB
Pin Configuration (Top View)
PECLVCC
Features
• Supply voltage: 5V ± 10% single power supply
• Package: 48-pin QFP
• Power consumption: 350mW
• Sync input frequency: 10 to 100kHz
• Clock output signal frequency: 10 to 160MHz
• Clock delay: 1/16 to 20/16 CLK
• Sync delay: 1/16 to 20/16 CLK
• I/O level: TTL, PECL (complementary)
• Low clock jitter
• 1/2 clock output
36 35 34 33 32 31 30 29 28 27 26 25
24 DSYNC
IOGND 37
23 CLK
IOVCC 38
PLLVCC 39
22 CLKN
PLLGND 40
21 CLK/2
VCOVCC 41
20 CLK/2N
VCOGND 42
19 DGND
18 DVCC
VCOHGND 43
IREF 44
17 UNLOCK
RC2 45
16 DIVOUT
RC1 46
15 SEROUT
14 CS
IRGND 47
13 TLOAD
VCOL
VCO
8
9 10 11 12
SCLK
VCOH
7
SDATA
IOGND
6
SYNC
5
SENABLE
4
SYNCL
3
SYNCH
2
HOLD
1
IOVCC
IRVCC 48
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97812A03
CXA3106AQ
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
•
•
•
•
•
IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC,
VCOVCC, IRVCC,
–0.5 to +7.0
IOGND, DGND, TTLGND, VCOHGND, PLLGND,
VCOGND, IRGND
–0.5 to +0.5
Input voltage
VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD,
SYNC, SENABLE, SCLK, SDATA, TLOAD, CS
IOGND – 0.5 to IOVCC + 0.5
RC2
IRGND – 0.5 to IRVCC + 0.5
Output current
SEROUT, DIVOUT, UNLOCK, CLK/2N, CLK/2,
CLKN, CLK, DSYNC, CLK/2L, CLK/2H, CLKL,
CLKH, DSYNCH, DSYNCL, VBB
–30 to +30
IREF, RC1
–2 to +2
Storage temperature Tstg
–65 to +150
Operating ambient temperature
Ta
–25 to +75
Allowable power dissipation
750
PD
V
V
V
V
mA
mA
°C
°C
mW
Recommended Operating Conditions
IOVCC, DVCC, TTLVCC, PECLVCC,
PLLVCC, VCOVCC, IRVCC
IOGND, DGND, TTLGND, VCOHGND,
PLLGND, VCOGND, IRGND
• Digital input
DIN (PECL) ∗1 H level
DIN (PECL) ∗1 L level
DIN (TTL) ∗2 H level
DIN (TTL) ∗2 L level
• SYNC, SYNCH, SYNCL input jitter
• Operating temperature
Ta
Min.
Typ.
Max.
4.75
5.00
5.25
V
–0.05
IOVCC – 1.1
0
0.05
V
IOVCC – 1.5
0.8
1.0
V
V
V
ns
+75
°C
• Supply voltage
∗1 VCOH, VCOL, SYNCH, SYNCL
∗2 VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS
–2–
2.0
–20
TTLIN
PECLIN
SYNC
(TTL)
SYNC
(PECL)
–3–
IREF
DAC
TTLIN
PECLIN
VCO
(PECL)
HOLD
(TTL)
TTLIN
VCO
(TTL)
Block Diagram
SENABLE SCLK
DIVOUT
TTLOUT
1bit
12bit
Programmable
Counter
on/off
SEROUT
VCO
TLOAD
1bit
synthesizer
power save
2bit
2bit
Coarse
Delay
1 to 4 CLK
DIV1, 2, 4
logic
Latch
1bit
MUX
TTLIN
1/256 to 1/4096 CLK
5bit
Fine
Delay
1/16 to 20/16 CLK
RC2
2bit
Charge
Pump
1bit
on/off
read out
TTLOUT
Phase
Detector
1bit
SDATA
CONTROL REGISTER
1bit
Polarity
RC1
CS
whole chip
power save
1/2
RESET
1bit
Polarity
1bit
1bit
1bit
1bit
1bit
PECL
on/off 1bit
unlock
detect
PECLOUT
TTLOUT
on/off
TTLOUT
on/off
PECLOUT
TTLOUT
on/off
TTLOUT
on/off
PECLOUT
TTLOUT
on/off
VBB
UNLOCK
CLK/2
(PECL)
NCLK/2
(TTL)
CLK/2
(TTL)
CLK
(PECL)
NCLK
(TTL)
CLK
(TTL)
DSYNC
(PECL)
DSYNC
(TTL)
CXA3106AQ
CXA3106AQ
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
IOVCC
IOGND
VCOH
VCOL
VCO
HOLD
SYNCH
SYNCL
SYNC
SENABLE
SCLK
SDATA
TLOAD
CS
SEROUT
DIVOUT
UNLOCK
DVCC
DGND
CLK/2N
CLK/2
CLKN
CLK
DSYNC
TTLGND
TTLVCC
IOGND
PECLVCC
CLK/2L
CLK/2H
CLKL
CLKH
DSYNCL
DSYNCH
VBB
PECLVCC
IOGND
IOVCC
PLLVCC
PLLGND
VCOVCC
VCOGND
VCOHGND
IREF
RC2
RC1
IRGND
IRVCC
Description
Digital power supply
Digital GND
External VCO input
External inverted VCO input
External VCO input
Phase detector disable signal input
Sync input
Inverted sync input
Sync input
Control signal (enable)
Control signal (clock)
Control signal (data)
Programmable counter test input
Chip select
Register read output
Programmable counter test output
Unlock signal output
Digital power supply
Digital GND
Inverted 1/2 clock output
1/2 clock output
Inverted clock output
Clock output
Delay sync signal output
TTL output GND
TTL output power supply
Digital GND
PECL output power supply
Inverted 1/2 clock output
1/2 clock output
Inverted clock output
Clock output
Delay sync signal output
Inverted delay sync signal output
PECL reference voltage
PECL output power supply
Digital GND
Digital power supply
PLL circuit analog power supply
PLL circuit analog GND
VCO circuit analog power supply
VCO circuit analog GND
VCO SUB analog GND
Charge pump current preparation
External pin for LPF
External pin for LPF
IREF analog GND
IREF analog power supply
–4–
Reference voltage level
5V
0V
PECL
PECL
TTL
TTL
PECL
PECL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
5V
0V
TTL
TTL
TTL
TTL
TTL
0V
5V
0V
5V
PECL
PECL
PECL
PECL
PECL
PECL
PECLVCC – 1.3V
5V
0V
5V
5V
0V
5V
0V
0V
1.3V
1.7 to 4.4V
2.1V
0V
5V
CXA3106AQ
Pin Description and I/O Pin Equivalent Circuit
Pin
No.
Symbol
I/O
Reference
voltage level
Equivalent circuit
Description
1
IOVCC
—
5V
Digital power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
2
IOGND
—
0V
Digital GND.
18
DVCC
—
5V
Digital power supply.
19
DGND
—
0V
Digital GND.
25
TTLGND
—
0V
TTL output GND.
26
TTLVCC
—
5V
TTL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
27
IOGND
—
0V
Digital GND.
5V
PECL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
28
PECLVCC
—
36
PECLVCC
—
5V
PECL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
37
IOGND
—
0V
Digital GND.
5V
Digital power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
38
IOVCC
—
39
PLLVCC
—
5V
PLL circuit analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
40
PLLGND
—
0V
PLL circuit analog GND.
41
VCOVCC
—
5V
VCO circuit analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
42
VCOGND
—
0V
VCO circuit analog GND.
43
VCOHGND —
0V
VCO SUB analog GND.
47
IRGND
—
0V
IREF analog GND.
5V
IREF analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
48
IRVCC
—
–5–
CXA3106AQ
Pin
No.
3
Symbol
VCOH
I/O
I
Reference
voltage level
Equivalent circuit
PECL
External VCO input.
Programmable counter test input
(switchable by a control register).
When using the VCO PECL input,
open the Pin 5 VCO TTL input.
PECL
External inverted VCO input.
When open, this pin goes to the PECL
threshold voltage (IOVcc – 1.3V).
Only the pin 3 VCOH input with VCOL
input open can be also operated but
complementary input is recommended
in order to realize stable high-speed
operation.
IOVCC
4
VCOL
I
r
7
SYNCH
I
Description
3
7
4
8
r
Sync input.
When using the SYNCH PECL input,
open the Pin 9 SYNC TTL input.
The sync signal can be switched
between positive/negative polarity by
an internal register.
PECL
IOGND
8
SYNCL
I
Inverted sync input.
When open, this pin goes to the PECL
threshold voltage (IOVcc – 1.3V).
Only the Pin 7 SYNCH input with
SYNCL input open can be also
operated but complementary
input is recommended in order to
realize stable high-speed operation.
PECL
–6–
CXA3106AQ
Pin
No.
5
6
9
Symbol
VCO
HOLD
SYNC
I/O
I
I
I
Reference
voltage level
Equivalent circuit
TTL
External VCO input.
Programmable counter test input
(controlled by a control register).
When using the VCO TTL input, open
the Pin 3 VCOH and Pin 4 VCOL
PECL inputs.
TTL
Phase detector disable signal.
Active high. When this pin is high, the
phase detector output is held. This pin
goes to high level when open.
(See the HOLD Timing Chart.)
TTL
IOVCC
r/2
r
5 10
10
SENABLE
I
TTL
6 11
1.5V
2r
9 12
13
12
13
SCLK
SDATA
TLOAD
I
I
I
Sync input.
When using the SYNC TTL input,
open the Pin 7 SYNCH and Pin 8
SYNCL PECL inputs.
The sync signal can be switched
between positive/negative polarity by
a control register.
Control signal (enable) for setting the
internal registers.
When SENABLE is low, registers can
be written; when high, registers can be
read.
(See the Control Register Table and
Control Timing Chart.)
TTL
Control signal (clock) for setting the
internal registers.
When SENABLE is low, SDATA is
loaded to the registers at the rising
edge of SCLK.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Table and
Control Timing Chart.)
TTL
Control signal (data) for setting the
internal registers.
(See the Control Register Table and
Control Timing Chart.)
TTL
Programmable counter test input.
This pin is normally open status and
high. Register contents can be loaded
immediately to Programmable counter
by setting TLOAD low during the
programmable counter test mode.
IOGND
11
Description
–7–
CXA3106AQ
Pin
No.
Symbol
I/O
Reference
voltage level
Equivalent circuit
Description
IOVCC
14
CS
I
Chip select.
When low, all circuits including the
register circuit are set to the power
save mode.
When high, all circuits are set to
operating mode.
TTL
14
IOGND
15
16
SEROUT
DIVOUT
O
O
TTL
Register read output.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Timing
Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTL
Programmable counter test output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
IOVCC
20
CLK/2N
O
TTLVCC
TTL
100k
15 22
16 23
20 24
21
CLK/2
O
TTL
21
TTLGND
IOGND
22
23
24
CLKN
CLK
DSYNC
O
O
O
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTL
Inverted clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTL
Clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
TTL
Delay sync signal output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) and switched
between positive/negative polarity by
a control register.
–8–
CXA3106AQ
Pin
No.
Symbol
I/O
Reference
voltage level
Equivalent circuit
Description
TTLVCC
17
UNLOCK
O
TTL
17
TTLGND
IOGND
29
30
CLK/2L
CLK/2H
O
O
PECL
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
PECL
1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
PECL
Inverted clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
PECLVCC
IOVCC
31
CLKL
O
30 32 34
29 31 33
32
33
34
CLKH
DSYNCL
DSYNCH
O
O
O
Unlock signal output.
This pin is an open collector output,
and pulls in the current when a phase
difference occurs. The UNLOCK
sensitivity can be adjusted by
connecting a capacitor and resistors
to this output as appropriate.
(See the UNLOCK Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
PECL
IOGND
Clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
PECL
Delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
PECL
Inverted delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
–9–
CXA3106AQ
Pin
No.
Symbol
I/O
Reference
voltage level
Equivalent circuit
Description
PECLVCC
35
VBB
O
PECLVCC
–1.3V
35
PECL reference voltage.
When used, ground this pin to the
ground pattern with a 0.1µF ceramic
chip capacitor as close to the pin as
possible.
IOGND
IRVCC
44
IREF
O
Charge pump current preparation.
Connect to GND via an external
resistor (1.6kΩ).
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor
as close to the pin as possible.
1.3V
44
IRGND
IOGND
45
RC2
O
1.7
to
4.4V
IRVCC
VCOVCC
46
45
External pin for LPF.
See the Recommended Operating
Circuit for the external circuits. Note
that external resistors and capacitors
should be metal film resistors and
temperature compensation capacitors
which are relatively unaffected by
temperature change.
VCOGND
IRGND
46
RC1
O
100
2.1V
– 10 –
IOGND
External pin for LPF.
See the Recommended Operating
Circuit for the external circuits.
– 11 –
30
21
34
27
FINE
DELAY
Bit 2
24
N/A∗1
TESTPOWREG
register read no
TTLPOLREG
UNLOCK
Enable
DSYNC
Enable
NCLK/2
Enable
CLK/2
Enable
DIVOUT
Enable
38
NCLK
Enable
Read out
power
39
CLK
Enable
35
33
FINE
DELAY
Bit 3
23
N/A∗1
register read no
32
FINE
DELAY
Bit 4
22
N/A∗1
PD
POL
31
COARSE COARSE
DELAY
DELAY
Bit 0
Bit 1
20
DIV 1, 2, 4 DIV 1, 2, 4
Bit 0
Bit 1
CPREG
register read no
DELAYREG
register read no
CENFREREG
Synth
power
40
DSYNC
POL
36
C.Pump
Bit 1
28
FINE
DELAY
Bit 1
25
N/A∗1
18
16
register read no
17
VCO
DIV
Bit 9
VCO
DIV
Bit 10
VCO
DIV
Bit 11
VCO
DIV
Bit 1
7
DATA1
DIVREG2
VCO
DIV
Bit 2
6
DATA2
11
VCO
DIV
Bit 3
5
DATA3
10
15
VCO
DIV
Bit 4
VCO
DIV
Bit 5
14
4
DATA4
3
DATA5
9
register read no
13
VCO
DIV
Bit 6
VCO
DIV
Bit 7
DIVREG1
2
1
register read no
DAT6
DATA7
MSB
Register Name
DATA
∗1 Register read no. 15 to 19 are N/A.
∗2 VCO By-pass at register read no. 41 is a MUX control bit in Block Diagram.
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register No.
Control Register Table
VCO
By-pass∗2
41
SYNC
POL
37
C.Pump
Bit 0
29
FINE
DELAY
Bit 0
26
N/A∗1
19
VCO
DIV
Bit 8
12
VCO
DIV
Bit 0
8
DATA0
1
1
1
1
0
0
0
ADDR2
MSB
1
1
0
0
1
1
0
ADDR1
ADDRESS
1
0
1
0
1
0
1
ADDR0
LSB
CXA3106AQ
CXA3106AQ
Electrical Characteristics
Item
(Ta = 25°C, VCC = 5V, GND = 0V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Current consumption (excluding output current)
Current consumption 1
ICC1
CS = H, Synth Power = 1
40
70
105
mA
Current consumption 2
ICC2
CS = H, Synth Power = 0
5
19
38
mA
Current consumption 3
ICC3
CS = L
3
14
24
mA
Digital input
Digital high level input
voltage (PECL)
VIH1
Digital low level input
voltage (PECL)
VIL1
VCOL, SYNCL input open
voltage (PECL)
VIO
Digital high level input
current (PECL)
IIH1
VIH = IOVCC – 0.8V
–100
100
µA
Digital low level input
current (PECL)
IIL1
VIL = IOVCC – 1.6V
–200
0
µA
Digital high level input
voltage (TTL)
VIH2
Digital low level input
voltage (TTL)
VIL2
Digital high level input
current (TTL)
IIH2
VIH = 2.7V
Digital low level input
current (TTL)
IIL2
VIL = 0.5V
IOVCC
–1.15
V
IOVCC
–1.5
IOVCC
–1.3
V
V
2.0
V
0.8
V
–200
–20
µA
–500
–100
µA
1.0
nA
HOLD characteristics
RC1 input pin leak current
Ileak
HOLD signal set-up time
Ths
20
ns
HOLD signal hold time
Thh
20
ns
PECLVCC
–1.1
V
Digital output
Digital high level output
voltage (PECL)
VOH1
RL = 330Ω
Digital low level output
voltage (PECL)
VOL1
RL = 330Ω
PECL output reference
voltage
VBB
RL = 330Ω
Digital high level output
voltage (TTL)
VOH2
CL = 10pF
Digital low level output
voltage (TTL)
VOL2
CL = 10pF
– 12 –
PECLVCC
–1.6
PECLVCC
–1.3
V
V
V
2.7
0.5
V
CXA3106AQ
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
UNLOCK output
UNLOCK output current
Iunlock
mA
–30
SYNC input
SYNC input frequency range Fin
100
10
kHz
DSYNC output
DSYNC output variable
coarse delay time setting
resolution
Rdsync1
DSYNC output variable
coarse delay time
Td1
DSYNC output variable
fine delay time setting
resolution
Rdsync2
DSYNC output variable
fine delay time
Td2
bit
2
4
1
CLK
bit
5
1/16
20/16
CLK
VCO characteristics
DIV output frequency
operation range 1
FVCO1
DIV = 1/1
40
160
MHz
DIV output frequency
operation range 2
FVCO2
DIV = 1/2
20
80
MHz
DIV output frequency
operation range 3
FVCO3
DIV = 1/4
10
40
MHz
VCO lock range
Vlock
1.7
4.4
V
VCO gain 1
KVCO1
DIV = 1/1
240
400
640
Mrad/sv
VCO gain 2
KVCO2
DIV = 1/2
120
200
320
Mrad/sv
VCO gain 3
KVCO3
DIV = 1/4
60
100
160
Mrad/sv
Charge pump current 1
Kpd1
C.Pump Bit = 00,
IREF = 1.6kΩ
80
100
130
µA
Charge pump current 2
Kpd2
C.Pump Bit = 10,
IREF = 1.6kΩ
350
400
500
µA
Charge pump current 3
Kpd3
C.Pump Bit = 11,
IREF = 1.6kΩ
1350
1600
1800
µA
VCO counter bits
Rdiv2
12
– 13 –
bit
CXA3106AQ
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
CLK (CLK, CLK/2) output
CLK output (PECL)
frequency range 1
Fclk1PECL DIV = 1/1
40
160
MHz
CLK output (PECL)
frequency range 2
Fclk2PECL DIV = 1/2
20
80
MHz
CLK output (PECL)
frequency range 3
Fclk3PECL DIV = 1/4
10
40
MHz
CLK, CLK/2 output (PECL)
TrPECL
rise time
10% to 90%,
RL = 330Ω
1.0
1.5
2.0
ns
CLK, CLK/2 output (PECL)
TfPECL
fall time
10% to 90%,
RL = 330Ω
1.0
1.5
2.0
ns
CLK output (TTL)
frequency range 1
Fclk1TTL
DIV = 1/1
40
80
MHz
CLK output (TTL)
frequency range 2
Fclk2TTL
DIV = 1/2
20
80
MHz
CLK output (TTL)
frequency range 3
Fclk3TTL
DIV = 1/4
10
40
MHz
CLK, CLK/2 output (TTL)
rise time
TrTTL
10% to 90%,
CL = 10pF
2.0
3.0
4.0
ns
CLK, CLK/2 output (TTL)
fall time
TfTTL
10% to 90%,
CL = 10pF
2.0
3.0
4.0
ns
CLK output (PECL, TTL)
duty
Dclk2
CL = 10pF
40
50
60
%
SYNC input (PECL) and
CLK output (PECL) delay
offset
Td3
CL = 10pF
CLK output (PECL) and
DSYNC output (PECL)
phase difference
Td4
CL = 10pF
1.5
2.4
3.0
ns
CLK output (PECL) and
CLK/2 output (PECL)
phase difference
Td5
CL = 10pF
0.0
0.8
1.0
ns
CLK output (PECL) and
DIVOUT output (TTL) rise
phase difference
Td6
CL = 10pF
10
14
19
ns
CLK output (PECL) and
DIVOUT output (TTL) fall
phase difference
Td7
CL = 10pF
8
11
14
ns
DSYNC, CLK, CLK/2 PECL
output and TTL output
Td8
phase difference
CL = 10pF
1.5
3.0
4.5
ns
– 14 –
1
ns
CXA3106AQ
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Tj1p-p
triggered at SYNC
Fsync = 15.73kHz
(Crystal)
Fclk = 12.27MHz
N = 780
3.0
5.0
8.0
ns
Tj2p-p
triggered at SYNC
Fsync = 31.47kHz
(Crystal)
Fclk = 25.18MHz
N = 800
1.0
2.0
3.0
ns
Tj3p-p
triggered at SYNC
Fsync = 48.08kHz
(Crystal)
Fclk = 50.00MHz
N = 1040
0.9
1.6
2.5
ns
Tj4p-p
triggered at SYNC
Fsync = 56.48kHz
(Crystal)
Fclk = 75.00MHz
N = 1328
0.8
1.5
2.0
ns
Tj5p-p
triggered at SYNC
Fsync = 80kHz
(Crystal)
Fclk = 136.00MHz
N = 1700
0.6
1.0
1.4
ns
triggered at DSYNC
0.1
ns
12
MHz
CLK (CLK, CLK/2) output
CLK vs. SYNC output jitter
(NTSC)
CLK vs. SYNC output jitter
(VGA)
CLK vs. SYNC output jitter
(SVGA)
CLK vs. SYNC output jitter
(XGA)
CLK vs. SYNC output jitter
(SXGA)
CLK vs. DSYNC output jitter Tj6p-p
Control registers
SCLK frequency
SCLK
in write/read mode
SENABLE setup time
TENS
in write mode
3
ns
SENABLE hold time
TENH
in write mode
0
ns
SDATA setup time
TDS
in write mode
3
ns
SDATA hold time
TDH
in read mode
0
ns
SENABLE setup time
TNENS
in read mode
3
ns
SENABLE hold time
TNENH
in read mode
0
ns
– 15 –
CXA3106AQ
Description of Block Diagram
Sync Input
Sync signals in the range of 10 to 100kHz can be input. Input supports both positive and negative polarity.
PECL input can also be a single input.
When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal.
When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal.
VCO oscillation stops when there is no sync input.
Register: SYNC POL
1
0
SYNC input polarity
Positive
Negative
Phase Detector
The phase detector operates at the sync input frequency of 10 to 100kHz. The PD input polarity should be
set to the default PD POL = 1. Phase comparison is performed at the edges.
The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped
at the front end of the CXA3106AQ when inputting a noisy signal.
The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.)
The PLL UNLOCK signal is output by an open collector.
(See the UNLOCK Timing Chart.)
Charge Pump
The gain (I, I/4, I/16) can be varied by changing the charge pump current using 2 bits of control register.
Register: C.Pump bit 1
0
1
1
Register: C.Pump bit 0
0
0
1
Charge pump current
100µA
400µA
1600µA
LPF
This is a loop filter comprised of the external capacitors and resistor.
Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor.
In particular, the 0.33µF capacitor should be equivalent to high dielectric constant series capacitor type B or
better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C)
VCO
The VCO oscillator frequency covers from 40 to 160MHz.
VCO Rear-end Counter
The VCO output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register.
The operating range can be expanded to 10 to 160MHz by combining the counter with a VCO frequency divider.
Register: DIV 1, 2, 4 bit 1
0
1
1
Register: DIV 1, 2, 4 bit 0
0
0
1
Counter frequency divisions
1/1
1/2
1/4
– 16 –
CXA3106AQ
Feedback Programmable Counter
This counter can be set as desired from 256 to 4096 using 12 bits.
Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11)
When the register value is changed, the new setting is actually loaded to the counter when the counter value
becomes "all 0".
Clock Output
When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the
sync signal.
The clock output delay time can be changed in the range of 1/16 to 20/16 CLK using 5 bits of control register.
(See the I/O Timing Chart.)
Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL
output can also be turned off independently.
Register: Clock Enable
1
0
Clock output status
ON
OFF
1/2 Clock Output
Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O
Timing Chart.)
Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.
Register: Clock Enable
1
0
Clock output status
ON
OFF
Delay Sync Output
The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK
regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the
reset signal for the system timing circuit.
The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is
undefined for one clock as shown in the Timing Chart.
The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range
of 1/16 to 20/16 CLK using 5 bits of control register, and then in the range of 1 to 4 CLK using 2 bits of
control register. In other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) CLK. (See the I/O Timing
Chart.)
DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock
TTL output can also be turned off.
Register: Clock Enable
1
0
Clock output status
ON
OFF
Lower delay line
FINE DELAY bits 0 to 4
00000
00001
· · · · · · · · · · · ·
10011
Delay time
1/16CLK
2/16CLK
· · · · · · · · · · · ·
20/16CLK
Upper delay line
COARSE DELAY bits 0 to 1
00
01
10
11
Delay time
1CLK
2CLK
3CLK
4CLK
Register: DSYNC POL
1
0
DSYNC output polarity
Positive
Negative
– 17 –
CXA3106AQ
Control Circuit (3-bit address, 8-bit data)
The timing and input methods are described hereafter.
Feedback programmable counter control
VCO rear-end counter control
Fine delay line control
Coarse delay line control
Charge pump current DAC control
Phase detector input positive/negative polarity control
Sync input positive/negative polarity control
Delay sync output positive/negative polarity control
Clock TTL output OFF function
Inverted clock TTL output OFF function
1/2 clock TTL output OFF function
Inverted 1/2 clock TTL output OFF function
Delay sync TTL output OFF function
UNLOCK output OFF function
Programmable counter input switching
Power save with register contents held
Register read function power ON/OFF
Programmable counter TTL output OFF function
REGISTER1, 2
REGISTER3
REGISTER4
REGISTER4
REGISTER5
REGISTER5
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER7
REGISTER7
REGISTER7
REGISTER7
12bit
2bit
5bit
2bit
2bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
VCO DIV Bit0 to 11
DIV1, 2, 4 Bit0, Bit1
FINE DELAY Bit0 to 4
COARSE DELAY Bit0, Bit1
C.Pump Bit0, Bit1
PD POL
SYNC POL
DSYNC POL
CLK Enable
NCLK Enable
CLK/2 Enable
NCLK/2 Enable
DSYNC Enable
UNLOCK Enable
VCO By-pass
Synth power
Read out power
DIVOUT Enable
Power Save
The CXA3106Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a
control register and the chip selector.
Step 1: Chip selector control
CS
H
L
Power save status
Power ON
All OFF
Step 2: Control register control
Register: Synth power
1
0
Power save status
Power ON
Control registers only ON
Readout Circuit (during test mode)
The control register contents can be read by serial data from SEROUT.
(See the Control Register Timing Chart.)
Register: Read out power
Readout status
0
1
Function OFF Function ON
– 18 –
CXA3106AQ
Programmable Counter Output (during test mode)
The programmable counter output is TTL output from the DIVOUT pin.
(See the I/O Timing Chart.)
This output is normally not used.
Register: DIVOUT Enable
0
1
DIVOUT output status
OFF
ON
TLOAD input (during test mode)
This control signal forcibly loads the control register contents to the programmable counter.
This signal is normally not used.
TLOAD
H
L
Forced load control status Function OFF Function ON
VCO input (during test mode)
This is the programmable counter test signal input pin.
This pin can be switched internally by the MUX circuit.
TTL and PECL input are possible.
This pin is normally not used.
Register: VCO By-pass
Input status
1
0
Internal VCO External input
– 19 –
CXA3106AQ
Control Register Timing
1) Write mode
Many CXA3106AQ functions can be controlled via a program. Characteristics are changed by setting the
internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin
11) and SDATA (Pin 12). The write timing diagram is shown below.
Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but
the data is input aligned with the LSB side in these cases. (See the Register Table.)
SENABLE is the enable signal and is active low. SCLK is the transfer clock signal, and data is loaded to the
IC at the rising edge. When SENABLE rises, SCLK must be high. (Registers are set at the rising edge of
SENABLE.) When SENABLE falls, SCLK may be either high or low.
SENABLE
8bit
DATA
SDATA
3bit
ADDRESS
SCLK
Enlarged
Enlarged
TENS
TENH
SENABLE
SDATA
SCLK
TDS TDH
For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. This is
to say that the latter 11 bits are loaded to the register.
SENABLE
SDATA
5bit
Invalid DATA
8bit
DATA
SCLK
– 20 –
3bit
address
CXA3106AQ
The settings of the frequency divider (2 bits, DIV1, 2, 4) and programmable counter (12 bits, VCODIV) at the
rear end of the VCO are transferred in the order shown below. (The data will be set when the three registers
are transferred.)
First DIVREG2, CENFREREG and DIVREG1 are set, and then the data is transferred independently at the
timings shown below.
DIVREG2 (upper 4 bits of VCODIV)
↓
CENFREREG (2 bits of DIV1, 2, 4)
↓
DIVREG1 (lower 8 bits of VCODIV)
All three of the above registers must be changed even when changing only DIV1, 2, 4 (2 bits). This is the
same when changing only VCODIV (12 bits).
SENABLE
SDATA
SCLK
DIVREG2
CENFREREG
– 21 –
DIVREG1
CXA3106AQ
2) Read mode
Data can be transferred from the shift register to the data register only when SENABLE is high.
Binary data can be read from the data register by inputting SCLK when SENABLE is high. Data is loaded
from the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output
sequentially from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 41st SCLK
clock pulse is input, the register read no. 41 data (VCO By-pass) is output. Then, when the 42nd clock pulse
is input to SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output is
repeated. Also, the data output from the SCAN PATH circuit is automatically reloaded even when the shift
register data is changed during data output.
Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH
circuit. (See the Control Register Table for the actual register read no.)
SCLK
CLK
I/P SHIFT REGISTER, 11 BITS
NEN
SENABLE
8 BIT DATA
3 BIT ADDRESS
7 DATA REGISTERS (41 LATCHES).
REGISTERS ARE DIFFERENT LENGTHS
UP TO 8 BIT
TR
EN
CLK
SEROUT
SCAN PATH, 1 ELEMENT PER REGISTER BIT
Block Diagram during Read Mode
TNENS
TNENH
SENA
READ NO. 1
SEROUT
SCLK
1
READ NO. 2
2
Timing Chart during Read Mode
– 22 –
READ NO. N
N
Td3
(typ. 1ns)
0
1CLK
– 23 –
CLK/2 output
(PECL)
RESET
(internal signal)
DSYNC output
(positive polarity)
(PECL)
DIVOUT output
(TTL)
1
Td1
(1 to 4) CLK
Td6
(typ. 14ns)
1/16CLK to 20/16CLK
Td2
CLK output
(PECL)
SYNC input
(positive polarity)
(PECL)
Timing Charts
1. I/O timing
2
1CLK
Td4
(typ. 2.4ns)
3
Td5
(typ. 0.8ns)
8CLK
4CLK
Td7
(typ. 11ns)
CXA3106AQ
CXA3106AQ
2. HOLD timing
SYNC input
(SYNC POL = 1)
SYNC input
(SYNC POL = 0)
DIVOUT output
(TTL)
Thh
Ths
HOLD input
(TTL)
Thh
Ths
Thold
AA
A
AA
A
AA
The phase comparison output is held and fixed VCO output frequency is output.
CLK output
HOLD signal set-up time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DICOUT.
Or, when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC; when
SYNC POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC.
HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or,
when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal; when
SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal.
When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows.
I
SW
+Q
∆V
–Q
C
Ileak
VCO
∆f
SW
I
C · ∆V = Q = Ileak · Thold
C:
∆V:
Ileak:
Thold:
Loop filter capacitance
Voltage variation due to leak current
Internal amplifier leak current
Hold time
∆V = Ileak · Thold/C
∆f = ∆V · KVCO = Ileak · Thold/C · KVCO
For example, assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, and KVCO = 2π · 65MHz, then:
∆V = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) = 3 × 10–6 [V]
∆f = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) · 65 × 106 = 197 [Hz]
– 24 –
CXA3106AQ
3. Relationship between SYNC input and DSYNC output during HOLD
SYNC
internal signal
J
DIVOUTN
internal signal
K
DSYNC
internal signal
Q
CK
Q
CLK
When the above SYNC internal and DIVOUTN internal signals are input, the DSYNC internal signal is output
as shown the table below.
First, when SYNC = L and DIVOUTN = L, it does not stand up because the output of Q = DSYNC = L and Q =
DSYNC = H∗∗ (unchanged with the previous data) is exclusive logic. And, Q = DSYNC = H∗∗ is the impossible
output. Therefore, it is as follows.
1. DSYNC = L when SYNC = L and DIVOUTN = L.
2. DSYNC = H∗ or L∗ (unchanged with the previous data) when SYNC = H and DIVOUTN = L.
3. DSYNC = H when DIVOUTN = H (SYNC = H or L)
SYNC
DIVOUTN
L
L
L
H
H
L
H
H
J
K
Q
Q
L
L
L ∗∗
H ∗∗
H
L
H
L
L
L
H
L
H
H
L
L
L∗
H∗
L
L
H∗
L∗
H∗
L∗
L
H
L
H
H
(∗) and (∗∗) are unchanged with the previous data.
– 25 –
DSYNC
H ∗∗
CXA3106AQ
The polarity of SYNC internal signal and DSYNC internal signal has a relationship between the setting of the
respective SYNC POL and DSYNC POL. The below diagrams are the examples that show the relationship
between SYNC input and DSYNC output and between the SYNC POL and DSYNC POL during HOLD.
CASE1
1/fSYNC
1/fSYNC
1/fSYNC
Thh
1/fSYNC
Ths
1/fSYNC
Thh
1/fSYNC
1/fSYNC
8CLK
8CLK
Ths
HOLD input
SYNC Input
SYNC internal signal
(SYNC POL = 1)
8CLK
DIVOUTN
internal signal
8CLK
8CLK
8CLK
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 1)
CASE2
1/fSYNC
1/fSYNC
1/fSYNC
Thh
1/fSYNC
Ths
1/fSYNC
Thh
1/fSYNC
1/fSYNC
Ths
HOLD input
SYNC Input
SYNC internal signal
(SYNC POL = 0)
DIVOUTN
internal signal
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 0)
– 26 –
8CLK
8CLK
8CLK
8CLK
CXA3106AQ
CASE3
1/fSYNC
1/fSYNC
1/fSYNC
1/fSYNC
1/fSYNC
Thh
1/fSYNC
1/fSYNC
8CLK
8CLK
Ths
HOLD input
Ths
Thh
SYNC Input
SYNC internal signal
(SYNC POL = 1)
8CLK
DIVOUTN
internal signal
8CLK
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 1)
CASE4
1/fSYNC
1/fSYNC
Thh
1/fSYNC
1/fSYNC
1/fSYNC
Ths
1/fSYNC
1/fSYNC
Thh
HOLD input
Ths
SYNC Input
SYNC internal signal
(SYNC POL = 0)
DIVOUTN
internal signal
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 0)
– 27 –
8CLK
8CLK
8CLK
8CLK
CXA3106AQ
CASE5
1/fSYNC
1/fSYNC
1/fSYNC
Thh
1/fSYNC
1/fSYNC
1/fSYNC
Ths
Thh
1/fSYNC
Ths
HOLD input
SYNC Input
SYNC internal signal
(SYNC POL = 1)
8CLK
DIVOUTN
internal signal
8CLK
8CLK
8CLK
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 1)
CASE6
1/fSYNC
1/fSYNC
Thh
1/fSYNC
1/fSYNC
Ths
1/fSYNC
Thh
1/fSYNC
1/fSYNC
Ths
HOLD input
SYNC Input
SYNC internal signal
(SYNC POL = 0)
DIVOUTN
internal signal
8CLK
8CLK
DSYNC
internal signal
DSYNC output
(DSYNC POL = 0)
– 28 –
8CLK
8CLK
8CLK
8CLK
CXA3106AQ
4. UNLOCK timing
Inside the IC
Outside the IC
VCC
I2
R2
R1
Signal from phase
comparator
unlock
detect
S1
I1
UNLOCK
S2
C
The unlock detect output is an open collector. When unlock detect output S1 goes high, the current I1 is pulled in.
The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this output
pin as appropriate and changing these values. Operation during three modes is described below.
CASE 1: When there is no phase difference, that is to say, when the PLL is locked.
The S1 signal is low and the S2 signal is high.
The UNLOCK output remains low.
S1
S2
threshold
level
UNLOCK
CASE 2: When there is a phase difference, that is to say, when the S1 signal goes high and low as shown in
the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that
open collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to
become slower. Also, since the S2 signal rise slew rate is determined by the current I2, reducing
the resistance R2 causes the S2 signal rise slew rate to become faster. If this integrated S2 signal
does not fall below the threshold level of the next inverter, the UNLOCK signal stays low, and the
PLL is said to be locked.
S1
S2
threshold
level
UNLOCK
CASE 3: However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the
current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster.
Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this
integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes
from low to high, and the PLL is said to be unlocked.
S1
threshold
level
S2
UNLOCK
– 29 –
CXA3106AQ
Charge Pump and Loop Filter Settings
The CXA3106Q's charge pump is a constant-current output type as shown below.
When a constant-current output charge pump circuit is used inside the
PLL, the phase detector output acts as a current source, and the
dimension of its transmittance KPD is A/rad. Also, when considering the
VCO input as a voltage, the LPF transmittance dimension must be
expressed in ohms (Ω = V/A).
Therefore, the PLL transmittance when a constant-current output charge
pump circuit is used is as follows.
VCC
S1
To LPF
S2
ωr
1/S
θr
+
PD
LPF
VCO
KPD
(A/rad)
F (S)
(Ω)
KVCO
(rad/sV)
–
θo
N
1/S
counter
ω0/N
1/N
The PLL closed loop transmittance is obtained by the following formula.
θo/N
θr
=
KPD · F (S) · KVCO · 1/N · 1/S
... (1)
1 + KPD · F (S) · KVCO · 1/N · 1/S
Here, KPD, F (S), and KVCO are:
KPD: Phase comparator gain
F (S): Loop filter transmittance
KVCO: VCO gain
(A/rad)
(Ω)
(rad/sV)
∗1 The reason for the 1/S inside the phase detector is as follows.
t
θo (t)/N = ∫ o ω0 (t)/Ndt + θo (t = 0)/N ... (a)
θo (t = 0) = 0
t
θo (t)/N = ∫ o ω0 (t)/Ndt ... (b)
Performing Laplace conversion:
θo (S)/N = 1 W0 (S)/N ... (c)
S
– 30 –
ω0
CXA3106AQ
The loop filter F (S) is described below.
The loop filter smoothes the output pulse from the phase comparator and inputs it as the DC component to the
VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL
response characteristics.
Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the
CXA3106AQ's LPF is a current input type active filter as shown below, so the following calculations show an
actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this
transmittance to create a formula for setting the filter constants.
Current input type active filter
C
R
ii
–A
–1
Vo
–Vo
The Bode diagram for formula (2) is as follows.
F (S) =
=
gain [dB]
VO
1
+ VO = (R +
)
A
SC
1 + SRC
A
·
SC
1+A
log scale
The filter transmittance is as follows.
1
τ
log w
1 + Sτ
A
·
SC
1+A
∴τ = RC
log w
phase [deg]
0
Here, assuming A > 1, then:
F (S) =
1 + Sτ ...........................
(2)
SC
–45deg
–90
Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL:
θo/N
θr
KPD · KVCO · τ
NC
=
KPD · KVCO · τ
NC
S2 +
=
ωn =
ζ=
S2
√
·S+
2ζωnS + ωn2
+ 2ζωnS + ωn2
KPD · KVCO
NC
... (3)
KPD · KVCO
·S+
NC
............................................ (4)
KPD · KVCO ......................................................
(5)
NC
1
2
ωnτ ................................................................. (6)
– 31 –
CXA3106AQ
Here, ωn and ζ are as follows.
ωn characteristic angular frequency:
The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter
and individual loop gains is called the characteristic angular frequency: ωn.
ζ damping factor:
This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is
determined by the loop gain and the loop filter.
A capacitor C2 is added to the actual loop filter.
This added capacitor C2 is used to reduce the R noise, and a value of about 1/10 to 1/1000 of C1 should be
selected as necessary.
Current input type active filter with added capacitor C2
C2
C1
R
ii
–1
–A
Vo
–Vo
=
1 + C1 · R · S
S ((C1 + C2) + C1 · C2 · R · S)
gain [dB]
F (S) =
The Bode diagram for formula (7) is as follows.
1 + τ1 · S
.................. (7)
S (C1 + C2) (1 + τ2 · S)
log scale
The filter transmittance is as follows.
1
τ1
τ1 = C1 · R
τ2 =
log w
C1 · C2 · R
C1 + C2
log w
phase [deg]
0
Here, assuming C2 = C1/100, then:
τ2 =
C1 · C1/100 · R
C1 + C1/100
=
1
C1 · R
101
=
1
τ1
101
–45deg
–90
– 32 –
1
τ2
CXA3106AQ
Next, the various parameters inside an actual CXA3106AQ are obtained.
The CXA3106AQ's charge pump output block and the LPF circuit are as follows.
C2
R1 C1
46
45
CXA3106Q
VCC
100k
100µA
or 400µA
or 1600µA
To VCO
S1
100µA
or 400µA
or 1600µA
S2
20k
100
First, KPD is as follows.
KPD = 100µ/2π or 400µ/2π or 1600µ/2 π (A/rad)
VCO frequency [MHz]
Typical KVCO characteristics curves for the CXA3106Q's internal VCO are as follows.
VCO DIV = 1/1
150
VCO DIV = 1/2
100
VCO DIV = 1/4
50
2
3
VCO input voltage [V]
Therefore, KVCO is as follows.
KVCO = 2π · 65M or 2π · 32.5M or 2π · 16.25M (rad/sV)
– 33 –
4
CXA3106AQ
ωn and ζ calculated for various types of computer signals are shown below.
Here, the various parameters are as follows.
FSYNC: Input H sync frequency
FCLK: Output clock frequency
KPD∗2π: Phase comparator gain ∗2π
(KPD*2π = +100 or 400 or 1600)
KVCO/2π: VCO gain
(when VCO DIV = 1/1, KVCO/2π = 65)
(when VCO DIV = 1/2, KVCO/2π = 65/2)
(when VCO DIV = 1/4, KVCO/2π = 65/4)
N: Counter value
C1: Loop filter capacitance value
R1: Loop filter resistance value
Resolution FSYNC FCLK
kHz
MHz
KPD C.Pump
N
DIV1.2.4
C1
KVCO/2π
× 2π setting
setting setting
µA Bit1 Bit0
MHz/V
µF
Bit1 Bit0
R1
Ω
ωn
fn
ζ
kHzrad kHz
NTSC
15.734 12.27 100
0
0
65/4
1
1
780
0.33 3300 2.51
0.40 1.37
NTSC
15.734 18.41 400
1
0
65/4
1
1
1170 0.33 3300 4.10
0.65 2.23
NTSC
15.734 24.55 400
1
0
65/4
1
1
1560 0.33 3300 3.55
0.57 1.93
PAL
15.625 14.69 100
0
0
65/4
1
1
940
0.33 3300 2.29
0.36 1.25
PAL
15.625 22.03 400
1
0
65/4
1
1
1410 0.33 3300 3.74
0.59 2.04
PAL
15.625 29.38 400
1
0
65/4
1
1
1880 0.33 3300 3.24
0.52 1.76
PC-98 640 × 400 24.82 21.05 400
1
0
65/4
1
1
848
0.33 3300 4.82
0.77 2.62
640 × 480 31.47 25.18 400
1
0
65/4
1
1
800
0.33 3300 4.96
0.79 2.70
MAC 640 × 480 35.00 30.24 400
1
0
65/4
1
1
864
0.33 3300 4.77
0.76 2.60
VESA 640 × 480 37.86 31.50 400
1
0
65/4
1
1
832
0.33 3300 4.87
0.77 2.65
SVGA 800 × 600 35.16 36.00 400
1
0
65/2
1
0
1024 0.33 3300 6.20
0.99 3.38
SVGA 800 × 600 37.88 40.00 400
1
0
65/2
1
0
1056 0.33 3300 6.11
0.97 3.33
SVGA 800 × 600 46.88 49.50 400
1
0
65/2
1
0
1056 0.33 3300 6.11
0.97 3.33
SVGA 800 × 600 48.08 50.00 400
1
0
65/2
1
0
1040 0.33 3300 6.15
0.98 3.35
SVGA 800 × 600 53.67 56.25 400
1
0
65/2
1
0
1048 0.33 3300 6.13
0.98 3.34
MAC 832 × 624 49.72 57.28 400
1
0
65/2
1
0
1152 0.33 3300 5.85
0.93 3.18
XGA 1024 × 768 48.36 65.00 400
1
0
65/2
1
0
1344 0.33 3300 5.41
0.86 2.95
XGA 1024 × 768 56.48 75.00 400
1
0
65/2
1
0
1328 0.33 3300 5.45
0.87 2.97
XGA 1024 × 768 60.02 78.75 400
1
0
65/2
1
0
1312 0.33 3300 5.48
0.87 2.98
MAC 1024 × 768 60.24 80.00 400
1
0
65/2
1
0
1328 0.33 3300 5.45
0.87 2.97
XGA 1024 × 768 68.68 94.50 400
1
0
65/1
0
0
1376 0.33 3300 7.57
1.20 4.12
SXGA 1280 × 1024 46.43 78.75 400
1
0
65/1
0
0
1696 0.33 3300 6.82
1.08 3.71
SXGA 1280 × 1024 63.98 108.00 400
1
0
65/1
0
0
1688 0.33 3300 6.83
1.09 3.72
SXGA 1280 × 1024 79.98 135.00 400
1
0
65/1
0
0
1688 0.33 3300 6.83
1.09 3.72
SXGA 1280 × 1024 91.15 156.96 400
1
0
65/1
0
0
1722 0.33 3300 6.76
1.08 3.68
VGA
– 34 –
CXA3106AQ
CLK Jitter Evaluation Method
The regenerated CLK is obtained by applying Hsync to the CXA3106AQ. Apply this CLK to a digital
oscilloscope and observe the CLK waveform using Hsync as the trigger.
trigger
Hsync
Pulse
Generator
CXA3106AQ
CLK
ch1
H
Back
Sync Porch
Digital
Oscilloscope
Active
Video
Front
Porch
Computer signal
15 to 25% of Tsync
Hsync
Tsync = 1/fsync
CLK
Enlarged
Enlarged
Enlarged
Enlarged
Trigger
CLK
Tjp-p
The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in
the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync.
Therefore, when the observation point is changed, the CLK jitter at that point is observed.
Jitter amount [Tjp-p]
The figure below shows an typical example of the CLK jitter for the CXA3106AQ.
The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles
down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has
passed from the rising edge of Hsync.
0
1/4 · Tsync
2/4 · Tsync
Observation points
– 35 –
3/4 · Tsync
Tsync
CXA3106AQ
Example of Representative Characteristics
KVCO characteristics
KVCO Temperature characteristics
250
300
Output Frequency [MHz]
Output Frequency [MHz]
Ta = +75°C
Ta = +25°C
Ta = –25°C
250
200
DIV = 1/1
150
DIV = 1/2
100
DIV = 1/4
50
200
150
100
50
0
0
1.5
2.0
2.5
3.0
3.5
VCO Control Voltage [V]
4.0
4.5
1.5
Coarse Delay Td1 vs Coarse Delay Bit
2.5
3.0
3.5
4.0
VCO Control Voltage [V]
4.5
Fine Delay Td2 vs Fine Delay Bit
5
25
Fine Delay Td2 [1/16 CLK]
Ta = –25°C
Ta = +25°C
Ta = +75°C
4
3
2
Ta = –25°C
Ta = +25°C
Ta = +75°C
20
15
10
5
1
0
0
1
2
Coarse Delay Bit
3
0
5
10
Fine Delay Bit
Jitter peak-peak vs Output Frequency
5.0
NTSC/PAL, DIV = 1/4, CP = 10
VGA, DIV = 1/4, CP = 10
SVGA, DIV = 1/2, CP = 10
XGA, DIV = 1/2, CP = 10
SXGA, DIV = 1/1, CP = 11
4.0
Jitter peak-peak [ns]
Coarse Delay Td1 [CLK]
2.0
3.0
2.0
1.0
0.0
0
20
40
60
80
100
Output Frequency [MHz]
– 36 –
120
140
160
15
20
CXA3106AQ
Notes on Operation
• Be sure not to separate the analog and digital power supplies, and the analog and digital GND.
• The ground pattern should be as wide as possible. Using a multi-layer substrate with a mat ground is
recommended.
• Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as
possible.
• Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during
high-speed operation.
• Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3106AQ
PWB.)
– 37 –
CXA3106AQ
(1) Recommended PECL I/O circuit
The peripheral circuits mainly use PECL for digital input and output. Of course, PECL and TTL can also be
mixed. In this case, disable the TTL outputs with the control registers.
PECL level output pins
330Ω
33
32
31
30
29
28
27
DSYNCL
CLKH
CLKL
CLK/2H
CLK/2L
PECLVCC
IOGND
26
TTLVCC
34
25
TTLGND
35
DSYNCH
37 IOGND
PECLVCC
36
VBB
GND
DSYNC 24
38 IOVCC
CLK 23
39 PLLVCC
CLKN 22
40 PLLGND
CLK/2 21
41 VCOVCC
CLK/2N 20
42 VCOGND
100pF
0.33µF
DGND 19
43 VCOHGND
∗3
DVCC
VCC
18
1.6kΩ
100Ω
44 IREF
UNLOCK 17
45 RC2
DIVOUT 16
46 RC1
SEROUT 15
100kΩ
10nF
1200pF
GND
3.3kΩ
Loop Filter ∗4
47 IRGND
IOVCC
IOGND
VCOH
VCOL
VCO
HOLD
SYNCH
SYNCL
SYNC
SENABLE
SCLK
SDATA
48
CS 14
1
2
3
4
5
6
7
8
9
10
11
12
IRVCC
TLOAD
GND
Notes)
∗1 Unless otherwise specified, all capacitors are 0.1µF.
∗2 Vary the external resistor and capacitor values of the
UNLOCK output as necessary.
∗3 This external resistor (1.6kΩ) should be a metal film
resistor in consideration of temperature characteristics.
∗4 The loop filter's capacitors and resistor should also be
temperature compensated.
13
VCC (+5.0V)
Control
Register
HOLD
SYNCH, SYNCL: PECL level
complementary input
– 38 –
UNLOCK output∗2
CXA3106AQ
34
33
32
31
30
29
28
27
26
DSYNCL
CLKH
CLKL
CLK/2H
CLK/2L
PECLVCC
IOGND
TTLVCC
25
TTLGND
35
DSYNCH
37 IOGND
PECLVCC
36
VBB
(2) Recommended TTL I/O circuit
The peripheral circuits mainly use TTL for digital input and output. Of course, PECL and TTL can also be
mixed.
TTL level output pins
DSYNC 24
38 IOVCC
CLK 23
39 PLLVCC
CLKN 22
40 PLLGND
CLK/2 21
41 VCOVCC
CLK/2N 20
42 VCOGND
100pF
0.33µF
DGND 19
43 VCOHGND
∗3
VCC
DVCC 18
1.6kΩ
100Ω
44 IREF
UNLOCK 17
45 RC2
DIVOUT 16
46 RC1
SEROUT 15
100kΩ
10nF
1200pF
GND
3.3kΩ
Loop Filter ∗4
47 IRGND
IOVCC
IOGND
VCOH
VCOL
VCO
HOLD
SYNCH
SYNCL
SYNC
SENABLE
SCLK
SDATA
48
CS 14
1
2
3
4
5
6
7
8
9
10
11
12
IRVCC
TLOAD
GND
Notes)
∗1 Unless otherwise specified, all capacitors are 0.1µF.
∗2 Vary the external resistor and capacitor values of the
UNLOCK output as necessary.
∗3 This external resistor (1.6kΩ) should be a metal film
resistor in consideration of temperature characteristics.
∗4 The loop filter's capacitors and resistor should also be
temperature compensated.
13
VCC (+5.0V)
Control
Register
HOLD
SYNC: TTL level input
– 39 –
UNLOCK output∗2
CXA3106AQ
Connecting the CXA3106AQ with Sony ADC (Demultiplex Mode)
When connecting the PLL output to A/D converters with built-in demultiplex function such as the
CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured by connecting the CLK
(PECL) and CLKN (PECL) outputs of the CXA3106AQ to the CLK (PECL) and CLKN (PECL) inputs of each
A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3106AQ to
the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively. (when the PLL counter
value N is an even number)
Wiring Diagram
R
8 or 6
VIN
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
TTL
8 or 6
RESETN (PECL)
RESET (PECL)
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
CMOS LOGIC
8 or 6
VIN
TTL
8 or 6
RESETN (PECL)
RESET (PECL)
TTL
8 or 6
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
TTL
DSYNC (TTL)
1/2 CLKN (PECL)
CLKN (PECL)
1/2 CLK (PECL)
CLK (PECL)
1/2 CLK
(TTL)
8 or 6
RESETN (PECL)
RESET (PECL)
TTL
CLK (TTL)
VIN
B
RESET (TTL)
G
TTL
• CXA3026AQ 8bit 140MSPS ADC
• CXA3026Q 8bit 120MSPS ADC
• CXA3086Q 6bit 140MSPS ADC
PLL
CXA3106AQ
– 40 –
CXA3106AQ
CXA3106AQ and Sony ADC (Demultiplex Mode) Timing
The CXA3106AQ and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the A/D converters
Clock input vs. reset input
The setup time is T–1ns and the hold time is 0ns, satisfying the A/D converter specifications.
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. 1/2 clock output timing
The setup time is T–4.5ns and the hold time is T–0.5ns. (These timings also include combinations of
three A/D converters from different lots, and are defined for all operating temperatures and all operating
supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106AQ vs. A/D converter 1/2 clock output
The setup time is T–3ns and the hold time is T–5ns.
CXA3106AQ
T
CLK (PECL)
out
3 to 7.5ns
DSYNC (TTL)
out
0 to 1ns
1/2CLK (PECL)
out
∗ See the CXA3026AQ/Q and
CXA3086Q specifications.
CXA3026Q
CXA3026AQ
CXA3086Q
4.5 to 8ns
Thold min.
T–5ns
Tsetup min.
T–3ns
1/2CLK (TTL)
out
DATA (TTL)
out
– 41 –
Tsetup min. Thold min.
T–4.5ns
T–0.5ns
CXA3106AQ
Connecting the CXA3106AQ with Sony ADC (Straight Mode)
When connecting the PLL output to A/D converters such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony),
a simple system can be configured as shown below.
Wiring Diagram
R
8 or 6
VIN
CLK (PECL)
CLKN (PECL)
TTL
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
CLK (PECL)
CLKN (PECL)
CMOS LOGIC
8 or 6
VIN
TTL
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
8 or 6
VIN
CLK (PECL)
CLKN (PECL)
TTL
DSYNC (TTL)
CLK (TTL)
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
CLK (TTL)
B
RESET (TTL)
G
• CXA3026AQ 8bit 140MSPS ADC
• CXA3026Q 8bit 120MSPS ADC
• CXA3086Q 6bit 140MSPS ADC
PLL
CXA3106AQ
– 42 –
CXA3106AQ
CXA3106AQ and Sony ADC (Straight Mode) Timing
The CXA3106AQ and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. clock output from CXA3106AQ
The setup time is T–8.5ns and the hold time is 2ns. (These timings also include combinations of three A/D
converters from different lots, and are defined for all operating temperatures and all operating supply
voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106AQ vs. clock output from CXA3106AQ
The setup time is T–4.5ns and the hold time is 1.5ns.
CXA3106AQ
T
CLK (PECL)
out
1.5 to 4.5ns
CLK (TTL)
out
1.5 to 3ns
DSYNC (TTL)
out
Thold min.
1.5ns
Tsetup min.
T–4.5ns
CXA3026Q
CXA3026AQ
CXA3086Q
Tsetup min.
T–8.5ns
Thold min.
2ns
6.5ns min
DATA (TTL)
out
10ns max
– 43 –
CXA3106AQ
CXA3106AQ-PWB (CXA3106AQ Evaluation Board)
The CXA3106AQ-PWB is an evaluation board for the CXA3106AQ PLL-IC. This board makes it possible to
easily evaluate the CXA3106AQ's performance using the supplied control program (Note: IBM PC/AT, MSDOS 5.0 and newer US mode specifications).
Features
• Two input level (TTL and PECL) SYNC input
• Two output level (TTL and PECL) CLK, CLK2 and DSYNC output
• Supply voltage: +5.0V
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage
VCC
–0.5 to +7.0
Recommended Operating Conditions
• Supply voltage
VCC
4.75 to 5.25
GND
0
• Digital input
(PECL)
DIN (High)
DIN (Low)
(TTL)
DIN (High)
DIN (Low)
• Operating ambient temperature
Ta
–20 to +75
V
V
V
VCC – 1.1
VCC – 1.5
GND + 2.0
GND + 0.8
V (Min.)
V (Max.)
V (Min.)
V (Max.)
°C
Block Diagram
Loop Filter
VCO input
(PECL/TTL)
DSYNC output
(PECL/TTL)
CXA3106AQ
48pin QFP
SYNC input
(PECL/TTL)
CLK output
(PECL/TTL)
CLK/2 output
(PECL/TTL)
VBB (PECL)
SEROUT (TTL)
3
DIVOUT (TTL)
UNLOCK (TTL)
CONTROL BUS (TTL)
SENABLE, SCLK, SDATA
– 44 –
CXA3106AQ
Setting Methods and Notes on Operation
Input pins
This PWB supports TTL single and PECL complementary input.
Input pins: SYNC: TTL level input, 10 to 100kHz
SYNCL: PECL low level input, 10 to 100kHz
SYNCH: PECL high level input, 10 to 100kHz
VCO:
VCOL:
VCOH:
TTL level input. This is a test pin and is therefore normally not used.
PECL low level input. This is a test pin and is therefore normally not used.
PECL high level input. This is a test pin and is therefore normally not used.
Output pins
This PWB supports TTL single and PECL complementary output.
DSYNCH,
DSYNCL: PECL level complementary delay SYNC outputs. The output range is 10 to 160kHz.
DSYNC:
TTL level delay SYNC output. The output range is 10 to 100kHz.
CLKH,
CLKL:
PECL level complementary CLK outputs. The output range is 10 to 160MHz.
CLK,
CLKN:
TTL level complementary CLK outputs. The output range is 10 to 80MHz.
CLK/2H,
CLK/2L:
PECL level complementary 1/2 CLK outputs. The output range is 5 to 80MHz.
CLK/2,
CLK/2N:
TTL level complementary CLK outputs. The output range is 5 to 80MHz.
VBB:
Outputs the PECL amplitude threshold voltage.
SEROUT: TTL level control register serial data output.
DIVOUT: TTL level internal programmable counter test output.
UNLOCK: TTL level UNLOCK output. This pin requires external circuits such as appropriate capacitors and
resistors.
See the IC specifications for a detailed description.
PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL
outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective
control registers. Therefore, the enable/disable settings should be made in accordance with the application.
See the following pages for the setting method.
– 45 –
CXA3106AQ
Jumper Wire Settings
S1, S2: These enable/disable HOLD (Pin 6). HOLD is active high, so the jumper wire should be connected to
S2 (HOLD = low) for normal use. When using HOLD, connect the jumper wire to S1 (HOLD = high).
(For the initial setting, the jumper wire is connected to S2.)
S3, S4: These enable/disable TLOAD (Pin 13). Connect the jumper wire to S4 (TLOAD = high) for normal use.
When using TLOAD, connect the jumper wire to S3 (TLOAD = low). (For the initial setting, the jumper
wire is connected to S4.)
S5, S6: These enable/disable CS (Pin 14). Connect the jumper wire to S6 (CS = high) for normal use. When
using Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is
connected to S6.)
Supplied Program
This PWB is equipped with a control program that facilitates evaluation of the CXA3106AQ. Operation
methods and precautions are as follows.
1) Compatible personal computers
Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also,
operating systems which support the program are MS-DOS 5.0 or newer and MS-Windows 3.1 or newer.
(When using Windows, start the program from the DOS window.)
2) Connect the supplied cable
Connect the supplied cable to the parallel port of the personal computer and the DBUS1 connector of the
CXA3106AQ-PWB.
D-SUB 25-pin parallel connector pin arrangement
1
13
14
2pin : SCLK
3pin : SDATA
4pin : SENABLE
11pin : SERIN
19pin : GND
25
3) Connect the power cable and supply power to the CXA3106AQ-PWB
4) Start the program
A) Boot the personal computer and then shift to the directory containing the program.
B) Set MS-DOS to US mode. → US Return or Enter
C) Input the program name. → ∗1CXA3106A or CXA3106B Return or Enter → Move to the program screen.
∗1 Only one of either CXA3106A or CXA3106B can be used as the program name depending on the printer
port setting of the personal computer.
– 46 –
CXA3106AQ
5) Description of the program screen
A) When the program is started, the following initial screen is displayed.
Please type the name of the initialization file OR press ENTER.
The file extention.INI should not be included. The default file
when ENTER is pressed is CXA3106.INI
Filename > _
When this screen appears, press the Return or Enter key. The screen shifts to the function setting screen.
B) Function settings
When the program is loaded, the following function setting screen appears.
CXA3106 PLL REGISTERS
Divisor 1344
Divider 2
Coarse Delay 00
Fine Delay
10
Charge Pump 10
Polarity
Power
SYNC
DSYNC
PD
SCAN
SYNTH
VCO Bypass
1
1
1
OFF
ON
ON
O/P Enable
DIVOUT
OFF
UNLOCK
OFF
DSYNC
CLK2
NCLK2
CLK1
NCLK1
OFF
OFF
OFF
OFF
OFF
Use arrow keys to select data bit. Press ENTER to toggle and load data.
Use Pg Up and Pg Dn to increment/decrement divisor and fine delay registers.
Press a to abort, s to scan registers
– 47 –
MIXED SIGNAL SYSTEMS JAN 1997
CXA3106AQ
Divisor
This is used to input the frequency division ratio of the program counter. The value can be changed as
desired from 9 to 4111 by moving the cursor to the position of the number and pressing the Return or Enter
key. (Note: The operating range of the CXA3106AQ is from 256 to 4096.) The value can also be incremented
or decremented by one step by pressing the Page Up or Page Down key, respectively.
The internal VCO has an oscillator frequency of 40 to 160MHz, so the output frequency and Divider (VCO
frequency divider) setting range are as follows.
40
Divider = 1
160
Divider
1/1
20
1/2
1/4
10
Divider = 2
80
40
Divider = 4
50
100
150
O/P Frequency [MHz]
Divider
This sets the VCO output frequency division ratio to 1/1, 1/2 or 1/4. The frequency division ratio changes
repeatedly in the order of 1/1 → 1/2 → 1/4 → 1/1 each time the cursor is moved to the position of the number
and the Return or Enter key is pressed.
Coarse Delay
This is the DSYNC upper delay time setting. The value can be changed by moving the cursor to the position
of the number and pressing the Return or Enter key. The delay time variable range settings are "00" (1 CLK),
"01" (2 CLK), "10" (3 CLK) or "11" (4 CLK).
Fine Delay
This is the DSYNC lower delay time setting. The value can be changed by moving the cursor to the position
of the number and pressing the Return or Enter key. The value can also be incremented or decremented by
one step by pressing the Page Up or Page Down key, respectively. The delay time can be varied from 1/16
CLK to 32/16 CLK by setting "0" to "31", respectively.
Charge Pump
This is the charge pump circuit KI setting. The value can be changed by moving the cursor to the position of
the number and pressing the Return or Enter key. KI can be set to "00" (about 100µA), "10" (about 400µA) or
"11" (about 1.6mA).
The setting "01" is not used. (Setting "01" is the same as setting "00".)
Polarity
These are the SYNC, DSYNC and PD (Phase Detector) polarity inversion settings, and should be set as
necessary such as when inverting the SYNC input and DSYNC output waveforms. The setting value "1" is
positive polarity, and "0" is negative polarity. These should normally all be set to "1". (Fix PD to "1" other than
during test mode.)
– 48 –
CXA3106AQ
Power
SCAN:
This is the control register read setting. When this is ON, the control register serial data is
output from SEROUT (Pin 15). This should normally be set to OFF.
SYNTH:
This is the enable/disable setting for this IC. This should normally be set to ON.
VCO Bypass: This is set to OFF when testing the program counter. This should normally be set to ON.
O/P Enable
These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2,
CLK1 and NCLK1). Set to ON when performing evaluation using TTL output.
– 49 –
CXA3106AQ
C) Description of readout mode
This program has a function (readout mode) that reads the contents written to the control registers from the
CXA3106AQ SEROUT (Pin 15) and displays these contents on the screen. This function is described below.
1) Set SCAN to ON at the function setting screen.
2) Press the S key.
The following screen appears.
SCAN RESULT, CXA3106 PLL REGISTERS
Register 1 DIVREG1
00111000
Register 2 DIVREG2
0101
Register 3 CENFREREG
1011111
Register 4 DELAYREG
0010000
Register 5 CPREG
100
Register 6 TTLPOLREG
00000011
Register 7 TESTPOWREG
0111
Press r to return to PLL REGISTERS MENU.
Press a to abort
MIXED SIGNAL SYSTEMS AUG 1996
This screen conforms to the Control Register Table listed in the CXA3106AQ specifications.
3) Press the R key to return to the original function setting screen.
D) Quit the program
Press the A key to quit the program.
– 50 –
CXA3106AQ
AAAAAA
AAAAAAAAAAAAA
AA
AAA
A
AAAAAAAA
AAAAAAAAAAAAA
AAAAAA
AA
AAA
AAAAAAAA
AAAAAAAAAAAAA
AAAAAA
AAA
AAAAAAAA
AAAAAAAAAAAAA
AAAAAA
AAAAA
AAAAAAAAA
AAAAA
AAAAA
Substrate Pattern (parts surface)
Substrate Pattern (solder surface)
– 51 –
CXA3106AQ
VCO
VCOL
BNC3
VCC
VCOH
BNC2
GND
C21
33µ
+
BNC1
R1
PR10
VBB
CXA3106Q/AQ PWD v1.2
R19
R8
BNC4
SYNCH
R3
PR8
DSYNCL
R10
S1
S2
BNC5
SYNCL
R7
IC1
PR6
CLKL
R4
R11
R6
PR1
CLK/2L
PR4
UNLOCK
PR11
CLK/2N
PR12
CLK/2
PR13
CLKN
PR14
CLK
1C
21C
31C
4C
6C
81C
41C
02C
5C
C3
2C
01C
11C
7C
81C
51C
71C
61C
Silk Screen (solder surface)
– 52 –
PR5
CLK/2H
PR15
DSYNC
Silk Screen (parts surface)
91C
R5
R12
C9
C8
DBUS1
Control Register
R13
PR3
DIVOUT
PR7
CLKH
S3
S4
S5
S6
SYNC
PR2
SEROUT
PR9
DSYNCH
R9
R14
BNC6
R2
C21
33µ
VCC
5
1
GND
DBUS1
GND
SYNC
9
12
S3
SEROUT
S6
15 16
DIVOUT
CXA3106AQ
19 20
C7
0.1µ
17 18
PR2A
PR4A
PR3A
SEROUT DIVOUT UNLOCK
S4
S5
14
13
SDATA
11 SCLK
VCC
PWR2
GND
SYNCL
SYNCH
8
HOLD
6
VCO
5
7
VCOL
4
21
22 23
24
TTLGND 25
TTLVCC 26
IOGND 27
PECLVCC 28
CLK/2L 29
CLK/2H 30
CLKL 31
CLKH 32
DSYNCL 33
DSYNCH 34
VCOH
3
10 SENABLE
PWR1
S2
BNC6
SYNC
S1
SYNCL
BNC5
SYNCH
BNC4
VBB 35
PECLVCC 36
IOVCC
IOGND
IRVCC
2
IRGND
1
UNLOCK
C2
0.1µ
38 37
40 39
42 41
43
44
45
48 47 46
DVCC
VCO
CLK/2N
VCOL
C12
0.1µ
VCOGND
DGND
BNC3
C3
0.1µ
CLKN
BNC2
C6
0.1µ
RC1
C5
0.1µ
RC2
C4
0.1µ
IREF
C11
100p
VCOHGND
R19
1.6k
GND
VCOVCC
PLLGND
CLK/2
VCOH
R18 C19
3.3k 0.33µ
C20
1200p
PLLVCC
IOVCC
CLK
DSYNC
BNC1
Note) R1 to R7 are not mounted.
Control Register
IOGND
TLOAD
– 53 –
CS
PWB Circuit Diagram
GND
C9
0.1µ
C10
0.1µ
C8
0.1µ
VCC
C17
0.1µ
C16
0.1µ
C18
0.1µ
C15
0.1µ
C14
0.1µ
C13
0.1µ
C1
0.1µ
R6
R5
R7
R4
R3
R2
R1
VCC
R13 330
R12 330
R14 330
R11 330
R10 330
R9 330
R8 330
GND
CLK/2N
CLK/2
PR11A
CLKN
PR12A
CLK
PR13A
DSYNC
PR14A
PR15A
CLK/2L
PR1A
CLK/2H
PR5A
CLKL
PR6A
CLKH
PR7A
DSYNCL
PR8A
DSYNCH
PR9A
VBB
PR10A
CXA3106AQ
CXA3106AQ
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
13.5
37
48
+ 0.2
0.1 – 0.1
13
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-48P-L04
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
∗QFP048-P-1212-B
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 54 –
Sony Corporation