CXA3202N TX Gain Control Amplifier For the availability of this product, please contact the sales office. Description CXA3202N is a TX gain control amplifier suitable for CDMA cellular/PCS phone. 16 pin SSOP (Plastic) Features • Wide gain control range • Linear gain slope • Wideband operation (50MHz to 300MHz) • Very small package (16 Pin SSOP) • Low voltage operation • High output IP3 • Power save function included Absolute Maximum Ratings • Supply voltage VCC 6 V • Operating temperature Topr –55 to +125 °C • Storage temperature Tstg –65 to +150 °C • Allowable Power dissipation PD 330 mW • Supply voltage range –0.3 to 6 V • Logic input voltage –0.3 to VCC + 0.3 V • Signal input voltage –0.3 to VCC + 0.3 V • Differental signal input voltage 0 to 2.5 V Operating Condition Supply voltage VCC 2.7 to 3.8 V Applications CDMA cellular/PCS phone Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97808-PS CXA3202N Block Diagram IF Input Gain control Supply Voltage CDMA IN OUT CDMA INX OUTX GCTL VCC1, 2 Bias Driver Ground Power Save GND1, 2 PSV Pin Configuration CDMA IN 1 16 GCTL CDMA INX 2 15 NC NC 3 14 VCC1 GND1 4 13 VCC2 GND2 5 12 GND1 NC 6 11 GND2 NC 7 10 OUT PSV 8 9 –2– OUTX IF Output CXA3202N Pin Description Pin No. 1 Symbol CDMA IN Pin voltage TYP (V) Equivalent circuit Description 1.1 40k 40k Differential input pins for CDMA transmit IF signal. 2 CDMA INX GND 1.1 1 2 3 6 7 15 NC 4 12 GND1 0 Ground 5 11 GND2 0 Ground No connection. VCC1 8 PSV — Power save function pin. High: Active Low: Power save 8 135k GND 10 9 9 10 OUTX OUT — 510 510 12.25k 12.25k VCC2 Differential output pins for transmit IF signal. Open collector output. — GND 13 VCC2 3.0 Positive power supply for output stage. 14 VCC1 3.0 Positive power supply. –3– CXA3202N Pin No. Symbol Pin voltage TYP (V) Equivalent circuit Description VCC1 8k 16 GCTL — 8k Gain control pin. 16 6k 6k GND –4– CXA3202N Electrical Characteristics (VCC = 3.0V, Ta = 27°C) DC Characteristics Parameter Symbol Conditions Min. Typ. Max. Unit Current consumption 1 ICC1 Vpsv = 3.0V, Vgctl = 1.5V, Pin 13, 14 10 Current consumption 2 ICC2 Vpsv = 0 V, Vgctl = 1.5V, Pin 13, 14 5 Input current pin 8H IpsvH Vpsv = 3.0V Input current pin 8L IpsvL Vpsv = 0 V Input current pin 16H IgctlH Vgctl = 3.0V Input current pin 16L IgctlL Vgctl = 0.5V –1 PSV high voltage VpsH Pin 8 2.5 PSV low voltage VpsL Pin 8 18 mA 40 1 µA –15 1 0.5 AC Characteristics Parameter 15.7 21.5 V (VCC = 3.0V, Ta = 27°C) Symbol Conditions Min. Typ. Max. Unit Operating frequency range Fr Gain 2.3 G2.3 f = 130.38MHz, level = –22.5dBm, Vgctl = 2.3V 13 17 21 Gain 1.5 G1.5 Vgctl = 1.5V –28 –24 –20 Gain 1.0 G1.0 Vgctl = 1.0V –58 –54 –50 Gain 0.7 G0.7 Vgctl = 0.7V –75 –70 –65 CDMA Gain slope GCLIN 56 59 62 Input level 3rd order intercept point IIP3 Noise Figure NF Gain at Vgctl = 2.0V – Gain at Vgctl = 1.0V G = 15dB∗1 f1= 129.38MHz, f2 = 131.38MHz Measure of 130.38MHz G = 15dB∗1 Measure of 130.38MHz 300 MHz 50 ∗1 Adjust GCTL voltage, and set the overall gain to 15dB. –5– dB/V dBm –8.5 –4.5 28 dB 32 dB CXA3202N Measurement Circuit 1µ ∗1 V16 1k 2k 1 CDMA IN GCTL 16 A16 1000p CDMA INPUT 1000p 2 CDMA INX ∗2 0.01µ NC 15 V14 VCC1 14 3 NC A14 0.01µ 4 GND1 VCC2 13 5 GND2 GND1 12 820n∗3 6 NC GND2 11 7 NC OUT 10 820n∗3 2.4k ∗1 OUTPUT V8 A8 8 PSV OUTX 9 ∗1 TOKO, Inc. B5FL 616DS-1135 ∗2 Coilcraft, Inc. 1008HS-102TKBC ∗3 Coilcraft, Inc. 1008HS-821TKBC –6– CXA3202N Application Circuit VCC 1000p 1k GCTL 16 1 CDMA IN CDMA RX IF INPUT ∗ Gain Control Voltage 0.01µ ∗ NC 15 2 CDMA INX 100p 1000p 0.01µ 3 NC VCC1 14 4 GND1 VCC2 13 5 GND2 GND1 12 6 NC GND2 11 ∗ 1000p 7 NC OUT 10 RX IF OUTPUT Active Sleep 8 PSV OUTX 9 1000p ∗ ∗ Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– CXA3202N Design Reference Values Single ended measurement Item (VCC = 3.0V, Ta = 27°C) Conditions Symbol Typ. Unit 10 kΩ 0.98 pF Input resistance Rin Input capacitance Cin Output resistance Rout 6.0 kΩ Output capacitance Cout 0.92 pF f = 130.38MHz, Vgctl = 1.5V Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin and VCC Pin should be as close to the IC as possible. 2) The resistors connected to Pins 9 and 10 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 1 and 2 is 500Ω. Refer to the Measurement Circuit for the external element settings, etc. 4) Pay attention to handling this IC because its electrostatic discharge strength is weak. –8– CXA3202N IIP3 Sensitivity 15 40 VCC = 3.0V VCC = 3.0V 20 10 5 IIP3 [dBm] Power gain [dB] 0 –20 –40 0 –5 –60 T = –40°C T = 27°C T = 85°C –80 –10 –15 –60 –100 0 0.5 1 1.5 2 2.5 3 T = –40°C T = 27°C T = 85°C 3.5 –40 –20 0 20 40 Power gain [dB] Vgctl [V] Gain Error from Room Temp Noise Figure 100 6 VCC = 3.0V VCC = 3.0V 90 4 Gain error [dB] Noise figure [dB] 80 70 60 50 40 30 20 –80 T = –40°C T = 27°C T = 85°C –60 –40 2 0 –2 T = –40°C T = 85°C –4 –20 0 –6 –80 20 –60 –40 –20 0 Power gain [dB] Power gain [dB] –9– 20 40 CXA3202N Package Outline Unit: mm 16PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗5.0 ± 0.1 0.1 16 9 1 6.4 ± 0.2 ∗4.4 ± 0.1 A 8 + 0.05 0.15 – 0.02 0.65 + 0.1 0.22 – 0.05 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-16P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE SSOP016-P-0044 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 10 –