CXA3271GE
Fingerprint Sensor
Description
The CXA3271GE is an electrostatic capacitance
method fingerprint sensor.
This monolithic IC integrates the sensor block, sense
amplifier (3-bit gain adjustment), sample-and-hold,
output amplifier and output buffer needed to acquire
fingerprint images, as well as the timing generator for
determining the operation of these functions onto a
single chip.
30 pin LLGA
Features
• Electrostatic capacitance type sensor (charge transfer method)
• Number of pixels: 192 × 128
• 317 DPI
• Low power consumption (50mW or less)
• Single 3.3V power supply
• Sensor gain control: 3 bits
• S/N ratio improved by on-chip sensor block parasitic capacitance cancel function
Applications
Fingerprint verification units
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
• Input voltage
• Output voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation
VDD
VI
VO
Topr
Tstg
PD
VSS – 0.5 to +7.0
V
VSS – 0.5 to VDD + 0.5
V
VSS – 0.5 to VDD + 0.5
V
–20 to +75
°C
–25 to +125
°C
970
mW
Operating Conditions
• Supply voltage
• Recommended operating temperature
3.15 to 3.45
0 to +50
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00235-PS
CXA3271GE
Block Diagram
C_SP
UC
UC
Timing
Generator
CLK (D/I)
SENSOR
........ 128 .........
UC
XSP (D/I)
UC
128
Column Shift Register
C_CLK
UC
ADCLK (D/O)
UC UC UC UC ........... 192 ........... UC UC UC UC
192
S_CNT
Sense AMP (×192)
3bit
DAC
DI (D/I)
192
Load
S/H & SW (×192)
Output
Buffer
AOUT (A/O)
192
R_SP
Row Shift Register
VOS (Bias)
R_CLK
–2–
3
CXA3271GE
Detailed Block Diagram
Pin Symbol
LAND No.
C_CLK
VOS
BUF
OAMP
VCS_O
BIAS_O
C_COUT
SR
C_LOG
C_SP
SRN (1 to 128)
128
28
AVDD (P/S)
7C
27
AVSS (P/S)
7D
26
AOUT (A/O)
7E
25
VCS_O (Bias)
7F
24
VOS (Bias)
6B
23
VH (Bias)
6C
22
VM (Bias)
6D
21
VL (Bias)
6E
20
VCS_S (Bias)
6F
19
DVDD (P/S)
5B
18
DVSS (P/S)
5C
17
DVSS (P/S)
5D
16
CSRO (D/O)
5E
15
RSRO (D/O)
5F
14
ADCLK (D/O)
4F
13
C_CK (D/O)
4E
12
C_CLK (D/I)
4D
11
CLK (D/I)
4C
10
HD (D/I)
4B
9
XSP (D/I)
3F
8
DI2 (D/I)
3E
7
DI1 (D/I)
3D
6
DI0 (D/I)
3C
5
MODE (D/I)
3B
4
TEST2 (D/I)
2F
3
TEST1 (D/I)
2E
2
AVSS (P/S)
2D
1
AVDD (P/S)
2C
C_CO
R_LOG
CLK
XSP
SC (1 to 192) N
SC (1 to 192)
DCLK
192
192
VH
VM
VL
OUT
DA AMP
OUT
IN
VL
VDS
DA
3
2
–3–
BIAS_SA
DA AMP
OUT
IN
DA AMP
OUT
IN
VS (1 to 8) N
VS (3 to 8)
VH
6
8
D1 (D to 2)
VS (3 to 8)
VS (1 to 8) N
DEC
VM
DA AMP
OUT
IN
DCLK
XSP
TEST1/2
IN_N (1 to 192)
S (1 to 5) N
S (1 to 5)
SAMP (192)
VH
VM
SC (1 to 192)
SC (1 to 192) N
VL
D (1 to 192)
5
S (1 to 5)
XSP
MODE
HD
C_CLK
C_CK
192
5
TG
S (1 to 5) N
C_SP
DSELN
UC UC UC ..................... 192 .................. UC UC UC
UC
SENSOR (UC)
UC
UC
UC
UC
........ 128 .........
UC UC UC ........... 192 (Dummy) ...........
UC UC UC
PG (1 to 128)
VCS_O
CXA3271GE
Pin Description
Serial
Land No. Symbol
No.
I/O
Description
2B
SUB
Power
Substrate electrode (chip rear surface electrode) 3.3V.
1
2C
AVDD
Power
Analog power supply 3.3V.
2
2D
AVSS
Power
Analog GND.
3
2E
TEST1
D/I
Test mode selection. Connect to GND.
4
2F
TEST2
D/I
Test mode selection. Connect to GND.
5
3B
MODE
D/I
Connect to GND.
6
3C
DI0
D/I
Gain setting input. (LSB)
7
3D
DI1
D/I
Gain setting input.
8
3E
DI2
D/I
Gain setting input. (MSB)
9
3F
XSP
D/I
Sense start pulse input (negative pulse).
The column and row shift registers and the timing generator are cleared
by this signal.
10
4B
HD
D/I
Connect to GND.
11
4C
CLK
D/I
Main clock. (1 to 2MHz)
12
4D
C_CLK
D/I
Column shift register clock.
Connect to C_CK (4E).
13
4E
C_CK
D/O
Column shift register clock output.
Connect to C_CLK (4D).
14
4F
ADCLK
D/O
Outputs the internally delayed input clock.
19
5B
DVDD
Power
Digital power supply 3.3V.
18
5C
DVSS
Power
Digital GND.
17
5D
DVSS
Power
Digital GND.
16
5E
CSRO
D/O
Column shift register final output. (Connection is not required.)
15
5F
RSRO
D/O
Row shift register final output. (Connection is not required.)
24
6B
VOS
A/O
Output amplifier reference voltage monitor. (1.65V)
23
6C
VH
A/O
Sensor charge voltage monitor. (1 LSB = 80mV)
Adjustable within the range of 1.92 to 2.48V by the three bits DI[0:2].
22
6D
VM
A/O
Sense amplifier reference voltage monitor. (1.85V)
21
6E
VL
A/O
Dummy cell charge voltage monitor for canceling parasitic capacitance.
VL = 2VM – VH
20
6F
VCS_S
A/O
Sense amplifier current source bias monitor.
(Do not connect.)
7B
SUB
Power
Substrate electrode (chip rear surface electrode) 3.3V.
28
7C
AVDD
Power
Analog power supply 3.3V.
27
7D
AVSS
Power
Analog GND.
26
7E
AOUT
A/O
Sensor output.
25
7F
VCS_O
A/O
Output amplifier and output buffer current source bias monitor.
(Do not connect.)
–4–
CXA3271GE
Electrical Characteristics
1. DC Characteristics
(Topr = 25°C, Vss = 0V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage
AVDD
3.15
3.3
3.45
V
Digital supply voltage
DVDD
3.15
3.3
3.45
V
Input voltage (High)
VIH
CMOS input cell
0.7VDD
VDD
V
Input voltage (Low)
VIL
CMOS input cell
Vss
0.3VDD
V
Output voltage (High) CMOS
VIH
VDD = 3.3V, IOH = –800µA
2.8
3.3
V
Output voltage (Low) CMOS
VIL
VDD = 3.3V, IOL = 2.4mA
0
0.4
V
Input leak current
IL
CMOS input pin
–5
5
µA
Output voltage
VH
VDD = 3.3V (D0 D1 D2) = (L L L)
1.92
V
Output voltage
VH
VDD = 3.3V (D0 D1 D2) = (H H H)
2.48
V
Output voltage
VL
VDD = 3.3V (D0 D1 D2) = (L L L)
1.76
V
Output voltage
VL
VDD = 3.3V (D0 D1 D2) = (H H H)
1.2
V
Output voltage
VM
VDD = 3.3V (D0 D1 D2) = (∗ ∗ ∗)
1.75
1.84
1.92
V
Output voltage
VOS
VDD = 3.3V (D0 D1 D2) = (∗ ∗ ∗)
1.55
1.65
1.75
V
Current consumption
IDD
VDD = 3.3V
4
10
14
mA
2. AC Characteristics
(Topr = 25°C, Vss = 3.3V)
Item
Applicable pins
Symbol Conditions Min. Typ. Max.
Clock input period
CLK
400
Output rise delay time
C_CK, ADCLK, RSRO, CSRO
Output fall delay time
C_CK, ADCLK, RSRO, CSRO
tpr
tpf
ns
CL = 30pF
160
ns
CL = 30pF
200
ns
5
Sensors
1300
mV
Number of sensor defects
AOUT
∗1
600
Output voltage Water Level AOUT
∗2
200
Output voltage Air Level
mV
Timing Definition
VDD
CLK
0V
VDD
0V
Output
tpr
VDD
0V
tpf
–5–
Unit
CXA3271GE
∗1 Output voltage Air Level means the output level in the condition where nothing is placed against the sensor
surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the
sensor output and then taking the average.
The gain setting for this measurement is (011).
∗2 Output voltage Water Level specifies the degree to which the output level changes from the Air Level when
a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each
sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level
when a drop of water is placed on the surface) are built into the sensor chip, and the average of these
output values is calculated. The difference from the Air Level noted above becomes the Water Level.
The gain setting for this measurement is (011).
–6–
CXA3271GE
Electrical Characteristics Measurement Circuit
Digital input pin
Digital output pin
Analog output pin
AVSS
AVDD
27
VCS_O/O
VH/O
0.1µF
VL/O
0.1µF
DVDD
0.1µF
DVSS
28
25
26
23
24
21
22
1.0µF
AOUT/O
VOS/O
VM/O
19
20
17
18
15
16
13
14
0.1µF
VCS_S/O
DVSS
RSRO/O
CSRO/O
C_CK/O
ADCLK/O
S1
CLK/I
C_CLK/I
11
12
9
10
7
8
5
6
3
4
1
2
XSP/I
HD/I
DI1/I
DI2/I
MODE/I
TEST1/I
AVDD
1.0µF
DI0/I
TEST2/I
AVSS
Vcc
3.3V
30pF or more is added to each pin.
–7–
CXA3271GE
Application Circuit
Flash
Registered data
Microcomputer
During
registration
DRAM
Fingerprint sensor chip
During
verification
ASIC
Binary value, verification
8-bit A/D
Verification results
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–8–
CXA3271GE
Description of Operation
,
,
• Fingerprint sensor principle
The principle of this newly developed fingerprint sensor
is described below. (Fig. 1) The sensor block contains an array of metal electrodes which are covered on top
by an insulating film (over coat). When a finger (which is conductive matter) is placed directly against this
surface, the three elements of the metal electrode, the insulating film and the finger form a capacitor.
The difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes,
and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge
capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air
in addition to this, making the difference between the ridge and valley capacitance values even greater than
the difference in distance.)
Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in
each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by
transferring and converting these charges to voltages.
Ridge
Valley
Fingerprint unevenness
Over coat
Metal electrode
Inter-layer film
Si
Fig. 1
–9–
CXA3271GE
S4
S6
Cf1
Cf2
Cs
Sr
Voi
Vsl
S5
Vcel
Sc
S7
S3
Cp
Vsns
Cp'
S11
VL
S2
Aout
Ch1
S_Amp
Vdmy
Sensor block
(192 × 128)
Buf
Voo
O_Amp
S1
Ch2
VOS
VM VH
Sense amplifier block
(192)
Output block
(1)
Fig. 2
• Fingerprint sensor operation (Fig. 2)
Description of characters
Cs: Capacitance formed between the finger and the metal electrode
Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate
Cp': Capacitance for canceling Cp (Cp ≈ Cp')
Ch∗: Hold capacitance
Cf∗: Feedback capacitance for determining the gain
S∗: Switch
V∗: Node voltage
VH – VM ≈ VM – VL
• Detailed description of operation
(All switches are off in the default status.)
1. S1, S4, Sr and S11 are turned on, Vcel is set to voltage VH, and Vdmy is set to voltage VL.
Vcel accumulated charge (Cs + Cp) VH
Vdmy accumulated charge Cp' VL
2. S1, Sr and S11 are turned off.
3. S2 is turned on and Vsl is set to VM.
4. S4 is turned off.
5. Sr, S3 and S5 are turned on.
At this time, the charge level that moves from Vcel and Vdmy to Vsl (actually between capacitances) is:
(Cs + Cp) (VH – VM) – Cp' (VM – VL) ≈ Cs (VH – VM)
This means that the sense amplifier gain is determined independently of the parasitic capacitance,
making it possible to obtain the required large signal dynamic range.
Vsns = VM – Cs (VH – VM)/Cf1
The voltage Vsns determined as shown above is accumulated in Ch1.
6. S5 is turned off.
7. S6 is turned on and the Voi voltage is set to VOS.
8. S6 is turned off.
9. Sc and S7 are turned on.
At this time, the charge level that moves from Ch1 to Cf2 is:
(VOS – Vsns) Ch1
This determines the Voo voltage which is accumulated in Ch2 and output to Aout via the buffer.
– 10 –
CXA3271GE
Appearance and Readout Order
15.36mm
Cell (1, 1)
Scan Formation
Cell (1, 1) to Cell (1, 192)
Cell (1, 192)
Sensor Area
192 × 128
10.24mm
Cell (128, 1)
16.8mm
Cell (128, 192)
Cell (128, 1) to
Cell (128, 192)
19.8mm
Flip
G
F
E
D
C
B
A
1
2
3
4
5
6
– 11 –
7
8
CXA3271GE
Notes on Operation
S4
S6
Cf1
Cf2
Cs
Sr
Voi
Vsl
S5
Vcel
Buf
Voo
Sc
S7
S3
Cp
Vsns
Cp'
S11
VL
S2
Aout
Ch1
S_Amp
Vdmy
O_Amp
S1
Ch2
VOS
VM VH
• Aout output variance
Aout output variance can be broadly classified into two types. The first is variance intrinsic to the IC, and the
second is variance caused by the influence of external noise due to the extremely high sensitivity.
• Variance intrinsic to the IC
1. The Aout output DC level fluctuates widely due to the IC.
This is caused by the Cp and Cp' capacitance values, the VM voltage level, the voltage differences VH – VM
and VM – VL, and the Vos voltage level in the figure above.
Vos, VH, VM and VL appear externally as pins. The Aout output level can be set to the desired potential
by applying the Vos voltage from an external source.
The Aout dynamic range is approximately 0.7 to 2.1V, so checking this output level and externally
applying the Vos voltage to set the optimum level is recommended.
2. 192 variances within one line
One line is comprised of 192 sensors. Each sensor is connected to a separate S_Amp, so the S_Amp
offset appears in the output. (approximately 100 to 200mV)
3. The DC level of a line changes with a certain regularity for some ICs. This is also caused by the S_Amp
DC offset.
• Variance due to the influence of external noise
1. Output fluctuation due to cross talk from the power supply
Power supply fluctuation has a large influence on the Aout output of this IC.
In addition to the capacitances between the power supply and GND (approximately 1µF, both sides if
possible), attaching capacitances of approximately 0.1µF to Vos, VH, VM and VL is recommended.
2. Finger stabilization
The human body acts as an antenna, so the finger potential changes during the sensing period, producing
noise in the Aout output. To prevent this, the potential of the area around the finger being sensed must be
equalized with the sensor GND. Measures such as placing a metal plate connected to GND around the
sensor so that the finger touches this place during sensing are recommended.
– 12 –
CXA3271GE
Fingerprint sensors have the silicon chip directly exposed, so care should be taken for the following points. In
addition, a cover should be attached to protect the sensor surface during operation.
Sensor surface electrostatic strength
Contact discharge (150pF, 330Ω): ±1.25kV or more
Body charge (when the charge accumulated in the body is discharged over the sensor surface): ±4kV or more
Body charge differs between individuals.
Sensor surface strength
The sensor surface is covered with only a thin coating in order to acquire fingerprint information.
Therefore, care should be taken when handling the sensor.
Problems have been confirmed not to occur during the following tests.
• Pressing 10,000 times with a finger (Pressing time: 2s/time)
• Rubbing 10,000 times with a finger (Back and forth, 2s/time)
• Scratching with a fingernail (20 times back and forth)
• Rubbing strongly with a pencil (6H hardness) (20 times back and forth)
• Rubbing with a tissue (1,000 times back and forth)
Note that problems also occurred with the sensor surface during the following tests.
• Pressing strongly with a needle (normal sewing needle)
• Rubbing with an eraser
• Rubbing with the tip of a ball point pen
• Rubbing with steel wool
– 13 –
CXA3271GE
Timing Chart
500ns
XSP
(3F)
CLK
(4C)
Strobe
Point
250ns
250ns
250ns
480ns
Input level
VIH = 0.7VDD
VIL = 0.3VDD
Output level
High
0.65VDD
X
0.35VDD
Low
– 14 –
CXA3271GE
Input/output Signal
CK1 clock 2MHz
Strobe point (CK Rise + 480ns)
CLK
(4C)
Input
F = 2.0MHz
500ns (1clk)
250ns
XSP
(3F)
Input
750ns
750ns
C_CK
(4E)
Output
500ns
(1clk)
96.5µs
(193clk)
31.5µs
(63clk)
96.5µs
(193clk)
31.5µs
(63clk)
256 clk
RSRO
(5F)
Output
96µs
(192clk)
500ns
(1clk)
500ns
(1clk)
CSRO
(5E)
Output
16384µs
(32768clk) {(193 + 63) × (2 + 126)}
– 15 –
128µs
(256clk)
CXA3271GE
250ns
XSP
(3F)
Input
750ns
750ns
C_CK
(4E)
Output
500ns
(1clk)
96.5µs
(193clk)
31.5µs
(63clk)
96.5µs
(193clk)
31.5µs
(63clk)
(Repeat 128 Times)
AOUT
(7E)
Output
Analog output
256.5µs
(513clk)
((192 + 1 + 63) × 2 + 1)
96µs
(192clk)
1st Culumn
32µs
(64clk)
96µs
32µs
(192clk)
(64clk)
2nd Culumn
Air level
0.6 to 1.3V
2.0V
AOUT
(7E)
Detail
D-range average
analog output
0.6V
500ns
(1clk)
– 16 –
CXA3271GE
Package Outline
Unit: mm
30PIN LLGA
AA
∗2.6 ± 0.25
20
A
A A
(10.04)
4-R1.0MAX
17
0.2 M S B
PIN1 INDEX
X
1.45 ± 0.2
0.05MAX
0.2 ± 0.2
∗2.42 ± 0.25
∗12.64 ± 0.25
∗17.58 ± 0.25
(15.16)
0.1 S
0.2 M S A
(0.85)
Y
0.15
SENSOR AREA
S
AA
AA AA
52-φ1.2 ± 0.08
C
B
A
0.25MAX
TYP
DETAIL Y
B
A
AA A
1 2 3 4 5 6 7 8
2.2
2.3
3.65
NOTE1: Dimension “∗” does not include
breedout of sensor area.
3.42
2.07
2.2 2.07
A
G
F
E
D
M S AB
2.54
2.54
2.3
3-φ2.2
φ0.1
0.25MAX
TYP
DETAIL X
NOTE2: The length of breedout is 0.25MAX.
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
LLGA-30P-01
ORGANIC SUBSTRATE
TERMINAL TREATMENT GOLD PLATING
EIAJ CODE
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 17 –
COPPER PLATING
0.7 g
Sony Corporation