CXA3541N 2-channel Read/Write Amplifier for GMR-Ind Head Hard Disk Drive Description The CXA3541N is a read/write amplifier for GMR-Ind (Giant Magneto Resistive-Inductive) heads used in hard disk drives, and is capable of supporting up to two channels. Features • +5V and –3V power supply • Current bias voltage sense type • Low power 180mW at read • Differential read amplifier gain; ×100/135 (RMR = 50Ω) • Input noise of 0.77nV/√ Hz (typ.), RMR = 50Ω, IB = 5.9mA • Recovery time write to read; 300ns (typ.) • Write data is triggered by differential P-ECL signal • Servo bank write • Write unsafe detection circuit • Serial port Head selection MR bias Write current Applications Hard disk drives with GMR-Ind heads 24 pin SSOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) –0.3 to +5.8 V • Supply voltage VCC • Supply voltage VEE –3.7 to +0.3 V • Digital input voltage Vdi –0.3 to VCC + 0.3 V • Operating temperature Topr 0 to +70 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 800 mW (on board) Operating Conditions • Supply voltage • MR bias voltage • Bias current • Write current Structure Bipolar silicon monolithic IC VCC VEE VMR IB IW 4.4 to 5.5 V –3.5 to –2.6 V –300 to +300 mV 3 to 8 mA 19.5 to 49.5 mA Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00205-PS CXA3541N Block Diagram and Pin Configuration SCLK 1 SDATA 2 WDX 3 Serial Interface Bias Current Source 24 RS 23 NC WD BUF Write Current Source 22 R1Y AMP WDY 4 21 R1X VCC 5 20 W1Y GND 6 RDY 7 DRIVER 19 W1X 18 W0X AMP RDX 8 FLT/SE/BHV 9 DRIVER 17 W0Y 16 R0X AMP R/XW 10 15 R0Y SDEN 11 14 NC VEE 12 13 CAP –2– CXA3541N Pin Description Pin No. Symbol Equivalent circuit Description VCC 1 1 2 11 SCLK SDATA SDEN 7.5k 2 Serial control signal input. 11 14k 2Vf GND VEE VCC 100 3 4 WDX WDY 3 Differential P-ECL write data input. 4 100 GND VEE 5 VCC 5V power supply. 6 GND Ground. VCC 100 7 8 RDY RDX Read amplifier output with coupling capacitors. High impedance in the write mode. 7 8 1.8mA GND VEE VCC 9 FLT/SE/BHV Head unsafe detection output. Servo bank write enable input. Buffered head voltage output. 9 GND VEE –3– CXA3541N Pin No. Symbol Equivalent circuit Description VCC 10 R/XW Read/write control signal input. Read when high, write when low. 10 3Vf GND VEE 12 –3V power supply. VEE VCC 13 CAP Connect an external capacitor of read amplifier between this pin and VEE. 13 VEE 14 23 NC Non connection. VCC 16 15 21 22 R0X R0Y R1X R1Y 16 21 MR heads for read. Two channels are provided. 15 22 VEE VCC 18 17 19 20 W0X W0Y W1X W1Y 18 19 Inductive heads for write. Two channels are provided. 17 20 GND VEE –4– CXA3541N Pin No. Symbol Equivalent circuit Description VCC 24 RS Bias current setting register is connected between this pin and GND. 250 24 VBGR = 1.3V GND VEE –5– CXA3541N Electrical Characteristics (Unless otherwise specified; VCC = 5V, VEE = –3V, Ta = 25°C, CAP = 0.1µF, RS = 7.5kΩ) No. Item Power Dissipation Symbol Measurement conditions Min. Typ. Max. Unit 2.15 2.85 mA IW = 29.5mA, IB = 5.9mA 1-1 ISP1 Sleep mode IID1 Idle mode 22 29 mA IRE1 Read mode 37 48 mA 1-4 IWR1 Write mode 98 130 mA 1-5 IID2 Idle mode 10 13 mA IRE2 Read mode 10 13 mA IWR2 Write mode 10 13 mA ICCBW ICCBW = 17 + 17 × N + IW × N IW = 29.5mA 111 1-2 1-3 1-7 VCC power supply current VEE power supply current 1-8 1-9 Bank write mode mA Digital Inputs 2-1 TTL input low input voltage VIL 2-2 TTL input high input voltage VIH 2-3 TTL input input current ITTL 2-4 Serial interface input low input voltage VSIL 2-5 Serial interface input high input voltage VSIH 2-6 Serial interface input input current VST High voltage: 3.3V Low voltage: 0V Pull-down resistor: 14kΩ –500 500 µA 3-1 P-ECL common voltage VPC (VH + VL)/2 1.55 VCC V 3-2 P-ECL differential voltage VPD (VH – VL) 0.2 1.5 V 3-3 P-ECL high voltage VPH VCC V 3-4 P-ECL input current IWD –20 20 µA Power Dissipation TTL input; R/XW Internal pull-up resistor High voltage: 5V Low voltage: 0V Serial input; SDATA, SCLK, SDEN Input voltage: 4V 0 0.8 V 2.0 VCC + 0.3 V –200 200 µA 0.8 V V 2.35 IW = 29.5mA, IB = 5.9mA 4-1 Bank write enable voltage VSEH VCC + 1.2 VCC + 1.4 V 4-2 Bank write enable current ISEH 6 14 mA 5-1 FLT output low voltage VFLTL Open collector output External resistance = 2.4kΩ 0.8 V 5-2 FLT output high voltage VFLTH Open collector output External resistance = 2.4kΩ 4.5 BHV gain accuracy EBHV VBHV = VCC – 4 × IB × (RMR + 5.5Ω) IB = "111", RMR = 50Ω –8 6 –6– V 8 % CXA3541N No. Item Read Characteristics Symbol Measurement conditions Min. Typ. Max. Unit RMR = 50Ω, IB = 5.9mA R1 Low gain AVL Gain = 0 RMR = 50Ω, IB = 5.9mA 82 100 118 V/V R2 High gain AVH Gain = 1 RMR = 50Ω, IB = 5.9mA 110 135 160 V/V R3 Low frequency cut-off (–3dB) FCL 350 550 kHz R4 High frequency cut-off (–3dB) FCH R5 Input reflected noise ENi R6 MR bias current range 1 IBR1 R7 MR bias accuracy EIB R8 MR bias resolution RIB 3-bit DAC R9-1 VCC power supply rejection ratio PSRR1 Ripple voltage: 100mVp-p 100kHz to 50MHz 38 dB R9-2 VEE power supply rejection ratio PSRR2 Ripple voltage: 100mVp-p 100kHz to 10MHz 45 dB R10-1 Common mode rejection ratio 1 CMRR1 Ripple voltage: 100mVp-p 100kHz to 50MHz 37 dB R10-2 Common mode rejection ratio 2 CMRR2 Ripple voltage: 100mVp-p 51MHz to 80MHz 27 dB R11 Control line input noise rejection CLRR Ripple voltage: 100mVp-p 4MHz to 80MHz 40 dB R12 RDX/RDY offset difference magnitude VOFF1 Write to read R13 RDX/RDY output impedance RDro Differential, read mode 30 140 200 MHz 0.95 nV √ Hz 3 8 mA –7 +7 % Exclusive of head noise RMR = 50Ω, IB = 5.9mA 0.77 0.714 mA 50 mV 100 Ω Read Safety Characteristics P1 MR head open threshold MRop Head X – Head Y 600 750 900 mV P2 MR head short threshold MRsh Head X – Head Y IB = "000" to "011" 15 50 90 mV 19.5 49.5 mA –7 +7 % Write Characteristics W1 Write current range IWR DAC code = x "0000" to x "1111" W2 Write current accuracy EIW RH = 0Ω W3 Write current resolution RIW 4-bit DAC W4 Leakage current ILEAK Unselected head W6 Damping resistor RD W7 Write current propagation delay time Tpd W8 Write current rise/fall time TR/TF W9 Erase current accuracy W10 Bank write current accuracy EIE 2 800 1000 LH = 0, RH = 0 Write data to 50% of write current Refer to Fig. –7– 200 µA 1200 Ω 10 ns 1.9 RH = 15Ω, LH = 150nH, IW = 25mA VCC = 3.5V DAC code = x "0101" mA –18 –9 ns 0 % CXA3541N No. Item Symbol Measurement conditions Min. Typ. Max. Unit 1.2 1.4 V 0.1 V 1.8 MHz 300 + T1 ns Write Safety Characteristics U1 Write head open threshold Rop Detect open head U2 Head voltage when short to GND VG Detect short to GND U3 WD frequency too low fWDL U4 Write safety detect time Tws T1: 2 transitions on WDX/WDY U5 Low VCC threshold VWthL Fault detected 3.7 3.9 4.1 V U6 Low VCC threshold VWthH Fault removed 3.9 4.1 4.3 V U7 Low VCC threshold hysteresis Vhys Switching Characteristics 0.5 mV 200 Iw = 29.5mA, IB = 5.9mA S1 Write to Read TWR Signal on WDX/WDY 90% RD signal or 10% IW 300 500 ns S2 Read to Write TRW 90% IW 50 70 ns S3 Idle to Read TIR 90% RD signal 1.0 µs S4 Sleep to Read TSR1 90% RD signal, 90% IB∗1 IB = "011" 2000 µs Bank Write Characteristics 600 Iw = 29.5mA, IB = 5.9mA S5 Read to Bank write TRB 90% IW 100 ns S6 Bank write to Read TBR 10% IW 100 ns S7 Idle to Bank write Idle to Write TIW 90% IW 300 µs Serial Port Timing 30 ns 15 ns B1 Setup time TSU (sden) SDEN to first SCLK B2 Hold time Th (sden) B4 SCLK frequency f (sclk) B5 SCLK pulse width Tw (sclk) 10 ns B6 SCLK – SDATA setup time TSU (d) 10 ns B7 SCLK – SDATA hold time Th (d) 10 ns B8 SDEN low time TSL 100 ns Last SCLK to deassert SDEN 30 ∗1 TSR is proportional to IB and external CAP value. –8– MHz CXA3541N Serial Port Characteristics ADR1 ADR0 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0 0 XSLP XIDL N/A N/A N/A HS 0 1 GAIN BHV N/A IB2 IB1 IB0 1 0 MROPN MRSHT IW3 IW2 IW1 IW0 ∗ IB[2:0] bits are initialized by "0" at power on. Code Description Bit Function XSLP 0 = Set the pre-amplifier into low power "sleep" mode. XIDL 0 = Set pre-amplifier to idle mode. HS Head select bit. GAIN Set the pre-amplifier to high or low gain mode. 1 = Set pre-amplifier to high gain mode. BHV Active the BHV test point pin. "1" active. IB[2:0] MR bias current set. MROPN 1 = Set MR head open detector active. MRSHT 1 = Set MR head short detector active. IW[3:0] Set write current. –9– CXA3541N Mode Control SLEEP XSLP = 0 READ IDLE WRITE XSLP = 1 XIDL = 1 R/XW = H XSLP = 1 XIDL = 0 R/XW = X XSLP = 1 XIDL = 1 R/XW = L Serial Port Timing Detail TSL SDEN f (sclk) Tsu (sden) Th (sden) Tw (sclk) SCLK Th (d) Tsu (d) SDATA A1 A0 D5 D4 D3 D2 D1 D0 Serial Port Timing After the SDEN goes high, the last eight bits are transferred into the register. The SCLK will shift the data presented at SDATA into an internal shift register on the rising edge of each clock. As SCLK initial condition, both of low and high signal is acceptable. – 10 – CXA3541N Unsafe Condition 1. Write fault condition FLT is a high level in write fault condition. • Open write head leads. fWD < 15MHz • Write head leads shorted to ground. • WD frequency is too low. • Power supply is out of tolerance. 2. Read fault condition FLT is a low level in read fault condition. • Open short MR head. (This function is set by serial resister.) Bank Write Control (Refer to Bank "Write current vs. Current accuracy" characteristic curve) 1. Set the read mode. 2. Force a certain voltage (min. VCC + 1.2V) to FLT/SE pin by using the pull-up register. (RSE = 820Ω) #This operation disables all fault detection. 3. Set VCC at 3.5V (in case of the erase mode only) 4. Start the write operation by setting R/XW = L. 5. Terminate the write operation by setting R/XW = H. i) Allow 50% write duty or less. ii) Low voltage detector is disabled in the bank write mode and erase mode. iii) Don't change the serial register data bits in following conditions: • VCC = 3.5V • On entering write data. BHV (Buffered Head Voltage) 1. Applicable within VCC = 5V ± 5%. 2. Turn BHV on, but turn off MROPN and MRSHT. 3. VBHV is determined by basis of VCC. VBHV = VCC – (4 × IB × (RMR + 5.5Ω)) Head Condition 1. Short X-Y terminal on un-used write head. 2. Recommended X-Y terminal on un-used read head short. Polarity 1. Read output signal on RDX is negative, when MRX is positive by increasing RMR. 2. Write current flows into X side, when WDX is high and WDY is low. Head Select Table (2ch) HS Normal operation 0 0 1 1 – 11 – CXA3541N MR Bias IB2 IB1 IB0 IB [mA] 0 0 0 3.0 0 0 1 3.714 0 1 0 4.429 0 1 1 5.143 1 0 0 5.857 1 0 1 6.571 1 1 0 7.286 1 1 1 8.0 IW3 IW2 IW1 IW0 Write current [mA0-P] 0 0 0 0 19.5 0 0 0 1 21.5 0 0 1 0 23.5 0 0 1 1 25.5 0 1 0 0 27.5 0 1 0 1 29.5 0 1 1 0 31.5 0 1 1 1 33.5 1 0 0 0 35.5 1 0 0 1 37.5 1 0 1 0 39.5 1 0 1 1 41.5 1 1 0 0 43.5 1 1 0 1 45.5 1 1 1 0 47.5 1 1 1 1 49.5 Write Current Actual head current is defined by the following equation: IHEAD = IW/(1 + RH/RD) RH: Head resistance RD: Damping resistance – 12 – CXA3541N Electrical Characteristics Measurement Circuit 7.5kΩ 1 SCLK RS 24 2 SDATA NC 23 3 WDX R1Y 22 4 WDY R1X 21 5 VCC W1Y 20 25Ω V WDX 3300µH 1µF Amp1 Gain = ×1 V WDY S7 1000pF S6 VPSRR 150nH 10µF R13 1.5k 25Ω 6 GND W1X 19 7 RDY W0X 18 8 RDX W0Y 17 9 FLT/SE/BHV R0X 16 10 R/XW R0Y 15 11 SDEN NC 14 CAP 13 1000pF VM1 V R14 1.5k 150nH VCC 2.4k 1000pF 25Ω V SE 25Ω Amp2 Gain = ×100 V R/XW VEE BPF 100kHz to 50MHz V VM2 12 VEE 1kΩ VPSRR' 1µF S7' S/I S6' 0.1µF 3300µH – 13 – 0.1µF CXA3541N Application Circuit 7.5kΩ 5V 1 SCLK RS 24 2 SDATA NC 23 3 WDX R1Y 22 4 WDY R1X 21 5 VCC W1Y 20 6 GND W1X 19 7 RDY W0X 18 8 RDX W0Y 17 9 FLT/SE/BHV R0X 16 10 R/XW R0Y 15 11 SDEN NC 14 CAP 13 0.1µF –3V 12 VEE 0.1µF 0.1µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXA3541N Normalized bias current vs. Ambient temperature Normalized bias current vs. Power supply voltage 1.04 1.04 VCC = 5V VEE = –3V RMR = 50Ω IBn = "100" 1.02 IB/IB (VCC = 5V) IB/IB (Ta = 25°C) 1.02 1.00 0.98 1.00 0.98 0.96 0.0 –25.0 25.0 50.0 0.96 3.5 75.0 4.0 4.5 5.0 5.5 6.0 6.5 Ta – Ambient temperature [°C] VCC [V] Normalized read amplifier voltage gain vs. Ambient temperature Normalized read amplifier voltage gain vs. Power supply voltage 1.06 1.04 VCC = 5V VEE = –3V RMR = 50Ω IBn = "100" High gain 1.02 VEE = –3V RMR = 50Ω IBn = "100" High gain Ta = 25°C 1.02 AV/AV (VCC = 5V) 1.04 AV/AV (Ta = 25°C) VEE = –3V RMR = 50Ω IBn = "100" Ta = 25°C 1.00 0.98 1.00 0.98 0.96 0.94 –25.0 0.0 25.0 50.0 0.96 3.5 75.0 Ta – Ambient temperature [°C] 4.0 4.5 5.0 VCC [V] 5.5 Bank write current vs. Current accuracy 0 VCC = 5V Ta = 25°C Bank write current accuracy [%] –2 RH = 0Ω –4 Read 170µs Write 30µs with Write Data –6 –8 –10 –12 –14 –16 15 20 25 30 35 40 45 Bank write current [mA] 50 55 Deviation of bank write current is within ± 7% at basis of the chart. – 15 – 6.0 6.5 CXA3541N Input refered noise voltage vs. Ambient temperature Normalized write current vs. Ambient temperature 0.82 1.04 VCC = 5V VEE = –3V RMR = 50Ω IBn = "100" 0.80 1.02 IW/IW (Ta = 25°C) EN [nV/√Hz] 0.78 0.76 0.74 1.00 0.98 0.96 0.72 0.70 VCC = 5V VEE = –3V IWn = "0101" –25.0 0.0 25.0 50.0 0.94 75.0 –25.0 Ta – Ambient temperature [°C] 0.0 25.0 50.0 75.0 Ta – Ambient temperature [°C] Power supply ON/OFF detector threshold voltage vs. Ambient temperature Normalized write current vs. Power supply voltage 1.04 4.15 Power supply ON/OFF detector threshold voltage [V] 4.10 IW/IW (VCC = 5V) 1.02 1.00 0.98 0.96 3.5 VEE = –3V IWn = "0101" Ta = 25°C 4.0 4.5 5.0 5.5 6.0 4.05 ON → OFF OFF → ON 4.00 3.95 3.90 3.85 6.5 VCC [V] –25.0 0.0 25.0 50.0 Ta – Ambient temperature [°C] – 16 – 75.0 CXA3541N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 24 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 12 b 0.13 M 0.5 ± 0.2 (0.15) (0.22) 0.1 ± 0.1 DETAIL B : SOLDER b=0.22 ± 0.03 + 0.03 0.15 – 0.01 + 0.1 b=0.22 – 0.05 + 0.05 0.15 – 0.02 0.65 B DETAIL B : PALLADIUM 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 17 – Sony Corporation