CXA3572R Driver/Timing Generator for Color LCD Panels Description The CXA3572R is an IC designed to drive the color LCD panel ACX306/312. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals and a VCO onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. Features • Color LCD panel ACX306/312 driver • Supports NTSC and PAL systems • Supports Y/color difference and RGB inputs • Supports OSD input • Power saving function (clock stopped) • Various setting control using a serial interface circuit (asynchronous type) • Electronic attenuators (D/A converter) • VCO (no external oscillator circuit) • LPF (fc variable) • COMMON and PSIG output circuits • Sharpness function • 2-point γ correction circuit • R, G, B signal delay time adjustment circuit • Sync separation circuit • D/A output pin (0 to 3V, 8 level output) • Output polarity inversion circuit • Supports AC drive for LCD panel during no signal 48 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC1 5.5 V VCC2 15 V VDD 4.6 V • Analog input pin voltage VINA1 (Pins 18, 19, 20, 22, 23, 24 and 25) GND – 0.3 to VCC1 + 0.3 V VINA2 (Pin 16) GND – 0.3 to VCC2 + 0.3 V • Digital input pin voltage VIND (Pins 34 and 35) VSS – 0.3 to +5.5 V • Common input pin voltage VINAD (Pins 31, 32 and 33) GND, VSS – 0.3 to +5.5 V • Operating temperature Topr –15 to +75 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation (Ta ≤ 25°C) PD 600 mW Operating Conditions • Supply voltage VCC1 – GND1 2.7 to 3.6 VCC2 – GND2 11.0 to 14.0 VDD – VSS 2.7 to 3.6 Applications Compact LCD monitors, etc. V V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Y05A11-PS CXA3572R DA OUT 26 ATT DA OSD B NC SIG.C PSIG DC DET PSIG OUT VCC2 17 16 15 14 13 PSIGBRIGHT DL HUE COLOR MATRIX DL HUE COLOR 12 G OUT R, G, B RBRIGHT USERBRIGHT CONTRAST SUBBRIGHT GAMMA1 GAMMA2 PHASE COMPARATOR CLOCK GENERATOR BLIM COM XSTBY1 SH1 SH2 SH3 SH4 FRP XCLP BLK COM HD_ CSYNC VCO ADJ Coarse VCO ADJ Fine CK IR RP DAC R DC DET 8 B OUT 7 B DC DET 6 COM 5 GND2 4 TEST 3 VST 2 VCK 1 EN FRP Analog block 3V SERIAL I/F SCK 32 9 BLIM S/H GND1 30 SEN 31 10 R OUT SYNC SEL SYNC SEP RPD 29 11 G DC DET OSD BBRIGHT USERBRIGHT CONTRAST γ2 SUBCONT B SUBCONT R SUBCONTRAST +12V MODE γ1 LPF TRAP LPF SW LPF FILTER 28 REF TRAP REF 27 DA 18 PSIGBRIGHT ATT 19 PICTURE ATT SYNC IN 25 20 +3V 21 PICTURE f0 PSIG PowerSW PICTURE Gain OSD R 24 23 22 OSD G VCC1 G/Y R/R-Y B/B-Y Block Diagram Analog block 12V XSTBY2 SDAT 33 Digital block 3V SERIAL I/F H. FILTER VD 34 TIMING GENERATOR PLL COUNTER XCLR 35 –2– 46 47 0V 48 VSS +3V 45 DWN VSS 44 WIDE RGT 43 VDD VDO 42 HST 0V 41 HCK2 40 HCK1 39 HDO +3V 37 38 VDD POF 36 CXA3572R Pin Description Pin No. Symbol Description I/O 1 EN O EN pulse output 2 VCK O V clock pulse output 3 VST O V start pulse output 4 TEST — Test (Leave this pin open.) 5 GND2 — Analog 12.0V GND 6 COM O Common pad voltage output for LCD panel 7 B DC DET O B signal DC voltage feedback circuit capacitor connection 8 B OUT O B signal output 9 R DC DET O R signal DC voltage feedback circuit capacitor connection 10 R OUT O R signal output 11 G DC DET O G signal DC voltage feedback circuit capacitor connection 12 G OUT O G signal output 13 VCC2 — Analog 12.0V power supply 14 PSIG OUT O PSIG output 15 PSIG DC DET O PSIG signal DC voltage feedback circuit capacitor connection 16 SIG.C I R, G, B and PSIG output DC voltage adjustment 17 NC 18 OSD B I OSD B input 19 OSD R I OSD R input 20 OSD G I OSD G input 21 VCC1 — 22 G/Y I G/Y signal input 23 R/R-Y I R/R-Y signal input 24 B/B-Y I B/B-Y signal input 25 SYNC IN I Sync separation circuit input/sync signal input 26 DA OUT O DAC output 27 REF O Level shifter circuit REF voltage output for LCD panel 28 FILTER O Internal filter circuit f0 adjusting resistor connection 29 RPD O Phase comparator output 30 GND1 — Analog 3.0V GND 31 SEN I Serial load input 32 SCK I Serial clock input 33 SDAT I Serial data input 34 VD I Vertical sync signal input 35 XCLR I Power-on reset capacitor connection (timing output block) 36 POF O LCD panel power supply on/off (Leave this pin open when not using this function.) Input pin for open status — Analog 3.0V power supply –3– L CXA3572R Pin No. Symbol Description I/O 37 VDD — Digital 3.0V power supply 38 HDO O HDO pulse output 39 VDO O VDO pulse output 40 RGT O Right/left inversion switching signal output 41 VSS — Digital 3.0V GND 42 HCK1 O H clock pulse 1 output 43 HCK2 O H clock pulse 2 output 44 HST O H start pulse output 45 VDD — Digital 3.0V power supply 46 WIDE O WIDE pulse output 47 DWN O Up/down inversion switching signal output 48 VSS — Digital 3.0V GND –4– Input pin for open status CXA3572R Analog Block Pin Description Pin No. 5 Symbol GND2 Pin voltage Equivalent circuit Description — Analog 12.0V GND. Vcc2 125k 6 COM — 6 5k 100k COMMON voltage output. The output voltage is controlled by serial communication. GND2 Vcc2 7 9 11 15 B DC DET R DC DET G DC DET PSIG DC DET 7 3.0V 4K Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output signal DC level control. Connect a low-leakage capacitor. 5k 9 10k 11 15 GND2 Vcc2 8 10 12 14 B OUT R OUT G OUT PSIG OUT 8 — 10 500 10 12 14 10 5k 100k R, G, B and PSIG signal outputs. The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode. GND2 13 VCC2 12.0V Analog 12.0V power supply. Vcc2 200k 16 SIG.C VCC/2 16 200k 10p GND2 17 NC — R, G, B and PSIG output DC voltage setting. Connect a 0.01µF capacitor between this pin and GND1. When using a SIG.C of other than Vcc2/2, input the SIG.C voltage from an external source. No connection. –5– CXA3572R Pin No. Symbol Pin voltage Equivalent circuit OSD pulse inputs. When one of these input pins exceeds the Vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the Vth2 level, only the corresponding output goes to white limiter level. Connect these pins to GND when not used. Vcc1 18 19 20 21 OSD B OSD R OSD G VCC1 Vth1 = VCC1 × 1/3 Vth2 = VCC1 × 2/3 G/Y R/R-Y B/B-Y 20k 19 20 GND1 3.0V G/Y: 1.8V 22 23 24 18 R/R-Y, B/B-Y, RGB: 1.8V Y/color difference: 2.0V Description Analog 3.0V power supply. Vcc1 22 In Y/color difference input mode, input the Y signal to Pin 22, the R-Y signal to Pin 23 and the B-Y signal to Pin 24. In RGB input mode, input the G signal to Pin 22, the R signal to Pin 23 and the B signal to Pin 24. Pedestal clamp these pins with external coupling capacitors. 1k 23 24 GND1 Vcc1 10k 25 SYNC IN 0.9V Sync separation circuit input, or composite sync/horizontal sync signal input. During input to the sync separation circuit, input via a capacitor. 1k 25 GND1 Vcc1 80k 26 DA OUT — 26 DA output. Outputs the serial data converted to DC voltage. The current driving capacity is ±1.0mA (max.). 15p GND1 Vcc1 25k 27 REF VCC1/2 27 100k GND1 –6– REF output. The current driving capacity (sink) is 1.6mA (max.). CXA3572R Pin No. Symbol Pin voltage Equivalent circuit Description Connect a resistor between this pin and GND1 to control the internal LPF and trap frequencies. Connect a 43kΩ resistor (tolerance ±2%, temperature characteristics ±200ppm or less). This pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the GND side of the external resistor and the GND1 pin as close as possible. Vcc1 28 FILTER 1.2V 500 28 GND1 Vcc1 29 RPD 1.8V 1k 100k 29 Phase comparator output. GND1 30 GND1 — Analog 3.0V GND. Vcc1 31 ∗1 20k 32 31 32 33 SEN SCK SDAT — Serial clock, serial load and serial data inputs for serial communication. 33 GND1 Vss –7– CXA3572R Digital Block Pin Description Pin No. Symbol 1 2 3 36 38 39 40 42 43 44 46 47 EN VCK VST POF HDO VDO RGT HCK1 HCK2 HST WIDE DWN 35 31 32 33 XCLR SEN SCK SDAT Pin voltage Equivalent circuit Description 1 36 40 44 2 38 42 46 — Digital block outputs. 3 39 43 47 Vss 35 32 — Digital block system reset, and serial clock, serial load and serial data inputs for serial communication. 31 33 Vss 34 34 VD — Vertical sync signal input. Vss 37 45 VDD — Digital 3.0V power supply. 41 48 VSS — Digital 3.0V GND. 4 TEST — Test. Leave this pin open. –8– CXA3572R Setting Conditions for Measuring Electrical Characteristics Use the Electrical Characteristics Measurement Circuit on page 21 when measuring electrical characteristics. For measurement, the digital block must be initialized and power saving must be canceled by performing Settings 1, 2 and 3 below. In addition, the serial data must be set to the initial settings shown in the table below. Setting 1. System reset After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. The serial bus is set to the default values. VDD XCLR (Pin 35) TR TR > 10µs System reset Setting 2. Horizontal AFC adjustment In the condition without sync input, adjust so that the HDO pulse output frequency is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz. Setting 3. Canceling power saving mode The power-on default is power saving mode, so clear (set all “1”) serial data PS0 and SYNC GEN. –9– CXA3572R Serial data initial settings MSB ADDRESS LSB MSB A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA D6 D7 D5 D4 LSB D3 D2 D1 D0 USER-BRIGHT (10000000/LSB) 0 SUB-BRIGHT R (1000000/LSB) 0 SUB-BRIGHT B (1000000/LSB) CONTRAST (10000000/LSB) 0 SUB-CONTRAST R (1000000/LSB) 1 0 SUB-CONTRAST B (1000000/LSB) 1 0 0 γ-1 (0000000/LSB) 1 1 1 0 γ-2 (0000000/LSB) 1 0 0 0 PSIGSW (0) PSIG-BRIGHT (1000000/LSB) 0 1 0 0 1 0 COM-DC (1000000/LSB) 0 0 1 0 1 0 0 COLOR (1000000/LSB) 0 0 0 1 0 1 1 0 HUE (1000000/LSB) 0 0 0 0 1 1 0 0 VCO Fine (10000000/LSB) 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 LPFSW (0) 0 0 0 1 0 0 0 0 0 0 VCO Coarse (000/LSB) 0 1 0 0 0 0 0 0 0 0 TEST2 (1) 0 1 0 0 0 0 0 1 SLSYP SLEXVD SLDWN SLRGT (1) (0) (0) (1) 0 1 0 0 0 0 1 0 SYST (0) SLFL (0) SLFR SL4096 SLCLP1 SLCLP0 SLVDO SLHDO (0) (0) (0) (0) (0) (0) 0 1 0 0 0 0 1 1 0 SLMBK (0) H POSITION (100000/LSB) 0 1 0 0 0 1 0 0 S/H POSITION (000/LSB) 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 BLACK-LIMITER PICTURE-F0 (000/LSB) PICTURE-GAIN (00000/LSB) TRAP (0) LPF (000/LSB) SB POSITION (100/LSB) (100000/LSB) PONF (1) DA (000/LSB) INPUT SYNC MODE SEL (0) SEL (1) (0) TEST1 SLPOF SYNC (0) GEN (1) (0) TEST3 (0, 0) PS0 (1) SLWD SLNTPL (0) (0) HDO POSITION (00000/LSB) V POSITION (01000/LSB) TEST4 (00000000/LSB) Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”. – 10 – CXA3572R Electrical Characteristics — DC Characteristics Analog Block (Ta = 25°C, VCC1 = VDD = 3.0V, VCC2 = 12.0V, see page 10 for the DAC) Item Symbol Measurement conditions Min. Typ. Max. Current consumption 1 (Y/color difference input) I1 Measure the inflow current to Pin 21. 16 34 50 Current consumption 2 (Y/color difference input) I2 Measure the inflow current to Pin 13. 1.0 3.4 10 Current consumption 1 (RGB input) IRGB1 Measure the inflow current to Pin 21. 12 28 42 Current consumption 2 (RGB input) IRGB2 Measure the inflow current to Pin 13. 1.0 3.4 10 Current consumption 1 (PS0 = 0) IPS01 Measure the inflow current to Pin 21. — 7 11 Current consumption 2 (PS0 = 0) IPS02 Measure the inflow current to Pin 13. — 0.3 1.0 Current consumption 1 (SYNC GEN = 0) ISG1 Measure the inflow current to Pin 21. — 14 27 Current consumption 2 (SYNC GEN = 0) ISG2 Measure the inflow current to Pin 13. — 0.3 1.0 B DC DET pin voltage V7 3.0 R DC DET pin voltage V9 3.0 G DC DET pin voltage V11 3.0 PSIG DC DET pin voltage V15 3.0 SIG.C pin voltage V16 6.0 G/Y pin voltage V22 1.8 R/R-Y pin voltage 1 V23 During Y/color difference input 2.0 R/R-Y pin voltage 2 V23 During RGB input 1.8 B/B-Y pin voltage 1 V24 During Y/color difference input 2.0 B/B-Y pin voltage 2 V24 During RGB input 1.8 SYNC IN pin voltage V25 During no input 1.1 REF pin voltage (power saving mode) V27 0.2 FILTER pin voltage V28 1.2 OSD R, G, B input voltage SIG. C input voltage VSIG.C – 11 – Unit mA V GND VCC1 5.0 6.5 CXA3572R Item Symbol Measurement conditions Y∗1 Y/Color difference mode Y, R-Y, B-Y signal input level 1 SYNC (Y on SYNC)∗2 R-Y INPUT SEL = 0 (–6dB Attenuate OFF) Min. Typ. Max. 0.35 0.4 0.15 0.2 0.245 0.311 B-Y Y∗1 Y/Color difference mode Y, R-Y, B-Y signal input level 2 SYNC (Y on SYNC)∗2 R-Y 0.7 0.3 INPUT SEL = 1 (–6dB Attenuate ON) 0.490 0.622 B-Y RGB mode R, G, B signal input level 1 RGB mode R, G, B signal input level 2 R, G, B∗1 SYNC (G on SYNC)∗2 R, G, B∗1 SYNC (G on SYNC)∗2 Unit INPUT SEL = 0 (–6dB Attenuate OFF) INPUT SEL = 1 (–6dB Attenuate ON) ∗1 Y signal level (SYNC level is not included.) ∗2 SYNC level of Y (G) on SYNC signal. – 12 – 0.35 0.5 0.15 0.2 0.7 0.3 Vp-p CXA3572R Control Signal Block (Sync signal, serial-serial signal, XCLR, digital output) (Ta = –15 to +75°C, VCC1 = VDD = 2.7 to 3.6V) Item Symbol Measurement conditions Min. Typ. Max. High level input voltage VIH1 VCC1 – 0.7 VCC1 Low level input voltage VIL1 0 0.7 High level input voltage VIH2 2.0 VDD (VCC1) Low level input voltage VIL2 0 0.7 High level input current | IIH1 | VIN = VDD 20 Low level input current | IIL1 | VIN = 0V 20 High level input current | IIH2 | VIN = VDD Low level input current | IIL2 | VIN = 0V 1.0 High level input current | IIH3 | VIN = VDD 1.0 Low level input current | IIL3 | VIN = 0V 1.0 High level output voltage VOH1 IOH = –1.2mA Low level output voltage VOL1 IOL = 4.0mA High level output voltage VOH2 IOH = –0.6mA Low level output voltage VOL2 IOL = 2.0mA ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 20 150 Unit Applicable pins ∗1 V ∗2, ∗3, ∗4 ∗1, ∗2 µA ∗3 (pull-down) ∗4 2.6 ∗5 0.3 V 2.6 0.3 SYNC IN (Pin 25) SEN (Pin 31), SCK (Pin 32), SDAT (Pin 33) VD (Pin 34) XCLR (Pin 35) HCK1 (Pin 42), HCK2 (Pin 43), HST (Pin 44) EN (Pin 1), VCK (Pin 2), VST (Pin 3), POF (Pin 36), HDO (Pin 38), VDO (Pin 39), RGT (Pin 40), WIDE (Pin 46), DWN (Pin 47) – 13 – ∗6 CXA3572R Electrical Characteristics AC Characteristics Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions are required. Ta = 25°C, VCC1 = 3.0V, VCC2 = 12V, GND1 = GND2 = 0V, VSS = 0V, SW8/10/12/14 = OFF, no video input, SG1 input to TP25 Note: Serial data values in the table are HEX notation. Symbol Serial data setting (HEX) Maximum gain between input and output GMAX Minimum gain between input and output GMIN Item Inverted and non-inverted gain difference Gain difference between R, G and B Min. Typ. Input SG2 (0.2Vp-p) to TP22 and CONT FFh measure the output amplitude at MODE 00h TP12. 19 22 25 dB CONT 00h Input SG2 (0.2Vp-p) to TP22 and MODE 00h measure the output amplitude at TP12. –6 –3 0 dB ∆GINV CONT 2Fh Input SG2 (0.2Vp-p) to TP22 and measure the inverted output amplitude Vinv and the non-inverted output amplitude Vninv at TP12. ∆Ginv = 20 log (Vninv/Vinv) — — ±0.4 dB ∆GRGB Input SG2 (0.2Vp-p) to TP22 (TP23, TP24), measure the non-inverted MODE 00h output amplitude at TP8, TP10 and CONT 2Fh TP12, and obtain the maximum and minimum difference between these values. — — 0.6 dB –4 –2.0 –1.0 ∆GSC1 Sub-contrast variable amount ∆GSC2 Sub-bright variable amount ∆VSB1 ∆VSB2 Set CONT = 26h, input SG2 (0.2Vp-p) SUB-CONT to TP22, and assume the non-inverted 00h output amplitude at TP8 and TP10 when SUB-CONT R, B = 40h, 00h and 7Fh as V1, V2 and V3, respectively. SUB-CONT ∆Gsc1 = 20 log (V3/V1) 7Fh ∆Gsc2 = 20 log (V2/V1) Measure the R, G, B, PSIG and COM output voltages in power saving mode. VBL1 BLK-LIM 00h VBL2 BLK-LIM 3Fh Set U-BRT = 00h, measure the non-inverted black limit level at TP12 when BLK-LIM = 00h and 3Fh, and assume the difference from the output DC voltage as VBL1 and VBL2, respectively. – 14 – Max. Unit dB 1.0 SUB-BRT Set U-BRT = 1Ah and measure the –2.0 R, B 00h non-inverted level at TP8 and TP10 relative to the non-inverted black SUB-BRT level at TP12 when SUB-BRT R, B = 0.9 R, B 7Fh 7Fh and 00h. R, G, B, PSIG and COM output VPSO voltage in power saving mode Black limiter variable amount Measurement conditions 2.0 4.0 –1.4 –0.9 V 1.4 2.0 — — 100 — 2.5 3.0 mV V 4.5 5.0 — CXA3572R Item Serial data setting (HEX) Measurement conditions Min. Typ. VWL Set CONT = FFh, input SG2 (0.2Vp-p) to TP22, measure the non-inverted white limit level, and obtain the difference from the output DC voltage. 0.3 0.6 1.0 V Black level difference between ∆VB R, G and B Measure the non-inverted black level at TP8, TP10 and TP12, and obtain the maximum and minimum difference between these values. — — 300 mV RGB and PSIG output DC voltage Measure the output DC level (average voltage) at TP8, TP10, TP12 and TP14. 5.8 6.0 6.2 V Measure the output average voltage difference at TP8, TP10 and TP14 relative to the output average voltage at TP12. — — 300 mV 8.5 10.0 — 1.0 2.0 — 4.5 4.8 — 1.4 2.0 2.5 — — 300 1.5 3 — — –5 –2 White limiter variable amount Symbol Vc DC voltage difference between ∆Vc RGB and PSIG PSIG-BRT variable amount VPB1 VPB2 PSIG-BRT Assume the PSIG output amplitude 00h when PSIG-BRT = 00h and 7Fh as PSIG-BRT VPB1 and VPB2, respectively. 7Fh ∆UB1 U-BRT 00h ∆UB2 U-BRT FFh Level difference between PSIG-BLK ∆VBB and BLK-LIM SLWD 1 USER-BRT variable amount ∆HUR1 HUE 00h ∆HUR2 HUE 3Fh HUE variable amount R HUE variable amount B Picture variable amount ∆HUB1 HUE 00h ∆HUB2 HUE 3Fh GP1 PIC-G 00h GP2 PIC-G 1Fh GC1 COLOR 00h Color variable amount GC2 COLOR 50h Measure the non-inverted black level at TP12 when U-BRT = 00h and FFh and assume the difference from the average voltage as ∆UB1 and ∆UB2, respectively. Set BLK-LIM = 00h and measure the difference between the inverted and non-inverted black level at TP12 and TP14. Set U-BRT = 80h, CONT = 80h, COLOR = 40h, input SG4 (56mVp-p) to TP23, input SG4 (100mVp-p) to TP24, and assume the amplitude at TP8 when HUE = 80h, 00h and 3Fh as VB1, VB2 and VB3. Similarly, assume the amplitude at TP10 as VR1, VR2 and VR3. ∆HUR1 = 20 log (VR2/VR1) ∆HUR2 = 20 log (VR2/VR1) ∆HUB1 = 20 log (VB2/VB1) ∆HUB2 = 20 log (VB2/VB1) Set CONT = 80h, input SG3 to TP22, and measure the TP12 amplitude at f0 relative to the TP12 amplitude at 100kHz when PIC-G = 00h and 1Fh, respectively. Input SG4 (160mVp-p) to TP23 and TP24, and assume the output amplitude at TP8 and TP10 when COLOR = 00h, 40h and 50h as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) GC2 = 20 log (V3/V2) – 15 – Max. Unit Vp-p V mV dB — –5 –2 1.5 3 — –2.5 0 2.5 9 12 — — — –20 dB dB 0.5 — — CXA3572R Item Symbol Serial data setting (HEX) Min. Typ. Max. Unit 0.85 1.00 1.15 0.41 0.51 0.61 0.15 0.19 0.23 — 1.5 — — 5.2 — Trap characteristics fo Set U-BRT = 30h, CONT = DFh, input SG7 (13.5MHz) to TP22, TP23 MODE 00h and TP24, and measure the amount TRAP 1 by which each output is attenuated relative to SG7 (100kHz). — –27 –18 dB Frequency response fRGB Set SW8, SW10 and SW12 = ON, input SG3 to TP22, TP23 and TP24, MODE 00h and measure the frequency which results in –3dB relative to the TP8, TP10 and TP12 amplitude at 100kHz. 5.5 — — MHz REF output voltage VREF Measure the REF pin output voltage at the output current 1.5mA sink. 1.3 1.5 1.7 V — — 0.3 B-Y/ R-Y Matrix amplitude ratio G-Y/ R-Y G-Y/ B-Y fc1 LPF characteristics fc2 DA adjustment range VDA1 VDA2 ∆γ 1 γ gain ∆γ 2 Vγ 1MN γ 1 adjustment variable range Vγ 1MX Measurement conditions Assume the TP10 output when SG4 (0.1Vp-p) is input to TP23 as RR, the TP8 amplitude when SG4 (0.1Vp-p) is input to TP24 as BB, the TP10 amplitude when SG5 CONT 80h (0.1Vp-p) is input to TP23 as RG, COLOR 40h and the TP8 amplitude when SG5 (0.1Vp-p) is input to TP24 as BG. B-Y/R-Y = RR/BB G-Y/R-Y = RG/RR G-Y/B-Y = BG/BB LPF 01h Input SG3 to TP22 and measure the MODE 00h frequency which results in –3dB LPF 07h relative to the TP12 amplitude at MODE 00h 100kHz when LPF = 01h and 07h. DA 00h DA 07h Output current Measure the DA 1.0mA output voltage when DA = 00h and 07h. Output current –1.0mA Input SG2 (0.35mVp-p) to TP22 and measure the amplitude at TP8, TP10 and TP12. Assume the output amplitude when CONT 41h GAMMA1 = 7Fh as V1, when GAMMA1 = 3Fh as V2, and when GAMMA1 = GAMMA2 = 3Fh as V3. ∆γ 1 = 20 log (V1/V2) ∆γ 2 = 20 log (V3/V2) Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when CONT 41h γ 1 = 00h and γ 1 = 7Fh from the IRE level of the input signal. γ 1 = 00h: Vγ 1MN γ 1 = 7Fh: Vγ 1MX – 16 – MHz V 2.6 — — 12 14 16 dB 12 14 16 — — 0 IRE 100 — — CXA3572R Item Symbol Vγ 2MN γ 2 adjustment variable range Vγ 2MX COMMON control range Vth1 OSD OSD threshold value Vth2 OSD COM-DC 7Fh Measure the COM output DC voltage when COM-DC = 00h and 7Fh, and measure the difference from the COM output DC voltage when COM-DC = 40h. Input SG4 to TP18, TP19 and TP20, gradually raise the high level from 0V, and assume the high level voltage at which the output level goes to BLK-LIM level as Vth1OSD, and the high level voltage at which the output goes to WHITE-LIM level as Vth2OSD. Min. Typ. 100 — Max. Unit — IRE — — 50 –1.3 –1.0 –0.8 V 0.8 1.0 1.3 0.8 1.0 1.2 V 1.8 2.0 2.2 — — ts0 SEN setup time, activated by the rising edge of SCK. (See Fig. 3.) 150 ts1 SDAT setup time, activated by the rising edge of SCK. (See Fig. 3.) 150 — — th0 SEN hold time, activated by the rising edge of SCK. (See Fig. 3.) 150 — — th1 SDAT hold time, activated by the rising edge of SCK. (See Fig. 3.) 150 — — tw1L SCK pulse width. (See Fig. 3.) 210 — — ns tw1H SCK pulse width. (See Fig. 3.) 210 — — ns tw2 SEN pulse width. (See Fig. 3.) 1 — — µs — — 30 Data setup time Data hold time tTHL tTLH Output transition time Measurement conditions Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when CONT 41h γ 2 = 00h and γ 2 = 7Fh from the IRE level of the input signal. γ 2 = 00h: Vγ 2MN γ 2 = 7Fh: Vγ 2MX COMMIN COM-DC 00h COMMX Minimum pulse width Serial data setting (HEX) tTHL tTLH Measure the transition time of each output. 90pF load: HST output pin 120pF load: HCK1 and HCK2 output pins (See Fig. 1.) Measure the transition time of each output. 50pF load: DWN, WIDE, VCK, VST, TEST, EN, VDO, HDO, POF and RGT output pins (See Fig. 1.) ns ns ns — — 30 — — 40 ns — — 40 Cross-point time difference ∆T Measure HCK1/HCK2. 120pF load (See Fig. 2.) — — — ns HCK duty DTYHC Measure the HCK1/HCK2 duty. 120pF load 48 50 52 % – 17 – CXA3572R Electrical Characteristic Measurement Method Diagrams ∆T 90% 50% 10% tTLH ∆T tTHL Fig. 1. Output transition time measurement conditions SDAT D15 D14 D13 D12 D11 D10 ts1 D9 D8 Fig. 2. Cross-point time difference measurement conditions D7 D6 D5 D4 D3 D2 D1 D0 D15 th1 50% SCK tw1H tw1L 50% SEN ts0 th0 Fig. 3. Serial transfer block measurement conditions – 18 – tw2 CXA3572R SG No. Waveform Horizontal sync signal (CSYNC) SG1 4.7µs 3.0Vp-p 1H Amplitude variable SG2 1H Horizontal sync signal Sine wave video signal; frequency and amplitude variable 0.1Vp-p SG3 0.1Vp-p 1H 25µs High level variable 10µs 0V SG4 Horizontal sync signal 3V 10µs SG5 Low level variable 25µs Horizontal sync signal – 19 – CXA3572R SG No. Waveform Horizontal sync signal (CSYNC) 50mVp-p 4.7µs SG6 1H Sine wave video signal 0.1Vp-p SG7 1H SG8 Horizontal sync signal (CSYNC) 4.7ns 0.15Vp-p 1H – 20 – CXA3572R Electrical Characteristics Measurement Circuit TP29 6800p 10k 3.3µ +3V TP33 TP32 TP31 TP36 35 34 33 32 31 30 29 28 27 VD SDAT SCK SEN GND1 RPD FILTER REF 26 DA OUT 36 37 VDD TP38 1µ XCLR 47µ ∗ 43k 0.1µ POF 0.01µ 100k TP27 TP26 TP25 38 HDO 25 SYNC IN A 0.01µ TP24 24 B/B-Y R/R-Y 23 0.01µ TP23 +3V 0.01µ TP22 TP39 39 VDO G/Y 22 TP40 40 RGT Vcc1 21 41 Vss1 OSD G 20 0.01µ TP20 TP42 42 HCK1 OSD R 19 TP19 TP43 43 HCK2 OSD B 18 TP18 TP44 44 HST TP16 SIG.C 16 0.1µ 46 WIDE 8 9 10 PSIG OUT 14 G OUT G DC DET R OUT R DC DET B OUT B DC DET 7 6 11 10 10 0.1µ 5 COM GND2 TEST 4 0.1µ 3 0.1µ 2 VST VCK 48 Vss2 1 0.01µ PSIG DC DET 15 47 DWN EN 10 Buffer SW14 13 +12V 12 10 A 350p 350p SW8 SW10 SW12 TP6 TP8 TP10 TP12 ∗ Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less Locate this resistor as close to the IC pin as possible to reduce the effects of external signals. – 21 – TP14 60n VCC2 0.01µ TP1 TP2 TP3 350p TP47 47µ NC 17 45 VDD TP46 A 47µ CXA3572R Description of Operation 1) RGB and Y/color difference signal processing block Signal processing is comprised of picture, HUE, matrix, LPF/trap, contrast, OSD, sample-and-hold, γ correction, bright, sub-bright, sub-contrast and output circuits. • Input signal mode switching The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings. (During internal sync separation signal input) During RGB input: The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the R signal to Pin 23. During Y/color difference input: The Y signal is input to Pins 22 and 25, the B-Y signal to Pin 24, and the R-Y signal to Pin 23. (During external sync signal input) During RGB input: The G signal is input to Pin 22, the B signal to Pin 24, the R signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. During Y/color difference input: The Y signal is input to Pin 22, the B-Y signal to Pin 24, the R-Y signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. • NTSC/PAL switching The input system (NTSC/PAL) can be switched by the serial communication settings. • Picture circuit This performs aperture correction for the Y signal. The center frequency to be corrected and the correction amount are controlled by serial communication. • HUE circuit This is the hue adjustment circuit for the color difference signal. It is controlled by serial communication. • Matrix circuit This circuit converts Y, R-Y and B-Y signals into RGB signals. • LPF circuit This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when not using the LPF, it can be turned off by serial communication. • Trap circuit This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC. In addition, when not using the trap, it can be turned off by serial communication. • Contrast adjustment circuit This adjusts the amplitude to set the input RGB signal to the appropriate output level. • OSD This inputs the OSD pulses. There are two input threshold values: Vth1 (Vcc1 × 1/3) and Vth2 (Vcc1 × 2/3). When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITER. When an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER. – 22 – CXA3572R • Sample-and-hold circuit This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous sampling systems of LCD panels. HCK1 R S/H1 S/H4 R A G S/H2 S/H4 G A' B S/H3 S/H4 B B SH1 SH2 SH3 SH4 B' RGT = H (Normal) SH1 SH2 C SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 B A' A C' C B' Through Through Through Through Through Through SH3 A C' C B' B A' SH4 C B' B A' A C' RGT = L (right/left inversion) SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 SH1 B A' A C' C B' SH2 A C' C B' B A' SH3 SH4 C' SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1, 2, 3, 4, 5, 6: Serial data settings Through Through Through Through Through Through C B' B A' A C' The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and other timing is also generated by the digital block. The sample-and-hold timing changes according to the phase relationship with the HCK pulse, so the timing should be set to the SHS1 to SHS6 position in accordance with the actual board. • γ correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ 1 gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ 1, and the γ 2 gain transition point B voltage changes as shown in Fig. 3 by adjusting γ 2. Output Output Output B' A' A B A B Input Fig. 1 A B B' Input Fig. 2 – 23 – Input Fig. 3 CXA3572R • Bright circuit This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not interlinked with the γ transition points. • White balance adjustment circuit This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white amplitude is adjusted by SUB-CONTRAST. • Output circuit RGB output (Pins 8, 10, and 12) signals are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (SIG.C) of the output signal matches the reference voltage (Vcc2 + GND2)/2 (or the voltage input to SIG.C (Pin 16)). In addition, the white level output is clipped at the limiter operation point that is set by the serial communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set by the serial communication BLACK-LIMITER. The output PSIG signal level is normally adjusted by PSIG-BRIGHT, but during black frame display the level is specified by the BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously goes to BLACK-LIMITER level output. RGB IN 1H inverted signal (internal) Black frame display signal (internal) BLACK-LIMITER Set by BLACK-LIMITER SIG.C PSIG OUT Set by PSIG-BRIGHT BLACK-LIMITER BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER RGB OUT BLACK-LIMITER Set by BLACK-LIMITER – 24 – CXA3572R 2) Common voltage generation circuit block The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage is offset by serial communication using the SIG.C voltage as the reference and then output. 3) DA OUT output circuit The DA OUT output circuit outputs DC 3.0V at equal divisions. 4) REF output circuit The REF output circuit generates and supplies the panel level shifter circuit reference voltage to the LCD panel. 5) Sync system • Internal sync separation circuit Sync separation is performed from the signal input from SYNC IN (Pin 25). An external sync signal can also be input from the same pin (SYNC IN) according to the serial communication setting. Serial communication setting SYNC SEL = 0: Internal sync separation. SYNC SEL = 1: External sync signal input. (The internal sync separation circuit is set to power saving mode.) Input pin (Pin 25) processing During internal sync separation: Input through an external capacitor (0.1µF) During external sync signal input: Directly coupled, input level 3Vp-p positive or negative polarity • PLL and AFC circuits (VCO setting method) A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division counter and a VCO circuit and external LPF circuit. The PLL error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the RPD output. RPD output is converted to DC error voltage with the lag-lead filter, and then it controls the internal VCO circuit to stabilize the oscillation frequency. The internal clock oscillation frequency is set as follows by adjusting VCO-Coarse/Fine. Adjust the VCO-Coarse/Fine settings so that the HDO pulse output frequency in the condition without sync input is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz. Min: 25MHz Max: 30MHz 5MHz Clock oscillation frequency VCO-Coarse setting (7 steps) VCO-Coarse: f0 coarse setting (7 steps) from 5 to 25MHz VCO-Fine: Variable by approximately 4MHz using the f0 coarse setting made by VCO-Coarse as the reference VCO-Fine setting range (255 steps) 6) Power saving circuit (PS circuit) A power saving system can be realized together with the LCD panel by independently controlling (serial communication) the operation of each output block. This system is also effective for improving picture quality during power-on/off. The serial data PS0 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the “Description of Serial Control Operation” and “Power supply and power saving sequence” items. – 25 – CXA3572R 7) Power supply and power saving sequence Power-on for the CXA3572R and the LCD panel should be performed in the following order. Power-on Power-off D1 D2 LCD VDD (LCD panel 12V) VCC2 (analog 12V block) B1 C1 C2 B2 VCC1 (analog 3V block) A2 A1 VDD (digital 3V block) Power saving set ∗1 Power saving canceled E1 Power saving setting (serial control) E2 Power saving PS0 = 0, SLSG = 0 Normal operation PS0 → 1, SLSG → 1 12 fields Power saving PS0 → 0, SLSG → 0 Normal video display Display setting period (no video display) 4 fields Picture cancel period (no video display) DA OUT (Pin 26) operation When power saving is set to on or off, video display is automatically turned on or off at the above timings. Power-on Power-off min. max. A1 0 — B1 0 — C1 0 — D1 100∗2 — E1 0 100 ms ∗1 After the digital 3V VDD has completely risen and XCLR (Pin 35) is completely high level. ∗2 After the 3V VDD/VCC1 has completely risen. min. max. A2 0 — B2 0 — C2 — D2 0 ∗3 E2 150 300 ms — ∗3 After the panel 12V VDD has completely fallen. • POF (Pin 36) is output as the panel VDD control signal. The POF output can be switched by the serial communication setting, and the POF setting can be made regardless of the power saving setting. SLPOF 0 1 3V power supply POF (Pin 36) output Low level Power supply VCC2 VDD VCC1 High Level (VDD) POF VDD CXA3572R ACX306 Panel power supply configuration using POF output – 26 – CXA3572R 8) TG block • H-Position This adjusts the horizontal display position. Set this function so that the picture center matches the center of the LCD panel. • V-Position This adjusts the vertical display position. Set this function so that the picture center matches the center of the LCD panel. • Right/left (RGT) and/or up/down (DWN) inversion The video display direction can be switched. The horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance with the LCD panel mounting position. • Overscan display mode (SLWD) Displaying black in the up/down 6 lines and right/left 18 (19) dots of the display area generates an overscan area (black frame) in the display area. Fine adjustment of the black frame display position is performed by SB-Position. 453 dots 490 dots Black display 6 lines 240 lines Display area Display area 228 lines 6 lines Black frame display Normal display • AC driving of LCD panels during no signal The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the SYNC IN (Pin 25) and VD (Pin 34) pins. – 27 – CXA3572R Description of Serial Control Operation 1) System reset After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. (See Fig. ) The serial bus is set to the default values. VDD XCLR (Pin 35) TR TR > 10µs System reset 2) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading operation starts from the falling edge of SEN and is completed at the next rising edge. Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the SEN signal is input. In addition, if 16 bits or more of SCK are not input while SEN is low, the transferred data is not loaded to the inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data. SDAT A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCK SEN A: ADDRESS Serial transfer timing – 28 – D: DATA CXA3572R 2) Serial data map The serial data map is as follows. Values inside parentheses are the default values. MSB ADDRESS LSB MSB A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA D6 D7 D5 D4 LSB D3 D2 D1 D0 USER-BRIGHT (10000000/LSB) (0) SUB-BRIGHT R (1000000/LSB) (0) SUB-BRIGHT B (1000000/LSB) CONTRAST (10000000/LSB) (0) SUB-CONTRAST R (1000000/LSB) 1 (0) SUB-CONTRAST B (1000000/LSB) 1 0 (0) γ-1 (0000000/LSB) 1 1 1 (0) γ-2 (0000000/LSB) 1 0 0 0 PSIGSW (0) PSIG-BRIGHT (1000000/LSB) 0 1 0 0 1 (0) COM-DC (1000000/LSB) 0 0 1 0 1 0 (0) COLOR (1000000/LSB) 0 0 0 1 0 1 1 (0) HUE (1000000/LSB) 0 0 0 0 1 1 0 0 VCO Fine (10000000/LSB) 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 LPFSW (0) 0 0 0 1 0 0 0 0 (0) (0) VCO Coarse (000/LSB) 0 1 0 0 0 0 0 0 (0) (0) TEST2 (1) 0 1 0 0 0 0 0 1 SLSYP SLEXVD SLDWN SLRGT (0) (0) (0) (0) 0 1 0 0 0 0 1 0 SYST (0) SLFL (0) SLFR SL4096 SLCLP1 SLCLP0 SLVDO SLHDO (0) (0) (0) (0) (0) (0) 0 1 0 0 0 0 1 1 (0) SLMBK (0) H POSITION (100000/LSB) 0 1 0 0 0 1 0 0 S/H POSITION (000/LSB) 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 (0) (0) BLACK-LIMITER PICTURE-F0 (000/LSB) PICTURE-GAIN (00000/LSB) TRAP (0) LPF (000/LSB) SB POSITION (100/LSB) (100000/LSB) PONF (0) DA (000/LSB) INPUT SYNC MODE SEL (0) SEL (0) (0) TEST1 SLPOF SYNC (0) GEN (0) (0) TEST3 (00) PS0 (0) SLWD SLNTPL (0) (0) HDO POSITION (00000/LSB) V POSITION (01000/LSB) TEST4 (00000000/LSB) Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”. – 29 – CXA3572R 3) Description of control data • USER-BRIGHT This adjusts the brightness of the RGB output signals. Adjustment from LSB → MSB decreases the amplitude (black – black). • SUB-BRIGHT R/B This adjusts the brightness of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB decreases the amplitude (black – black). • CONTRAST This adjusts the contrast of the RGB output signals. Adjustment from LSB → MSB increases the amplitude (black – white). • SUB-CONTRAST R/B This adjusts the contrast of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB increases the amplitude (black – white). • γ-1 This sets the black side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point. When not adjusting γ-1, set γ-1: 0000000 (LSB). Set the γ-1 point to the black side (lower side) of the γ-2 point. • γ-2 This sets the white side γ point level of the RGB output signals. Adjustment from LSB → MSB lowers the γ point. When not adjusting γ-2, set γ-2: 0000000 (LSB). Set the γ-2 point to the white side (upper side) of the γ-1 point. • PSIG-BRIGHT This adjusts the brightness of the PSIG output signal. Adjustment from LSB → MSB decreases the amplitude (peak to peak). • PSIG-SW This switches the PSIG circuit on and off. D7 Mode 0 PSIG OFF 1 PSIG ON • COM-DC This adjusts the COMMON output voltage. Adjustment from LSB → MSB increases the output voltage. • COLOR This adjusts the color gain during Y/color difference input. Adjustment from LSB → MSB increases the gain. • HUE This adjusts the phase during Y/color difference input. Adjustment from LSB → MSB advances the phase. – 30 – CXA3572R • VCO-Fine This finely adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the frequency. Perform this adjustment after adjusting VCO-Coarse. • VCO-Coarse This roughly adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the frequency. Adjust with VCO-Fine set to 10000000 (LSB). • BLACK-LIMITER This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB → MSB lowers the limiter level. • PICTURE-GAIN This adjusts the picture gain during Y/color difference input. Adjustment from LSB → MSB raises the gain. When not using the picture function, set PICTURE-GAIN: 00000 (LSB). • PICTURE-F0 This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the output level. D2 D1 D0 Center frequency (f0) typ. 0 0 0 1.0MHz 0 0 1 1.3MHz 0 1 0 1.6MHz 0 1 1 1.9MHz 1 0 0 2.2MHz 1 0 1 2.5MHz 1 1 0 2.8MHz 1 1 1 3.1MHz • LPF This switches the frequency response of the low-pass filter. Set the fc/–3dB frequency relative to the amplitude 100kHz reference. See the AC Characteristics for the output level. D6 D5 D4 fc (RGB input/no load/typ.) 0 0 0 — 0 0 1 1.5MHz 0 1 0 2.1MHz 0 1 1 2.7MHz 1 0 0 3.5MHz 1 0 1 4.1MHz 1 1 0 4.6MHz 1 1 1 5.2MHz – 31 – CXA3572R • LPF-SW This switches the LPF circuit on and off. D7 Mode 0 LPF off 1 LPF on • TRAP This switches the trap circuit on and off. D3 Mode 0 TRAP off 1 TRAP on • DA This adjusts the DA output voltage. Adjustment from LSB → MSB raises the output voltage level. • INPUT-SEL Set this according to the input signal level. D2 Input signal level Mode 0 Normal input 0.35Vp-p or less, 0.5Vp-p or less with sync 1 Internally attenuated by –6dB 0.35Vp-p or more, 0.5Vp-p or more with sync • SYNC SEL This switches between internal sync separation and external sync signal input. D1 Mode Input connection method 0 Internal sync separation Input via a coupling capacitor 1 External sync signal input (internal sync separation circuit power saving) Input level 3Vp-p positive or negative polarity • MODE This switches the input signal. D0 Input signal 0 RGB input 1 Y/color difference input • PS0 (Default: 0) This performs the power saving setting. Be sure to use this setting as described in “Power supply and power saving sequence”. The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. The LCD panel power supply must be turned off in power saving mode. PS0 Mode 0 Power saving 1 Normal operation – 32 – CXA3572R • SYNC GEN (Default: 0) This sets the sync generator mode. In sync generator mode, only the HDO and VDO pulses are output normally, and all other pulses are low. The LCD panel power supply must be turned off in sync generator mode. Normally set to “1”. SYNC GEN Mode 0 Sync generator mode 1 Normal operation • SLPOF (Default: 0) This sets the POF (Pin 36) output. The POF output setting can be made regardless of the power saving mode. SLPOF Mode 0 POF = Low output 1 POF = High output • TEST1 (Default: 0) This is the test mode. Set to “0”. TEST0 Mode 0 Normal operation 1 Test mode • PONF (Default: 0) This switches the time until the picture is displayed after power saving is canceled. PONF Mode 0 12 fields 1 4 fields • TEST2 (Default: 0) This is the test mode. Set to “1”. TEST2 Mode 0 Test mode 1 Normal operation • SLNTPL (Default: 0) This switches between NTSC and PAL mode. SLNTPL Mode 0 NTSC 1 PAL – 33 – CXA3572R • SLWD (Default: 0) This sets the up/down and/or right/left black frame display. SLWD Display 0 100% viewing field display 1 Black frame display (95% display) • TEST3 (Default: 0, 0) This is the test mode. Set to “0, 0”. TEST3 Mode 0, 0 Normal operation 0, 1 1, 0 1, 1 Test mode • SLRGT (Default: 0) This switches between normal and right/left inverted display. SLRGT Setting 0 Normal display (right scan) 1 Right/left inverted display (left scan) • SLDWN (Default: 0) This switches between normal and up/down inverted display. SLDWN Setting 0 Normal display (down scan) 1 Up/down inverted display (up scan) • SLEXVD (Default: 0) This sets the external VD input. The external VD signal is input via VD (Pin 34). When using internal vertical sync separation, vertical sync separation is performed using the CSYNC input from SYNC IN (Pin 25). SLEXVD Setting 0 Internal vertical sync separation 1 External VSYNC input • SLSYP (Default: 0) This switches the input sync signal polarity. When performing sync separation with the internal sync separation circuit from YonSYNC or GonSYNC, set this to “0”. SLSYP HD/CSYNC, VSYNC polarity 0 Positive polarity 1 Negative polarity – 34 – CXA3572R • SLHDO (Default: 0) This switches the HDO pulse output polarity. SLHDO HDO polarity 0 Positive polarity 1 Negative polarity • SLVDO (Default: 0) This switches the VDO pulse output polarity. SLVDO VDO polarity 0 Positive polarity 1 Negative polarity • SLCLP0, SLCLP1 (Default: 0, 0) These switch the clamp position. SLCLP1 SLCLP0 0 0 A: Back porch position (during internal sync separation) 0 1 B: Sync position (during internal sync separation) 1 0 C: Back porch position (during external sync signal input) 1 1 D: Sync position (during external sync signal input) Position HSYNC 00: A 2.0µs 1.3µs 01: B 2.9µs 2.0µs XCLP 10: C 2.0µs 1.0µs 11: D 3.6µs 2.0µs • SL4096 (Default: 0) This function inverts the R, G, B and PSIG output signal polarities every 4096 fields. This further inverts the output polarities that are inverted every 1H for 4096 fields. SL4096 Polarity inversion cycle 0 1H inversion 1 1H inversion + 4096-field inversion • SLFR (Default: 0) This function inverts the R, G, B and PSIG output signal polarities every field. Normally set to 1H inversion. SLFR Polarity inversion cycle 0 1H inversion 1 1-field inversion – 35 – CXA3572R • SLFL (Default: 0) This function is used to stop R, G, B and PSIG output signal polarity inversion. SLFL Polarity inversion cycle 0 Polarity inversion 1 Polarity inversion stopped • SYST (Default: 0) This invalidates the input horizontal sync (CSYNC, HD) and forcibly sets the free-running status. SYST Mode 0 Normal operation 1 Forced free-running • H POSITION (Default: 100000/LSB) These set the horizontal display position. The HST pulse position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 1fH increments. HSYNC HP: 100000 (LSB) Default HP: 000000 (LSB) HST HP: 111111 (LSB) 30 steps (fH) 31 steps (fH) • SLMBK (Default: 0) This sets the decimation cycle in PAL mode. SLMBK Decimation cycle 0 1/6, 1/6 decimation 1 1/6, 1/8 decimation • HDO POSITION (Default: 00000/LSB) These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. HSYNC HP: 00000 (LSB) Default HDO HP: 11111 (LSB) 31 steps (124fH) – 36 – CXA3572R • V POSITION (Default: 01000/LSB) These set the vertical display position. The VST pulse position is adjusted using the input vertical sync signal as the reference. Adjustment is possible in 1 bit = 1H (1 line) increments. Vertical sync signal VP: 01000 (LSB) Default VP: 00000 (LSB) VST VP: 11111 (LSB) 8 steps (8H) 23 steps (23H) • S/H POSITION (Default: 000/LSB) These set the sample-and-hold pulse output phase. D7 D6 D5 Sample-and-hold position 0 0 0 SHS1 0 0 1 SHS2 0 1 0 SHS3 0 1 1 SHS4 1 0 0 SHS5 1 0 1 SHS6 1 1 0 Through (sample-and-hold off) 1 1 1 Through (sample-and-hold off) • SB POSITION (Default: 100/LSB) In overscan display mode, fine adjustment of the right/left overscan area (black frame) position is possible in 1 bit = 1fH increments. HST SBP: 000 (LSB) SBP: 100 (LSB) (BLK) SBP: 111 (LSB) 4 steps 3 steps (3fH) (4fH) 4 steps 3 steps (4fH) (3fH) • TEST4 (Default: 00000000/LSB) This is the test mode. Set to 00000000/LSB (8 bits). – 37 – CXA3572R To LCD Panel 3.3µ 0.01µ 43k 36 35 34 33 32 31 30 29 28 27 26 POF XCLR VD SDAT SCK SEN GND1 RPD FILTER REF DA OUT 37 VDD 25 SYNC IN 10k 6800p Serial Data Input External VD Input 0.1µ ∗1 0.1µ 100k External HD Input (0 to 3V) Application Circuit 38 HDO 0.1µ 0.1µ 0.1µ Vcc1 21 41 Vss1 +3V (Analog) 0.1µ OSD G 20 42 HCK1 OSD R 19 43 HCK2 33µ OSD B 18 44 HST NC 17 45 VDD 0.01µ ∗ 2 SIG.C 16 0.68µ 46 WIDE PSIG DC DET 15 Buffer TEST GND2 COM B DC DET B OUT R DC DET R OUT G DC DET 3 4 5 6 7 8 9 10 11 0.68µ +3V (Digital) To LCD Panel 10 10 G OUT VST 2 PSIG 14 OUT VCC2 10 10 To LCD Panel 13 0.1µ 12 33µ 0.68µ VCK 1 48 Vss2 0.68µ EN 47 DWN 33µ G/Y G/Y 22 40 RGT 0.1µ R/R-Y R/R-Y 23 39 VDO To LCD Panel B/B-Y B/B-Y 24 +12V (Analog) +12V (Analog) 10 22k 33µ 10 10 IN OUT To LCD Panel 22k PSIG Buffer Circuit ∗1 ∗2 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less When using a signal center voltage other than Vcc2/2, input an external signal center voltage. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 38 – CXA3572R Notes on Operation (1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. • The digital and analog IC power supplies should be separated, but the GND and VSS should not be separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible. The power supplies should also use a plain pattern. • Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect these capacitors as close to the pins as possible. • The resistor connected to Pin 28 should be connected as close to the pin as possible, and the wiring from the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the connected resistor. (2) The G/Y (Pin 22), R/R-Y (Pin 23), B/B-Y (Pin 24) and SYNC IN (Pin 25) pin input signals are clamped at the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (Input at an impedance of 1kΩ (max.) or less.) (3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the RGB output pins should have a leak current with a small absolute value and variance. Also, when using the pulse elimination (PAL display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor. (4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel specifications should be made before deciding the capacitance value. (5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use. (6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up. (7) Be sure to observe the power supply and power saving sequence specifications specified for this IC. (8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins. (9) Do not use this IC under operating conditions other than those given. (10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. (11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. (12) Always connect the VSS, GND1 and GND2 pins to the lowest potential applied to this IC; do not leave these pins open. The voltages applied to the power supply pins should be as follows. VSS = GND1 = GND2 ≤ VDD = VCC1 ≤ VCC2. (13) Be sure to connect the damping resistor of 10Ω to ROUT, GOUT, BOUT, PSIGOUT and COM output. – 39 – CXA3572R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 S 25 13 48 B (0.22) 0.5 ± 0.2 A (8.0) 24 37 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 S 0.5 ± 0.2 0.18 ± 0.03 0˚ to 10˚ 0.127 ± 0.04 0.1 ± 0.1 DETAIL B: PALLADIUM DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE P-LQFP48-7x7-0.5 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 40 – Sony Corporation