CXA7002R I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control Description The Sony CXA7002R is an Audio/Video switch designed primarily for application in Digital Set Top Boxes. It provides video and audio routing from the digital encoder source to the TV and VCR scart (peri-television) connectors. In addition, the TV audio output has a programmable volume control. The chip is programmed by means of an I2C interface and can operate from a single or dual power supply. Target specifications: Canal+, BSkyB, TPS, NorDig, and ECCA Euro-Box Features Supply • Single: 0V, +5V, +12V • Dual: 0V, –5V, +5V and +12V (Low number of external parts required) Video • 2 scart switching (VCR, TV) • VCR input supports RGB mode • Integrated 75Ω drivers for direct video connection • Y/C mixer with trap for RF modulators • Switchable clamps on inputs • Low pass filters on six inputs • Controllable gain on encoder inputs • Adjustable gain on RGB outputs • Video output shutdown for low power modes • Fast blanking switch • Slow blanking switch for TV and VCR output • SVHS switch on VCR output • Y/C auxiliary input 64 pin LQFP (Plastic) I2C and Logic • Fast mode compatible I2C bus • Function monitor with loop through • Interrupt output for function monitor and sync detect • Logic output pin • Sync detector for Y/CVBS inputs Applications • Digital Set Top Box • Integrated digital television Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) unless stated 14 V • Supply voltage VCC • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.1 W (when mounted on the board) Audio • Four stereo audio inputs • Volume control (–56dB to +6dB in 2dB steps) • Additional +6dB gain on audio DAC inputs • Audio overlay facility • Volume bypass for TV and Phono outputs • Mono switching on TV, VCR outputs • Switchable audio limiter function • Switchable Mono output for RF modulators • Audio output disable for standby mode Operating Conditions • Single supply 12 ± 0.6 V 5 ± 0.25 V • Dual supply –5 ± 0.25 V 5 ± 0.25 V 12 ± 0.6 V • Operating temperature Topr –20 to +75 °C • Maximum ESD voltage ±2 kV (Human Body Model) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02750A41 CXA7002R Block Diagram (1) Video Section GAIN ADJUST DIG BLUE VCR BLUE DIG GREEN/CVBS VCR GREEN DIG RED/CHROMA VCR RED/CHROMA VIN_1 VIN_2 54 VIN_3 VIN_5 DC Restore DC Restore DC Restore /C Bias AUX CHROMA VIN_13 55 C Bias DIG CVBS/LUMA VIN_8 10 Sync Tip Clamp DIG CVBS/LUMA VIN_9 11 Sync Tip Clamp VCR CVBS/LUMA VIN_10 52 Sync Tip Clamp TV CVBS VIN_11 57 Sync Tip Clamp AUX Y/CVBS VIN_12 56 Sync Tip Clamp Sync Detector VID_BIAS 1 VOUT_2 GREEN 63 VOUT_3 C Bias VIN_6 BLUE TV 9 DIG CHROMA VOUT_1 DC Restore/ C Bias 8 VIN_7 51 2 DC Restore 7 VIN_4 53 RGB Gain Control (+1, 2, 3dB) DC Restore 6 4 TRAP 3 VOUT_7 RED/CHROMA RF MOD Mix Switch Mix Switch 62 VOUT_4 LUMA/CVBS 60 VOUT_5 CHROMA Bi-directional Control INTERUPT VCR 5 GND 12 61 VOUT_6 GND 37 LUMA/CVBS –5V_GNDA 13 59 GND_VID –5V_GNDA 36 64 +5V_VOUT –5V_GNDA 27 58 +5V_VID +12V 17 46 AUD_BIAS +5V_DIG 24 35 VCC_AUD GND_DIG 25 AUD_BIAS 26 +5/12V_VCCA 28 Note) All video outputs contain 75Ω drivers. –2– TV (2) Audio Section Mono Switch 12dB 31 MONO 12dB 30 PHONO_R 12dB 16 RTV Vol Bypass (Phono) Overlay on/off Volume Control +6 to –56dB AUDIO SWITCH1 (TV) RIN_1 (DIG) 41 –6dB RIN_2 (VCR) 44 –12dB RIN_3 (TV/OVERLAY) 47 –12dB RIN_4 (AUX) 49 –12dB LIN_1 (DIG) 42 –6dB LIN_2 (VCR) 45 –12dB LIN_3 (TV/OVERLAY) 47 –12dB LIN_4 (AUX) 50 –12dB Vol Bypass (TV) Limiter 2.2Vrms 2dB TV Overlay on/off ZCD Limiter 2.2Vrms 2dB Vol Bypass (TV) –3– 12dB 15 LTV 12dB 29 PHONO_L 12dB 33 ROUT1 Mono Switch Vol Bypass (Phono) Tone mix AUDIO SWITCH2 (VCR) VCR 12dB 32 LOUT1 Mono and R/L Switch Bias 19 Hardware Mute CXA7002R H/W MUTE Mute CXA7002R (3) Digital Section FBLK_SW +3.5V 0V 21 TV_FBLK FBLK_IN1 20 FBLK_IN2 23 Logic Control SDA 38 SCL 39 0/6/12V FNC_VCR 22 14 LOGIC 18 FNC_TV 0/6/12V Sync Detector Interrupt Control Monitor –4– 40 INTERUPT CXA7002R LIN_3 RIN_3 AUD_BIAS LIN_2 RIN_2 SYNC_ID LIN_1 RIN_1 INTERUPT SCL SDA GND –5V_GNDA Vcc_AUD GND_AUD ROUT1 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RIN_4 49 32 LOUT1 LIN_4 50 31 MONO VIN_7 51 30 PHONO_R VIN_10 52 29 PHONO_L VIN_4 53 28 +5/+12V_VccA VIN_2 54 27 –5V_GNDA VIN_13 55 26 AUD_BIAS VIN_12 56 25 GND_DIG VIN_11 57 24 +5V_DIG +5V_VID 58 23 FBLK_IN2 GND_VID 59 22 FNC_VCR VOUT_5 60 21 TV_FBLK VOUT_6 61 20 FBLK_IN1 VOUT_4 62 19 HW_MUTE VOUT_3 63 18 FNC_TV 17 +12V VOUT_1 VOUT_7 TRAP VID_BIAS VIN_1 VIN_3 VIN_5 9 10 11 12 13 14 15 16 RTV 8 LTV 7 LOGIC 6 –5V_GNDA 5 GND 4 VIN_9 3 VIN_8 2 VIN_6 1 VOUT_2 +5V_VOUT 64 –5– CXA7002R Pin Description Pin No. Symbol Pin voltage [V] Equivalent circuit Description VCC 6 54 53 VIN_1 VIN_2 VIN_4 6 2.5 1.2k RGB signal inputs 54 53 2k VCC 2.5 1.2k 7 7 VIN_3 RGB signal input or CVBS signal input 3k 2.4 VCC 2.5 8 51 50k RGB signal inputs or Chrominance signal inputs 1.2k 8 VIN_5 VIN_7 51 3.1 VCC 9 55 VIN_6 VIN_13 3.1 50k Chrominance signal inputs 9 55 VCC 10 11 52 57 56 VIN_8 VIN_9 VIN_10 VIN_11 VIN_12 2.4 1.2k 10 57 11 56 52 –6– CVBS/Luminance signal inputs CXA7002R Pin No. 2 1 63 62 61 3 Symbol VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOUT_6 VOUT_7 Pin voltage [V] Equivalent circuit Description VCC 2 62 0.6 1 61 20k RGB/CVBS signal outputs 63 3 VCC 60 VOUT_5 1.8 60 Chrominance signal output 20k VCC VCC 40.8k 5 VID_BIAS 0.9 5 9.2k Internal reference bias for video circuits. A capacitor is connected from this pin to GND. Typically 100nF VCC 4 TRAP 2.4 1.2k 4 Connects trap circuit for subcarrier 1.2k VCC 200 43 SYNC_ID 2.5 43 200 Sync detect circuit time constant, resistor and capacitor connection pin VCC VCC/2 42 41 LIN_1 RIN_1 2.5 50k 42 41 50k VCC 45 44 48 47 50 49 LIN_2 RIN_2 LIN_3 RIN_3 LIN_4 RIN_4 45 44 2.5 Audio signal inputs VCC 6.25k 50k 48 47 50 49 –7– Audio signal inputs CXA7002R Pin No. Symbol 15 16 32 33 29 30 31 LTV RTV LOUT1 ROUT1 PHONO_L PHONO_R MONO Pin voltage [V] Equivalent circuit VCC 6.0 (Single) 15 16 40k 32 33 AUD_BIAS 31 VCC 25k 2.5V (Single/ Dual) Capacitor Internal reference bias connected to GND. for audio circuit (Typically 22µF) 46 25k VCC 6.0 (Single) 26 Audio signal outputs 29 30 0.0 (Dual) VCC 46 Description Capacitor connected to GND. (Typically 22µF) VCC 40k 124 Internal reference bias for audio circuit Connected directly to GND. 26 AUD_BIAS 40k 0.0 (Dual) VCC 20 23 FBLK_IN1 FBLK_IN2 124 — Fast blanking signal inputs 20 23 VCC 21 TV_FBLK — 21 Fast blanking signal output 124 22 76.7k 22 FNC_VCR — SCART function pin 8 input/output to VCR 16.5k 124 18 FNC_TV — 18 19k 36k –8– SCART function pin 8 output to TV CXA7002R Pin No. Symbol Pin voltage [V] 19 HW_MUTE — 14 LOGIC (Vcc = +12V) — Equivalent circuit Mutes audio outputs when pin voltage is below 2V. This pin is normally connected to +5V. 124 19 VCC 14 40 INTERUPT (Vcc = +5V) 39 SCL Description 40 — 8k Open connector logic outputs Typically connect to +5V through 10kΩ resistor. I2C bus clock line 39 — 38 38 SDA I2C bus data line 24 +5V_DIG Digital supply 64 +5V_VOUT 58 +5V_VID Video supply 35 Vcc_AUD Audio supply 17 +12V 13 17 36 –5V_GNDA –5.0 (Dual) 0.0 (Single) Audio supply/ground 28 +5V/12V_VccA 5.0 (Dual) 12.0 (Single) Audio supply 12 37 GND 0.0 25 GND_DIG 0.0 Digital ground 34 GND_AUD 0.0 Audio Ground 59 GND_VID 0.0 Video ground Video output supply 5.0 Digital supply 12.0 –9– CXA7002R Electrical Characteristics Nominal conditions (Ta = 25°C) Item Current consumption (Single ended supply) Current consumption (Dual supply) Symbol Conditions Min. Typ. Max. Unit Icc1 +12 supply, no signal, no load — 30 55 mA Icc2 +5 supply, no signal, no load — 60 85 mA Icc3 +12 supply, no signal, no load — 10 30 mA Icc4 +5 supply, no signal, no load — 80 110 mA Icc5 –5 supply, no signal, no load –50 –20 — mA (1) Video System Nominal conditions single supply (Ta = 25°C, +5V/12V_VccA = +12V, –5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V) Item Symbol Conditions Min. Typ. Max. Unit Vclmp1 Vin3, Vin8, Vin9, Vin10, Vin11, Vin12 inputs. (Vin3 set to CVBS mode) (Fig. 1) — 2.4 — V Cbias1 Vin5, Vin7 inputs. Clamps set to Chroma bias mode. (Fig. 1) — 3.1 — V Cbias2 Vin6, Vin13 inputs. (Fig. 1) — 2.45 — V RGB dc restore input voltage RGB1 Vin1, Vin2, Vin3, Vin4, Vin5, Vin7 inputs. (Vin3 & Vin5 set to RGB mode) (Fig. 1) — 2.5 — V Sync tip clamp voltage at output Vclmp2 Vout4, Vout6 outputs (Fig. 1) — 0.3 — V Chroma bias output voltage Cbias3 Vout3, Vout5 outputs (Fig. 1) — 1.8 — V RGB dc restore output voltage RGB2 Vout1, Vout2, Vout3 outputs (Fig. 1) — 0.6 — V Gain (Vout1 to 7) GVv f = 200kHz, 0.3Vp-p input, RGB Gain = 0dB, Input Gain = 0dB (Fig. 2) 5.5 6.0 6.5 dB GVRGB1 f = 200kHz, 0.3Vp-p input, RGB Gain = +1dB, Input Gain = 0dB (Fig. 2) 6.5 7.0 7.5 dB GVRGB2 f = 200kHz, 0.3Vp-p input, RGB Gain = +2dB, Input Gain = 0dB (Fig. 2) 7.5 8.0 8.5 dB GVRGB3 f = 200kHz, 0.3Vp-p input, RGB Gain = +3dB, Input Gain = 0dB (Fig. 2) 8.5 9.0 9.5 dB Gi/p1 f = 200kHz, 0.3Vp-p input, Video gain = +1dB (Fig. 2) 6.5 7.0 7.5 dB Gi/p1 f = 200kHz, 0.3Vp-p input, Video gain = +3dB (Fig. 2) 8.5 9.0 9.5 dB Gi/p1 f = 200kHz, 0.3Vp-p input, Video gain = +6dB (Fig. 2) 11.5 12.0 12.5 dB Sync tip clamp voltage at input Chroma bias input voltage Gain (Vout1, 2, 3) Video input gain Vin 1, 3, 5, 6, 8, 9 – 10 – CXA7002R Item Symbol Conditions Min. Typ. Max. Unit 15 30 — MHz 8 30 — MHz Bandwidth (Vout7) Mixer on – No trap components fV3dB 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB. (Fig. 2) Input dynamic range VDRVI 200kHz input applied to any video (Fig. 2) 1.4 — — Vp-p Output dynamic range VDRVO 200kHz input applied to any video (Fig. 2) 2.8 — — Vp-p Cross talk Vctv f = 4.43MHz, 1Vp-p input (Fig. 2) — –65 — dB Fast blanking to RGB delay DelFB Falling edge delay from RGB to fast blank signal. Measured at 20% level. (Fig. 2) 50 ns Vout5 impedance when switched to ground ZVout5 2V applied to Vout5 with series 75Ω resistor. Measured voltage at pin and calculate Zout. (Fig. 2) — 1 — Ω S/N ratio S/NV Ratio of 0.7Vp-p white video signal to "black line" noise. Weighted using CCIR 567. HPF@5kHz, LPF@5MHz. (Fig. 2) — 74 — dB Non-linearity Lin V1 = Pin voltage + 0.5V, V2 = Pin voltage + 1V –4 0 4 % –3 0 3 % V1 V2 fV3dB Input pin V plus Bandwidth (Vout1 to 6) 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB. Filter Bypassed. (Fig. 2) At output, non-linearity V2 = –1 × 100 (Fig. 2) V1 × 2 Differential gain DG 1.7Vp-p 5-step modulated staircase. (Chroma & Burst are 150mVp-p, 4.43MHz) (Fig. 2) Differential phase DP As above. (Fig. 2) –3 0 3 deg Attn Measured 27MHz signal relative to signal at 1MHz. (Fig. 2) — –47 –24 dB Filter specification Attenuation @27MHz – 11 – CXA7002R Audio System Unless otherwise stated: input coupling capacitor 1µF; output coupling capacitor of 10µF; load of 10kΩ. Nominal conditions single supply (Ta = 25°C, +5V/12V_VCCA = +12V, –5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Nominal conditions dual supply (Ta = 25°C, +5V/12V_VCCA = +5V, –5V_GNDA = –5V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Symbol Conditions Min. Typ. Max. Unit Input pin voltage (Single/Dual supply) VAPIN1 No signal, no load (Fig. 3) 2.25 2.5 2.75 V Output pin voltage (Single supply) VAPIN2 No signal, no load (Fig. 3) 5.75 6 6.25 V Output pin voltage (Dual supply) VAPIN2 No signal, no load (Fig. 3) –0.25 0 0.25 V Output pin voltage when disabled (Single/Dual supply) VAPIN3 No signal, no load (Fig. 3) –0.25 0 0.25 V Gain Input Output Rin1 or Lin1 TV or Phono GVA1 f = 10kHz, 0.3Vp-p input (Fig. 4) 5.7 6.2 6.7 dB Rin1 or Lin1 VCR GVA2 f = 10kHz, 0.3Vp-p input (Fig. 4) 5.7 6.2 6.7 dB Rin1 + Lin1 TV (mono mix) GVA3 f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB, TV mono switch on (Fig. 4) 5.7 6.2 6.7 dB Rin1 + Lin1 MONO GVA4 f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB (Note 1) (Fig. 4) 5.7 6.2 6.7 dB Rin2, 3, 4 or Lin2, 3, 4 TV, VCR, Phono GVA5 f = 10kHz, 0.3Vp-p input, TV volume set to 0dB (Fig. 4) –0.3 0.2 0.7 dB Rin1 + Lin1 VCR (mono mix) GVA6 f = 10kHz, 0.3Vp-p stereo input, VCR mono switch on (Fig. 4) 5.7 6.2 6.7 dB Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 MONO GVA7 f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB (Note 1) (Fig. 4) –0.3 0.2 0.7 dB Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 VCR (mono mix) GVA9 f = 10kHz, 0.3Vp-p input, VCR mono switch on (Fig. 4) –0.3 0.2 0.7 dB Rin3 RTV, ROUT1, Phono_R GVA10 f = 10kHz, 0.3Vp-p, Lin3 has no signal Audio overlay enabled. –12.5 –11.75 –11.25 (Fig. 4) dB Lin3 LTV, LOUT1, Phono_L GVA11 f = 10kHz, 0.3Vp-p input Audio overlay enabled. (Fig. 4) dB Note 1) Mono switch set to mix RTV & LTV after volume control. – 12 – –12.5 –11.75 –11.25 CXA7002R Item Symbol Condition Min. Typ. Max. Unit Audio frequency response FAF 0.3Vp-p input. Output/Input gain at 30kHz with 10kHz serving as 0dB (Fig. 4) –0.3 0 0.3 dB Distortion THD f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @80kHz (Fig. 4) — 0.005 0.1 % Input dynamic range Rin2, 3, 4/Lin2, 3, 4 VdA1 f = 1kHz, RIN1/LIN1 input amplifier set to –6dB. Dual supply mode used. (Fig. 4) 2.5 2.9 — Vrms Input dynamic range Rin1/Lin1 VdA1 f = 1kHz (Fig. 4) 1.25 1.45 — Vrms Cross talk (Channel separation) VctA f = 10kHz, 1Vrms input on one input, measure on any audio output (Fig. 4) — –90 — dB Input impedance Rin1, 2, 3, 4/Lin1, 2, 3, 4 Zin1 (Excluding any external series resistor) (Fig. 4) — 100 — dB S/N ratio S/NA f = 1kHz, 1Vrms input (0dB volume). (20Hz to 20kHz) BPF + A weighting filter (Fig. 4) 80 — — dB Volume attenuation step AEVC f = 10Hz, 0.5Vp-p. Set by I2C (Fig. 4) 1.6 2 2.4 dB Audio limiter level Alimit f = 1kHz, 2.5Vrms input. Measure TV pk-pk output with limiter switched on. (Fig. 4) — 2.2 — Vrms Mute TV I/P Mute or VCR I/P MUTE Amute f = 1kHz, 1Vrms input (Fig. 4) — –85 — dB Electronic Volume Control – 13 – CXA7002R Digital Characteristics (1) I2C Interface The I2C interface is compliant with Philips I2C Fast Mode specification (data April 1995). The interface is also capable of interfacing to +3.3V or +5V logic levels. Symbol Item Condition Min. Typ. Max. Unit High level input voltage VIH 2.3 — 5.5 V Low level input voltage VIL 0 — 1.5 V Low level output voltage VOL With SDA, 3mA current supplied 0 — 0.4 With SDA, 6mA current supplied 0 — 0.6 Hysteresis of schmitt trigger input VHYST VIH – VIL — 0.5 — V Spike suppression — — 50 ns 400pF bus load — — 300 ns SCL clock frequency tSP tF tSCL I2C bus line requirement 0 — 400 kHz Bus free time between a stop and start tBUF I2C bus line requirement 1.3 — — µs I2C bus line requirement 0.6 — — µs I 2C bus line requirement 1.3 — — µs High period of SCL clock tHD;STA tLOW tHIGH I2C bus line requirement 0.6 — — µs Setup time for a repeated start condition tSU;SDA I2C bus line requirement 0.6 — — µs tHD;DAT tSU;DAT tSU;STO I2C bus line requirement 0 — 0.9 µs Fall time for SDA line Hold time (repeated start condition) Low period of SCL clock Data hold time Data setup time Setup time for stop condition tBUF I 2C bus line requirement 100 — — µs I 2C bus line requirement 0.6 — — µs tR tF tHD;STA tHD;STA P S tLOW tSU;DAT V tHIGH tSU;DAT – 14 – tSU;STA tSU;STO Sr P CXA7002R (2) Slow Blanking Load = 10kΩ, supply +12V = +12V Item Symbol Condition Min. Typ. Max. Unit Input threshold low level VTH1 — 3 — V Input threshold high level VTH2 — 8.1 — V Output low level (Int TV mode) VOUT1 Load = 10kΩ — 0.3 0.8 V Output level (Ext 16:9 mode) VOUT2 Load = 10kΩ 4.8 5.5 6.5 V Output level (Ext 4:3 mode) VOUT3 Load = 10kΩ 10 11 — V Condition Min. Typ. Max. Unit (3) Fast Blanking Output load = 150Ω, supply +5V_VOUT = +5V Item Symbol Input threshold VTH3 Measured on fast blanking input 1, 2 — 0.7 — V Input current IIN1 +2V applied to input — 2 — µA Output low level VOUT4 Load = 150Ω 0.2 V Output high level VOUT5 Load = 150Ω — V 3 — (4) logic and interrupt output These outputs are open collector type and normally connected to +5V through a 10kΩ resistor. Item Output low voltage Symbol Condition DIGVOUTL IOL = 1mA – 15 – Min. Typ. Max. Unit — — 0.4 V CXA7002R +5V 68k I2C SCL SDA 100nF 22µF +5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 100nF 75 100nF 75 100nF 75 100nF 75 100nF 75 100nF 75 100nF +5V +5V V Measurement Point 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 100nF 100nF 100nF 100nF 100nF 100nF 75 75 75 75 75 75 Measurement Point 22µF +5V +12V 10 11 12 13 14 15 16 V V +12V 100nF 75 49 Measurement Point Fig. 1. Video System (DC Tests) DC measured from Pins 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 51, 52, 53, 54, 55, 56, 57, 60, 61, 62, 63 Notes) 1. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10µF capacitors. 2. All video outputs are unloaded during tests. – 16 – CXA7002R +5V 68k I2C SCL SDA 100nF +5V 22µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 75 100nF 75 100nF 75 100nF 75 100nF +5V +5V 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 100nF Input Signal 6 7 8 9 22µF +5V +12V 10 11 12 13 14 15 16 Input Signal 75 75 75 75 75 75 150 150 150 150 150 150 150 V Measurement Point +12V 100nF 100nF 30 100nF 75 51 100nF 100nF 31 100nF 75 50 100nF 100nF 32 100nF 75 49 Fig. 2. Video System (Gain, Dynamic Range, Bandwidth, Differential Gain, Differential Phase, Crosstalk, Linearity) Signal applied to Pins 51, 52, 53, 54, 55, 56, 57, 6, 7, 8, 9, 10, 11 Output signal measured from Pins 60, 61, 62, 63, 64, 1, 2, 3 Notes) 1. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10µF capacitors. 2. For video crosstalk tests all video inputs are terminated with 37.5Ω. – 17 – CXA7002R V –5V 22µF I2C SCL SDA Input Measurement Point +5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +5V +5V 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 2 3 4 5 6 7 8 9 +12V +5V Output Measurement Point –5V 22µF +5V +12V 10 11 12 13 14 15 16 100nF 1 V –5V Fig. 3. Audio System (DC Tests) DC measured from Pins 29, 30, 31, 32, 41, 42, 44, 45, 47, 48, 49, 50 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10µF capacitors. – 18 – 1µF 1µF 1µF 1µF 1µF –5V I2 C SCL SDA 22µF 1µF 1µF 1µF CXA7002R Input Signal +5V 10µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +5V +5V 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10µF 10µF V 10k 10µF 10µF +12V +5V Output Measurement Point –5V 22µF +5V +12V 10 11 12 13 14 15 16 100nF 10µF 10µF –5V Fig. 4. Audio System (Gain, Bandwidth, Signal to Noise, Electronic Volume, Zero Cross Detection, Dynamic Range, Crosstalk) Signal applied to Pins 41, 42, 44, 45, 47, 48, 49, 50 Output signal measured from Pins 29, 30, 31, 32, 33 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to the supply pins, 17, 24, 58, 64 with 10nF and 10µF capacitors. – 19 – CXA7002R I2C Control Data Format S Slave address A S: Start condition DATA1 A DATA2 A: Acknowledge A DATA3 A DATA4 A DATAn A P P: Stop condition Address = 90H I2C Data Structure (write mode) Address b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 0 0 = Write Data1 AUDIO VCR MONO LIMITER SWITCH Data2 MONO SWITCH TV MONO SWITCH TV VOL BYPASS Data3 TV AUD MUTE TV INPUT MUTE ZCD Data4 VIDEO INPUT GAIN Data5 FILTER CONTROL Data7 VOUT5_0 V AUDIO DISABLE TV AUDIO SELECT LOGIC LEVEL PHONO BYPASS VCR INPUT OVERLAY MUTE ENABLE 0 FNC TV FAST BLANK RGB GAIN TV VIDEO SWITCH VIN5 CLAMP VIN7 CLAMP VIN3 CLAMP ENABLE VOUT6 ENABLE VOUT5 ENABLE VOUT4 ENABLE VOUT3 ENABLE VOUT2 ENABLE VOUT1 SYNC SEL ENABLE VOUT7 VCR AUDIO SELECT FNC VCR VCR VIDEO SWITCH Data6 TV AUD MUTE VOLUME CONTROL MIXER CONTROL I2C Data Structure (read mode) Address Data b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 0 1 = Read NOT USED NOT USED ZERO CROSS STATUS P.O.D. NOT USED SYNC DETECT Note) ZCD = Zero Cross Detect P.O.D. = Power on Detect – 20 – FNC_VCR CXA7002R I2C Video Control TV Video Control [Data 5 Bits 0, 1, 2] Switch setting Vout1 Blue Vout2 Green 0 xxxxx000 Encoder Blue VIN1 Encoder Green VIN3 Encoder Red VIN5 Encoder CVBS VIN8 Digital encoder RGB or CVBS 1 xxxxx001 Bias Bias Encoder Chroma VIN6 Encoder Luma VIN9 Digital encoder Y/C 2 xxxxx010 VCR Blue VIN2 VCR Green VIN4 VCR Chroma/Red VIN7 VCR CVBS/Y VCR Y/C or RGB VIN10 3 xxxxx011 Bias Bias Bias TV CVBS VIN11 TV 4 xxxxx100 Bias Bias Encoder Chroma VIN5 Encoder Luma VIN3 Digital encoder Y/C 5 xxxxx101 Encoder blue VIN1 Encoder Green VIN3 Encoder Red VIN5 Aux CVBS VIN12 Encoder RGB and AUX CVBS 6 xxxxx110 Bias Bias Aux Chroma VIN13 Aux CVBS/Y VIN12 Aux Y/C or CVBS 7 xxxxx111 Bias Bias Bias Bias Video Mute Vout3 Red/Chroma Vout4 CVBS/Y After power on all TV outputs are off (high impedance) and muted. TV RGB Gain Control [Data 5 Bits 3, 4] I2C setting "RGB GAIN" Extra gain/dB 0 xxx00xxx 0 1 xxx01xxx +1 2 xxx10xxx +2 3 xxx11xxx +3 The power on default is 0dB. – 21 – Comment CXA7002R VCR Video Control [Data 5 Bits 5, 6, 7] Vout5 Chroma Switch setting Vout6 CVBS/Y Comment 0 000xxxxx Encoder Chroma VIN5 Encoder CVBS/Y VIN8 Digital encoder Y/C 1 001xxxxx Encoder Chroma VIN6 Encoder Luma VIN9 Digital encoder Y/C 2 010xxxxx VCR Chroma VIN7 VCR CVBS/Y VIN10 VCR Y/C 3 011xxxxx Bias TV CVBS VIN11 TV CVBS 4 100xxxxx Encoder Chroma VIN5 Encoder Luma VIN3 Encoder Y/C 5 101xxxxx Bias Aux CVBS VIN12 AUX CVBS 6 110xxxxx Aux Chroma VIN13 Aux CVBS VIN12 AUX Y/C 7 111xxxxx Bias Bias Video mute After power on VCR outputs are off (high impedance) and muted. "Y/C MIXER CONTROL" [Data 6 Bits 0, 1] I2C setting Vout7 Mixer output 0 xxxxxx00 No mix, Vout7 = Vout4 (CVBS) 1 xxxxxx01 Mix Vout4 (Y) + Vout3 (C) 2 xxxxxx10 No mix, Vout7 = Vin8 (CVBS) 3 xxxxxx11 No mix Vout7 = Vout4 (CVBS) The power on default is no mix. Input Clamp Control "VIN3 Clamp" [Data 6 Bit 2] xxxxx0xx = GREEN input on VIN3. DC restore clamp active. (Power on default) xxxxx1xx = CVBS input on VIN3. Sync tip clamp active. Input Clamp Control "VIN7 Clamp" [Data 6 Bit 3] xxxx0xxx = CHROMA input on VIN7. Chroma bias applied. (Power on default) xxxx1xxx = RED input on VIN7. DC restore clamp applied. Input Clamp Control "VIN5 Clamp" [Data 6 Bit 4] xxx0xxxx = RED input on VIN5. DC restore clamp applied. (Power on default) xxx1xxxx = CHROMA input on VIN5. Chroma bias applied. – 22 – CXA7002R Sync Select Control for RGB DC Restore Circuits "SYNC_SEL" [Data 6 Bits 5, 6] When the TV output is set to RGB + Y/CVBS mode. Then it is necessary to select the input that contains the sync information for the RGB signal. This will normally be the digital encoder CVBS or VCR CVBS input. I2C setting "SYNC_SEL" Input with sync 0 x00xxxxx VIN8 1 x01xxxxx VIN9 2 x10xxxxx VIN10 3 x11xxxxx VIN12 The power on default is Vin8 ie. Digital encoder input. Video Input Gain [Data 4 Bits 6, 7] Extra gain applied to Vin1, 3, 5, 6, 8, 9 I2C setting "VIDEO INPUT GAIN" Extra gain/dB 0 00xxxxxx 0 (Bypass) 1 01xxxxxx +1 2 10xxxxxx +3 3 11xxxxxx +6 The power on default is bypass. Filter Control [Data 6 Bit 7] The filters on the six digital encoder inputs Vin1, 3, 5, 6, 8, 9 are switched on with this control bit. 0xxxxxxx = Filter bypass. Power on default. 1xxxxxxx = Filter on. Standby Mode Control [Data 7 Bits 0, 1, 2, 3, 4, 5, 6] The video outputs VOUT1, 2, 3, 4, 5, 6, 7 can be individually turned off using data byte 7. 0 = Video output off. (Power on default) 1 = Video output on. Note) When switched off, the video outputs are in a high impedance state. With a normal 150Ω load, the outputs will be pulled to 0V. – 23 – CXA7002R Bi-directional Line Control on VCR Scart "Vout5_0V" [Data 7 Bit 7] 0xxxxxxx = Vout5 active. Connected to input specified in VCR switch table. 1xxxxxxx = Vout5 set to 0V. I = 10mA (When set to 0V mode) VCR Scart 75Ω 6dB VOUT_5 Chroma output Vout5 0V Pin 15 Red in Chroma in Chroma out VIN_7 Red in Chroma in Fig 5. Bi-directional Line to VCR As Pin 15 on the VCR scart can be bi-directional, either chroma output or red/chroma input, it is necessary for output Vout5 to be individually controlled. When the red or chroma signal comes from the VCR, then output Vout5 is set to 0V giving the required line termination impedance of 75Ω. – 24 – CXA7002R I2C Audio Signal Control TV and Phono Audio Control [Data 2 Bits 1, 2] Switch setting RTV, Phono_R LTV, Phono_L 0 xxxxx00x Rin1 Lin1 1 xxxxx01x Rin2 Lin2 2 xxxxx10x Rin3 Lin3 3 xxxxx11x Rin4 Lin4 After power on Rin1/Lin1 are selected. VCR Audio Control [Data 2 Bits 3, 4] Switch setting Rout1 Lout1 0 xxx00xxx Rin1 Lin1 1 xxx01xxx RTV signal LTV signal 2 xxx10xxx Rin3 Lin3 3 xxx11xxx Rin4 Lin4 After power on Rin1/Lin1 are selected. TV Mono Switch [Data 2 Bit 6] Switch setting Connection to R channel output Connection to L channel output 0 x0xxxxxx R L 1 x1xxxxxx (R + L mix) (R + L mix) Comment Normal Mono mix VCR Mono Switch [Data 1 Bit 6] Switch setting Connection to R channel output Connection to L channel output 0 x0xxxxxx R L 1 x1xxxxxx (R + L mix) (R + L mix) Comment Normal Mono mix "AUDIO DISABLE" [Data 3 Bit 4] xxx0xxxx = Normal outputs xxx1xxxx = All outputs disabled. When the outputs are disabled, they are in a high impedance state. For a single supply configuration, the output voltage will drop to 0V. "PHONO BYPASS" [Data 2 Bit 0] xxxxxxx0 = Phono outputs connected after volume control block. (Default) xxxxxxx1 = Phono outputs connected before volume control block. – 25 – CXA7002R "TV VOL BYPASS" [Data 2 Bit 5] xx0xxxxx = TV outputs connected after volume control block. (Default) xx1xxxxx = TV outputs connected before volume control block. "MONO SWITCH" [Data 2 Bit 7] 0xxxxxxx = Mono output connected to mix of TV R + L channels. (Default) 1xxxxxxx = Mono output connected to mix of RIN1 + LIN1 inputs. "VOLUME CONTROL" [Data 1 Bits 1, 2, 3, 4, 5] Setting Volume gain 0 xx00000x +6dB 1 xx00001x +4dB 2 xx00010x +2dB 3 xx00011x 0dB (power on default) 4 xx00100x –2dB 5 xx00101x –4dB 6 xx00110x –6dB 7 xx00111x –8dB 8 xx01000x –10dB 9 xx01001x –12dB 10 xx01010x –14dB 11 xx01011x –16dB : 31 xx11111x : –56dB "OVERLAY ENABLE" [Data 3 Bit 0] xxxxxxx0 = Overlay off (Power on default) xxxxxxx1 = Overlay on: Rin3 and Lin3 are mixed and added to Rin1, Lin1 channels. TV Mute and Zero Cross Operation When the zero cross is switched on (ZCD = 1), volume control changes are only implemented when the audio signal passes though the zero cross point. Similarly, when a mute instruction is sent, the TV outputs are only muted when the signal passes the zero cross point. This eliminates any click noise. There are two TV audio mute control bits in the bus map. By having two bits it allows the TV outputs to be muted, the TV channel changed and then un-muted all in one I2C write operation. The normal structure for a click free audio channel change is as follows: Data 1: Mute the TV audio output with the ZCD switched on. Data 2: Change the TV audio source. Data 3: Un-mute the TV audio output again with the ZCD switched on. – 26 – CXA7002R Operation of the Mute circuit TV Audio Mute [Data 1 Bit 0], [Data 3 Bit 7] ZCD [Data 3 Bit 5] Operation TV, Phono, Mono output 0 0 Un-mute immediately 0 1 Un-mute on next zero cross 1 0 Mute immediately 1 1 Mute on next zero cross After power on TV Audio Mute = 1 and ZCD are set to 1. "TV INPUT MUTE" [Data 3 Bit 6] x0xxxxxx = The input to the TV switch is not muted. x1xxxxxx = The input to the TV switch is muted. (Power on default) "VCR INPUT MUTE" [Data 3 Bit 1] xxxxxx0x = The input to the VCR switch is not muted. xxxxxx1x = The input to the VCR switch is muted. (Power on default) "AUDIO LIMITER" [Data 1 Bit 7] When active, the output of the volume control block is limited to 2.2Vrms maximum. 0xxxxxxx = The volume control outputs are not limited. (Power on default) 1xxxxxxx = The volume control outputs are limited to 2.2Vrms. – 27 – CXA7002R Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode: Scart pin voltage = 0 to 0.4V 2. RGB mode: Scart pin voltage = 1 to 3.0V The threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA7002R has two fast blanking inputs, one associated with the digital encoder input (FBLK_IN1) and another associated with the VCR RGB/CVBS input (FBLK_IN2). These can be selected and switched to the output using an I2C instruction. In addition, the fast blank output pin can be set to a constant 0V or +3.5V by means of the I2C control. Hence there are four possible states. These are set according to the following table. "FAST_BLANK" [Data 4 Bits 0, 1] I2C setting "BLANK_LEVEL" Fast blank output pin voltage 0 xxxxxx00 0V (Power on default) 1 xxxxxx01 Same status as Fast Blank in 1 (0/+3.5V) 2 xxxxxx10 Same status as Fast Blank in 2 (0/+3.5V) 3 xxxxxx11 +3.5V Fast Blank Output Interface The Fast Blanking output pin is connected to the scart via a 75Ω resistor. Optional ESD protection circuitry can be added. 75Ω TV_FBLK T.V. 0V/3.5V 75Ω Scart line 16 CXA7002R Fig. 6. Fast Blanking Output Interface – 28 – CXA7002R Function Switching Operation (Pin 8 on scart) Both, VCR and TV function lines can be set to outputs and controlled independently. The TV function line has two modes, the first being control via I2C and secondly the follow mode where the output will follow the same state as the VCR input. When the VCR function lines is set as input, the level can be read back from the status resistor. An interrupt is generated when the level changes. "FNC TV_LEVEL" [Data 4 Bits 2, 3] These bits set the voltage at the output TV_FNC function line (Pin 8). I2C control "FNC_TV" Voltage at output Mode 0 xxxx00xx Follows VCR input Follows VCR input 1 xxxx01xx < 1V Internal TV 2 xxxx10xx > 4.5V, < 7V External scart input 16:9 mode 3 xxxx11xx > 9.5V External scart input 4:3 mode Note) After power on the output is internal TV mode ie. 0V at the pin. "FNC VCR_LEVEL" [Data 4 Bits 4, 5] These bits set the voltage at the output VCR_FNC function line (Pin 8). I2C control FNC_VCR Voltage at output Mode 0 xx00xxxx NA Input 1 xx01xxxx < 1V Internal 2 xx10xxxx > 4.5V, < 7V External scart input 16:9 mode 3 xx11xxxx > 9.5V External scart input 4:3 mode Note) The power on default is "Input" mode. +12V_DIG > 9.5V > 4.5V, < 7V < 1V FNC_VCR 10k Inside T.V. FNC_TV 330Ω maximum Scart Pin 8 Scart Pin 8 Fig. 7. TV Function Switch Output – 29 – 10k CXA7002R Logic and Interrupt Output Pins These two pins are open collector type and require an external pull-up resistor. Interrupt Output The interrupt pin will become a current sink for approximately 1µs when the VCR input function line changes from: a) 0 to 6V, 6 to 0V b) 0 to 12V, 12 to 0V c) 6 to 12V, 12 to 6V OR When the sync detector detects that a valid video signal has been added or removed. This pin will normally be connected to +5V through a 10kΩ resistor. Multiple interrupt signal may be generated for signals on the threshold of having a valid sync. Logic Output The logic output level can be changed using the logic output bit in the I2C register, "LOGIC_LEVEL". "LOGIC LEVEL" [Data 3 Bit 3] xxxxx0xx = Current sink mode resulting in < 0.4V saturation voltage on logic pin. (default) xxxxx1xx = Open collector/high output impedance on logic pin. Imax during current sink = 1mA +3 to +5V External resistors 10k 10k To Micro 1µs INT LOGIC Fig. 8. INT and Logic Line Interface – 30 – CXA7002R Read Mode Status Register The following information can be read from the status register: FNC VCR [Bits 0, 1] The status register bits 0, 1 hold the level of the input function line. Input pin voltage SCART mode FNC_VCR Read Data 8 b1 b0 0 to +2V (default) (Internal) 0 0 +4.5 to +7V (16:9 External) 1 0 +9.5 to +12V (4:3 External) 1 1 "SYNC DETECT" [Bit 2] Once a valid sync signal is detected on the input selected by "SYNC_SELECT" this bit is set to 1. The bit is reset to 0 every time the SYNC_SELECT is changed. It is assumed that when a video input is in-active then the input level will be 0V with minimum noise. "POD" (Power on Detect) [Bit 4] This bit is set to 1 after power on. It is then changed to 0 after the first I2C read. It is used to detect if the supply has been corrupted. If the POR bit is read as 1 at any time then the IC should be re-initialized to the correct I2C settings. "ZERO CROSS STATUS" [Bit 5] This audio function is used to determine if an input audio signal has passed the zero cross point. Zero cross point Input signal Bias voltage (2.5V) Fig. 9. Zero Cross Point 0 = No zero cross detected. 1 = Signal has passed through zero cross point. – 31 – CXA7002R Description of Operation Video Section Inputs and Outputs The video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video outputs. An internal +6dB amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation that occurs at the 75Ω series output resistor. Outputs VOUT_1 to VOUT_7 are capable of driving 150Ω loads. Output VOUT_7 is designed to interface to an RF Modulator. Composite/Luminance Inputs The 4 composite (or luma) inputs are ac coupled to the input pins. The signals are first sync tip clamped to a set level. These clamps are permanently active, therefore these inputs should only be used for signals with a sync. VCC = +5V VCC = +5V 1Vp-p 2Vp-p 2.4V 0.3V 0V 0V Output signal Input signal Fig. 10. CVBS/Y Waveforms RGB Inputs The RGB inputs are ac coupled to the input pins. The inputs have a dc restore circuit, which is used to set the blanking level to a fixed voltage. The clamps are controlled by the timing signal provided by the sync detect circuit. It is necessary to select the correct luma or CVBS signal associated with the RGB inputs for the sync select circuit. It is assumed that a sync signal will not be present on any of the RGB input signals. For inputs that can be either red or chroma then the clamp can be switched between the dc restore mode (for red input) and average level bias (for chroma). The RGB signals are fed through additional gain amplifiers which are controlled by I2C. These allow the nominal 0.7Vp-p signal to be increased to 0.8Vp-p, 0.9Vp-p or 1Vp-p. When the TV output is in Y/C mode, the RGB gain should be set to 0dB to prevent over amplification of the chroma output. VCC = +5V VCC = +5V 0.7Vp-p 1.4Vp-p 2.5V 0.6V 0V 0V Output signal Input signal Fig. 11. RGB Waveforms – 32 – CXA7002R DIG CVBS/Y DIG CVBS/Y VCR CVBS/Y AUX CVBS/Y RGB input clamp timing Sync Detection Circuit The clamp signals, used to restore the RGB level, are generated from the sync detect circuit. By using the "SYNC_DETECT" control bits, the 4 different CVBS/Y inputs may be selected. Once selected, the signal is compared with a threshold voltage 65mV above the tip level. If the signal is less than this threshold it is not passed to the next block. If greater than the threshold, it is passed to the discrimination circuit which checks that the duty cycle is greater than 91%. The discrimination block also contains a time constant which, when a sync is detected, holds the status line high for at least 7 video lines. If a valid sync signal is detected the "SYNC_DETECT" bit in the read register is set to 1. +5V_VID "SYNC_SELECT" LOGIC 68k External R/C SYNC_ID Comparator 0.1µF Duty Discrimination Sync detect circuit Status register "SYNC_DETECT" bit Interupt Control I2C GND_VID Fig. 12. Sync Detection Circuit Chroma Inputs The chroma signals are ac coupled to the input pins. The inputs have a fixed dc bias that sets the average level to approximately 3.1V for VIN_5 & VIN_7 and 2.45V for VIN_6 & VIN_13. For inputs that can also be RED signals the input circuit can be switched to the dc restore mode. Typical waveforms: VCC = +5V VCC = +5V 2.45V or 3.1V 0.7Vp-p 1.8V 0V 1.4Vp-p 0V Chroma input pin signal Chroma output pin voltage Fig. 13. Chroma Waveforms – 33 – CXA7002R Video Input Gain Stage The six inputs from the digital encoder, VIN_1, 3, 5, 6, 8, 9 may need further amplification. An adjustable gain stage is provided with settings of +1, 3, 6dB extra gain. For normal inputs (1Vp-p for CVBS, 0.7Vp-p for RGB), the gain section may be bypassed. Video Input filters To reduce any digital noise, the six inputs from the digital encode pass through a low pass filter. The filter has a high attenuation at the clock frequency of 27MHz. ±0.3dB 0dB –30dB 5MHz 27MHz Fig. 14. Basic Filter Response – 34 – freq CXA7002R Y/C Mixer A Y/C mixer can be used for mixing Luma and Chroma signals for use with an external RF modulator connected to VOUT_7. The Y/C mixer is controlled via the I2C data bus. The signal may be a mix of the TV Y/C signals or simply the TV CVBS signal. It is also possible to select the CVBS signal from the digital encoder. The circuit is shown in Fig. 15 with a trap circuit used to give 6dB attenuation at 4.43MHz of the Luma signal. R/C 6dB VOUT_3 6dB VOUT_4 0, 1, 2 or 3dB CVBS/Y Mixer switch 2k 6dB VOUT_7 VIN_8 = CVBS TRAP R For recommended values: see application circuit. C L Fig. 15. Internal Y/C Mixer Circuit Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output is set to a high impedance state and hence the current consumption and power dissipation is reduced. After power on, all the video outputs are set to the high impedance state. – 35 – CXA7002R Typical Video Interface Circuits Single or Dual Supply 100nF VIN_1 to VIN_13 75Ω Scart Fig. 16. Video Input Interface 75Ω VOUT_1 to VOUT_7 75Ω (Line C = 400pF max.) Scart Fig. 17. Video Output Interface – 36 – CXA7002R Audio Section Inputs and Outputs The audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and Phono outputs. The stereo outputs can be connected to any one of the 4 stereo inputs. All audio inputs have a –12dB attenuator except RIN_1 and LIN_1. Therefore, as an amplifier having +12dB of gain follows the interval switch, the net gain of the audio system from input to output is 0dB. The stereo input RIN_1/LIN_1 has fixed gain from input to output of +6dB. This input is typically connected to an audio DAC with full scale of 1Vrms or less. The output impedance of each audio amplifier is near zero. The output may be directly coupled to the scart for the dual supply case but must be ac coupled through a capacitor (typically 10µF) for the single supply case. The outputs are capable of driving 600Ω loads. The user may add additional low pass filters to the outputs. TV Output Switching The TV audio section is composed of an audio switch followed by a volume control stage. The volume is adjustable from +6dB to –56dB in 2dB steps. The volume control block includes a switchable limiter function to prevent the output signals exceeding 2.2Vrms. When activated, the output signals from the volume control block will be clamped to 2.2Vrms. A mono switch that allows the mixed R + L signal to be switched to the R and L output channels follows the volume control section. TV Mute This I2C mute function acts on the TV, Phono and Mono audio circuits. Audio mute will be implemented after an audio zero cross detection to reduce click noise if "ZCD" = 1. Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The volume change or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA3. This allows the software to action a mute, then after a delay (1/Audio_freq (min)) make any suitable changes to the audio source and then un-mute the output buffer. Such a period provides ample time to allow any audio signals to pass the zero cross point before the signal source is changed. VCR Output Switching The outputs ROUT1, LOUT1 have a fixed gain of 0dB from the input except when position 2 is selected. Position 2 selects the RTV and LTV signals. These signals are affected by the TV volume control. Phono outputs There is a stereo Phono output that carries the same signal as the TV output. This is typically used for connection to a hi-fi. The signal level of the Phono outputs is normally the same as the TV outputs however it is possible to bypass the volume section and set the Phono outputs to a fixed level. If any attenuation is required then this can be done externally. – 37 – CXA7002R Mono Output The mono output for the RF modulator has two settings. The first is a mix of the TV R + L channels. In this case, the output signal will have the same volume control as the RTV/LTV outputs. The second setting is a mix of the audio DAC inputs (RIN_1 + LIN_1). In this setting the output will always have fixed volume and if the tone overlay is used, this will appear on the output. Audio Overlay The inputs RIN_3, LIN_3 may be used for a normal stereo audio input or alternatively to overlay an external audio source onto the TV outputs. This may be a tone or voice. The R and L inputs are mixed and then added equally to the RIN_1 and LIN_1 inputs. The I2C control bit "AUDIO OVERLAY ENABLE" is used to switch on this facility. Audio Disable All the audio outputs may be disabled using the "Audio Output Disable" function (Data Byte 3 Bit 4). This disable mode is different from the normal mute as it puts the outputs into a high impedance state. The disable mode is different from the normal mute as it can be used for power reduction in standby modes. Hardware Mute The hardware mute input pin is used to instantaneously mute all the audio outputs. It has the same operation as the audio disable function. The outputs are muted when the pin goes below +2V. – 38 – CXA7002R Typical Audio Interface Circuits Supply type 1: Dual supply 0.1µF RIN_1, 2, 3, 4 LIN_1, 2, 3, 4 Scart Fig. 18. Audio Input Interface RTV, LTV ROUT1, LOUT1 PHONO_R, PHONO_L MONO Optional protection resistor Optional protection resistor To RF modulator 600Ω to 10kΩ (Line C = 400pF max.) Scart 600Ω to 10kΩ (Line C = 400pF max.) Fig. 19. Audio Output Interface Supply type 2: Single supply 0.1µF RIN_1, 2, 3, 4 LIN_1, 2, 3, 4 Scart Fig. 20. Audio Input Interface RTV, LTV ROUT1, LOUT1 10µF 600Ω to 10kΩ (Line C = 400pF max.) Scart PHONO_R, PHONO_L 10µF MONO To RF modulator 600Ω to 10kΩ (Line C = 400pF max.) ∗ For loads = 600Ω, larger capacitors may be needed Fig. 21. Audio Output Interface – 39 – CXA7002R Application in Set Top Box Inputs Outputs B G R CVBS C Y FAST BLANKING Digital Encoder B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH VIN_1 VIN_3 VIN_5 VIN_8 VIN_6 VIN_9 FBLK_IN1 VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK FNC_TV A/V switch VIN_2 VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 FNC_VCR VOUT_7 T.V. AUX CVBS VIN_11 CVBS/Y VIN_12 C VIN_13 B G T.V. R/C CVBS/Y FAST BLANKING FUNCTION SWITCH C CVBS/Y VCR CVBS RF MOD. Fig. 22. Video Application with 6 Output Digital Encoder Inputs Outputs B Digital G/CVBS Encoder R/C CVBS/Y FAST BLANKING Analogue C CVBS/Y Sat. B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH VIN_1 VIN_3 VIN_5 VIN_8 FBLK_IN1 VIN_6 VIN_9 VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK FNC_TV A/V switch VIN_2 VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 FNC_VCR VOUT_7 T.V. AUX CVBS B G T.V. R/C CVBS/Y FAST BLANKING FUNCTION SWITCH C CVBS/Y VCR CVBS RF MOD. VIN_11 CVBS/Y VIN12 C VIN13 Fig. 23. Video Application with 4 Output Digital Encoder – 40 – CXA7002R Audio Application L TV STB Audio DAC fs = 1Vrms RIN_1 LIN_1 RTV LTV VCR fs = 2Vrms RIN_2 LIN_2 ROUT1 LOUT1 VCR RIN_3 LIN_3 PHONO_R PHONO_L Hi-Fi RIN_4 LIN_4 MONO TV or STB Generated Voice/ Tone AUX fs = 2Vrms Fig. 24. Audio Application – 41 – R L RF Modulator R TV (Mono) CXA7002R Supply Connections +5V (±0.25V) +12V (±0.6V) AUD_BIAS (Pin 26) +5V/12V_VCCA +12V +5V_DIG +5V_VID +5V_VOUT VID_BIAS AUD_BIAS (Pin 46) –5V_GNDA GND_DIG GND_VID GND 0.1µF 22µF –5V (±0.25V) Fig. 25. Dual Supply +12V (±0.6V) 22µF AUD_BIAS (Pin 26) +5V (±0.25V) +5V/12V_VCCA +12V +5V_DIG +5V_VID +5V_VOUT VID_BIAS AUD_BIAS –5V_GNDA (Pin 46) GND_DIG 22µF Fig. 26. Single Ended Supply – 42 – GND_VID GND 0.1µF Application Circuit 1 Single Supply +5V 4 HEADER 2 1 68k TV_RIN TV_LIN 1 2 3 4 SUPPLIES +5V RF MODULATOR DIGITAL LIN1 100nF RF_VID 22µF DIGITAL RIN1 +12V SCL SDA MONO 10µF +5V PHONO R VCR_RED/C VCR_CVBS_IN VCR_GREEN VCR_BLUE 100nF 100nF 100nF 100nF 100nF AUX CHROMA 75 75 – 43 – 75 +5V VCR_RED/C VCR_CVBS_OUT TV_CVBS_OUT TV_RED/C AUX CVBS 100nF 75 TV_CVBS_IN 75 75 75 75 100nF 10µF LOUT1 MONO PHONO_R PHONO_L +5V/12V_VCCA –5V_GNDA AUD_BIAS GND_DIG +5V_DIG FBLK_IN2 FNC_VCR TV_FBLK FBLK_IN1 HW_MUTE FNC_TV +12V 100nF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10µF VCR_LOUT PHONO L 10µF 10µF 10µF +12V 22µF +5V VCR_FBLANK 330 75 TV_FBLANK 330 TV_FNC VCR_FNC 75 +12V 75 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 75 RIN_4 LIN_4 VIN_7 VIN_10 VIN_4 VIN_2 VIN_13 VIN_12 VIN_11 +5V_VID GND_VID VOUT_5 VOUT_6 VOUT_4 VOUT_3 +5V_ VOUT ROUT1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 100nF 100nF VOUT_2 VOUT_1 VOUT_7 TRAP VID_BIAS VIN_1 VIN_3 VIN_5 VIN_6 VIN_8 VIN_9 GND –5V_GNDA LOGIC LTV RTV AUX AUDIO L LIN _3 RIN_3 AUD_BIAS LIN_2 RIN_2 SYNC_ID LIN_1 RIN_1 INTERUPT SCL SDA GND –5V_GNDA VCC_AUD GND_AUD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AUX AUDIO R 10k 100nF 100nF Place Close to Supply Pins 17, 28 VCR_ROUT +5V VCR_LIN VCR_RIN Place Close to Supply Pins 24, 58, 64 100nF 100nF 100nF 22µF 100nF 100nF 100nF 22µF 75 FAST BLANKING INPUT TV_FNC TV_LIN TV_RIN 8 6 4 2 11 9 7 5 3 1 14 12 10 TV_GREEN TV_BLUE TV_LOUT TV_ROUT VCR_FNC VCR_LIN VCR_RIN 8 6 4 2 19 17 15 13 11 9 7 5 3 1 VCR SCART VCR_CVBS_OUT VCR_RED/C 1 12pF 100µH 10k 2 1.8k TV_LOUT 10µF TV_ROUT 10µF 16 21 +5V 10k +5V VCR_GREEN VCR_BLUE VCR_LOUT VCR_ROUT 100nF 100nF 100nF 100nF 100nF 100nF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXA7002R TV SCART TV_RED/C 18 DIG LUMA 10 13 VCR_FBLANK 20 DIG CVBS 12 15 VCR_CVBS_IN DIG CHROMA 14 17 TV_CVBS_OUT DIG RED/ CHROMA 16 19 DIG GREEN 18 DIG BLUE TV_FBLANK 20 21 100nF SKT2 SKT1 TV_CVBS_IN TV_GREEN TV_BLUE RF_VD 75 75 Application Circuit 2 Dual Supply +5V 1 2 3 4 4 HEADER +12V 2 1 68k TV_RIN TV_LIN +5V RF MODULATOR DIGITAL LIN1 100nF SUPPLIES RF_VID 22µF DIGITAL RIN1 –5V Place Close to Supply Pins 13, 27, 36 MONO –5V SCL SDA 10µF +5V PHONO R VCR_RED/C VCR_CVBS_IN VCR_GREEN VCR_BLUE 100nF 100nF 100nF 100nF 100nF AUX CHROMA 75 75 – 44 – 75 +5V VCR_RED/C VCR_CVBS_OUT TV_CVBS_OUT TV_RED/C AUX CVBS 100nF 75 TV_CVBS_IN 75 75 75 75 100nF 10µF LOUT1 MONO PHONO_R PHONO_L +5V/12V_VCCA –5V_GNDA AUD_BIAS GND_DIG +5V_DIG FBLK_IN2 FNC_VCR TV_FBLK FBLK_IN1 HW_MUTE FNC_TV +12V 100nF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10µF VCR_LOUT PHONO L 10µF 10µF 10µF +5V –5V +5V VCR_FBLANK 330 75 TV_FBLANK 330 TV_FNC VCR_FNC 75 +12V 75 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 75 RIN_4 LIN_4 VIN_7 VIN_10 VIN_4 VIN_2 VIN_13 VIN_12 VIN_11 +5V_VID GND_VID VOUT_5 VOUT_6 VOUT_4 VOUT_3 +5V_ VOUT ROUT1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 100nF 100nF VOUT_2 VOUT_1 VOUT_7 TRAP VID_BIAS VIN_1 VIN_3 VIN_5 VIN_6 VIN_8 VIN_9 GND –5V_GNDA LOGIC LTV RTV AUX AUDIO L LIN _3 RIN_3 AUD_BIAS LIN_2 RIN_2 SYNC_ID LIN_1 RIN_1 INTERUPT SCL SDA GND –5V_GNDA VCC_AUD GND_AUD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AUX AUDIO R 10k 100nF 100nF Place Close to Supply Pins 17, 28 +5V VCR_ROUT 100nF VCR_LIN VCR_RIN Place Close to Supply Pins 24, 58, 64 22µF 100nF 100nF 100nF 22µF 100nF 100nF 100nF 22µF 75 FAST BLANKING INPUT TV_FNC TV_LIN TV_RIN 8 6 4 2 11 9 7 5 3 1 14 12 10 TV_GREEN TV_BLUE TV_LOUT TV_ROUT VCR_FNC VCR_LIN VCR_RIN 8 6 4 2 17 15 13 11 9 7 5 3 1 VCR SCART VCR_CVBS_OUT VCR_RED/C 1 12pF 100µH 10k 2 1.8k TV_LOUT 10µF TV_ROUT 10µF 16 19 +5V 10k +5V VCR_GREEN VCR_BLUE VCR_LOUT VCR_ROUT 100nF 100nF 100nF 100nF 100nF 100nF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXA7002R TV SCART TV_RED/C 18 DIG LUMA 10 13 VCR_FBLANK 20 DIG CVBS 12 15 VCR_CVBS_IN DIG CHROMA 14 17 TV_CVBS_OUT –5V DIG RED/ CHROMA 16 19 DIG GREEN 18 21 DIG BLUE TV_FBLANK 20 21 100nF SKT2 SKT1 TV_CVBS_IN TV_GREEN TV_BLUE RF_VD 75 75 CXA7002R Notes on Operation 1) Supply de-coupling capacitors, 10nF and 10µF in parallel should be inserted as close as possible to the supply Pins 17, 24, 28, 35, 58 and 64. When using the dual supply configuration apply the capacitors to Pins 13, 27, 36 in addition to the listed supply pins. 2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) Attention should be given to the electrolytic capacitors on the output pins. In single supply configuration the audio pin dc bias voltage will be approximately 6.0V, therefore the positive terminal of the capacitors should be orientated towards the device pin. 4) To minimize stray capacitance the 75Ω series resistor on video outputs VOUT_1 to VOUT_7 should be mounted as close as possible to the device Pins 1, 2, 3, 60, 61, 62 and 63. 5) Pins 10, 11, 46, 52, 56, 57 have reduced ESD performance and external protection circuitry may be added. As shown in the application schematic, zener diodes may be added. Zener diodes with a rating > 5V may be used. – 45 – CXA7002R Typical Performance Curves Gain [dB] Video gain – VOUT_1, 2, 3, 4, 5, 6 7 6 5 4 3 2 1 0 VOUT_1, 2, 3 VOUT_4, 5, 6 1 10 100 Frequency [MHz] Gain [dB] Video gain – VOUT_7 7 6 5 4 3 2 1 0 –1 –2 Mixer Off Mixer On 1 10 100 Frequency [MHz] Audio gain 1 Gain [dB] 0 –1 –2 –3 –4 1 10 100 1000 10000 Frequency [kHz] –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 Audio THD + N RIN_2, 3, 4/LIN2, 3, 4 to TV outputs dB dB Audio THD + N RIN_1/LIN_1 to TV outputs 0.1 0.3 0.5 0.70.8 1 1.11.2 1.41.5 Input level [Vrms] –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 0.2 0.6 1 1.2 1.6 2 2.2 2.4 Input level [Vrms] – 46 – 2.8 3 CXA7002R Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 16 1 0.5 b 0.13 M + 0.2 1.5 – 0.1 0.1 0.1 ± 0.1 0˚ to 10˚ 0.125 ± 0.04 b = 0.18 ± 0.03 0.5 ± 0.2 Package Outline DETAIL B: PALLADIUM DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE P-LQFP64-10x10-0.5 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 47 – Sony Corporation