CXB1561Q-Y
s3R-IC for Optical Fiber Cimmunication Receiver
Description
The CXB1561Q-Y achieves the 3R optical-fiber
cimmunication receiver functions (Reshaping,
Regenerating and Retiming) on a single chip using
with a SAW filter.
Features
• 3R-IC with a built-in post-amplifier
(SAW filter system)
• Signal interruption alarm output
• Data shutdown function for signal interruption
• Timing phase can be fine adjusted
• Delay length for edge detector (differentiator) can
be selected
• Single 5V power supply
Absolute Maximum Ratings
• Supply voltage
VCC – VEE –0.3 to +7.0
• Operating case temperature
–55 to +125
TC
• Storage temperatureTstg
–65 to +150
• Output current (surge current)
Io
0 to 50 (100)
• D/D input current
IID
–200 to +400
• SC/SC input current IIC
–100 to +400
• S1/S2 input voltage VIS
VCC to VEE + 1.2
Recommended Operating Conditions
• Supply voltage
VCC – VEE 5.0 ± 0.5
• Operating case temperature
TC
–40 to +85
32 pin QFP (Ceramic)
Structure
Bipolar silicon monolithic IC
Applications
• SONET: 622.08Mbps, 155.52Mbps
• Fiber channel: 531.25Mbps, 265.625Mbp
• Clock multiplication: X2, X4
V
°C
°C
mA
µA
µA
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93615B6Z
CXB1561Q-Y
25
D
26
D
27
CAP1
28
CA
CA
VCCDA
Q
Q
VCCDI
VCCAL
24
23
22
21
20
19
18
17
Limit Amp
15 SC
29
S1
30
S2
31
VEEDB
D-FF
14 VEEAL
13 SQ
Post
Amp
CAP1
16 SC
Delay
Differential
VEEA
VEEDA
Block Diagram
delay2
delay1
12 SQ
VEEDB
ALARM
peak hold
11 VCCDB
10 VEEDB
peak hold
9 SD
UP
DOWN
5
6
7
8
SD
4
VEE
3
CAP3
2
CAP2
1
VEED
32
VccD
VCCA
–2–
CXB1561Q-Y
Pin Description
Typical pin voltage
Pin
No.
Symbol
1
VccD
0V
Positive power supply
pin for digital block.
2
VEED
–5V
Negative power supply
pin for digital block.
DC
Equivalent circuit
AC
Description
VCCA
1k
3
UP
–1.3V
100
100
3
200
4
200
4
DOWN
–1.3V
VEEA
0.8mA 0.8mA
5
6
VCCA
5
CAP2
–1.8V
80
10p
10p
80
6
CAP3
–1.8V
5µA
5µA
VEEA
20µA
7
8
VEE
–5V
VCCD
8
9
–0.9V
to
–1.7V
SD
Capacitance connection
pins for alarm block peak
hold circuit.
(Each pin incorporates a
capacitance of
approximately 10pF.)
CAP2 pin: Peak hold
capacitance connection
pin for the post-amplifier
signal output.
CAP3 pin: Peak hold
capacitance connection
pin for the alarm level
setting block.
Negative power supply pin.
–0.9V
to
–1.7V
SD
Resistor connection pins
for alarm level setting.
UP pin: When the
resistance connection to
this pin is increased, the
alarm level becomes
higher.
DOWN pin: When the
resistance connected to
this pin is increased, the
alarm level becomes
lower.
Alarm output pins.
Terminate these pins in
510Ω at VEE.
9
VEED
10
VEEDB
–5V
Negative power supply
pin for differential circuit.
11
VCCDB
0V
Positive power supply pin
for differential circuit.
–3–
CXB1561Q-Y
Pin
No.
12
Symbol
Typical pin voltage
DC
Equivalent circuit
AC
VCCDB
–0.9V
to
–1.7V
SQ
Description
13
13
14
–0.9V
to
–1.7V
SQ
VEEAL
Differential output pins.
12
510
510
VEED
VEEDB
Negative power supply
pin for limiter amplifier.
–5V
VCCAL
15
SC
–1.3V
–0.9V
to
–1.7V
200
16
15
200
1k
50
1k
100p
16
SC
–1.3V
–0.9V
to
–1.7V
Limiter amplifier input
pins. Ensure that these
inputs are AC-coupled.
50
0.4mA
0.4mA
VEEAL
17
VccAL
0V
Positive power supply pin
for limiter amplifier.
18
VccDI
0V
Positive power supply pin
for internal digital circuit.
VCCDA
19
–0.9V
to
–1.7V
Q
19
20
21
Q
VccDA
20
–0.9V
to
–1.7V
Data signal output pins.
Terminate these pins in
50Ω at VTT = –2V.
VEEDA
Positive power supply pin
for output circuit.
0V
–4–
CXB1561Q-Y
Pin
No.
Symbol
Typical pin voltage
DC
AC
—
–0.9V
to
–1.7V
Equivalent circuit
Description
VCCDA
22
CA
Clock signal output pins.
Terminate these pins in
50Ω at VTT = –2V
22
23
CA
—
–0.9V
to
–1.7V
23
VEEDA
24
VEEDA
–5V
Negative power supply
pin for output circuit.
25
VEEA
–5V
Negative power supply
pin for analog block.
26
D
27
28
D
–1.3V
–1.3V
–0.9V
to
–1.7V
–0.9V
to
–1.7V
VCCAL
Post-amplifier input pins.
Ensure that these inputs
are AC-coupled.
200
26
27
10k100p 200
200
1k
CAP1
10k
1k
0.8mA
29
200
VEEA
0.8mA
CAP1
28
29
Capacitance connection
pins to determine the
high cut-off frequency for
post-amplifier feedback.
VCCD
20k
30
S1
–2.0V
30
200
50k
0.1mA
Delay switchover input pin
for delay block.
∆T = T (S1: High) –
T (S1: open Low)
= 134ps (typ. target)
VEED
VCCD
20k
31
S2
–2.0V
31
200
50k
0.1mA
Pulse width switchover
input pin for differential
circuit.
S2: open low For 622Mbps
S2: High For 155Mbps
VEED
32
VccA
Positive power supply pin
for analog block.
0V
–5–
CXB1561Q-Y
Electrical Characteristics
• DC characteristics
Item
(Vcc = 0V, VEE = –5V ± 10%, Tc = –40 to 85°C)
Symbol
Supply current
IEE
CA/CA, Q/Q
High output voltage
VOH-Vcc
CA/CA, Q/Q
Low output voltage
VOL-Vcc
SD/SD
High output voltage
VOHa-Vcc
SD/SD
Low output voltage
VOLa-Vcc
S1/S2 High input voltage
Conditions
Min.
Typ.
Max.
Unit
–157
–110
–74
mA
Termination: Rt = 50Ω, VTT = –2V∗1
–1.03
–0.88
Termination: Rt = 50Ω, VTT = –2V
–1.15
–0.88
Termination: Rt = 50Ω, VTT = –2V∗1
–1.81
–1.62
Termination: Rt = 50Ω, VTT = –2V
Termination: Rt = 510Ω, to VEE∗1
–1.86
–1.60
–1.08
–0.82
Termination: Rt = 510Ω, to VEE
–1.20
–0.83
Termination: Rt = 510Ω, to VEE∗1
–1.90
–1.57
Termination: Rt = 510Ω, to VEE
–1.95
–1.55
VIH-Vcc
–1.17
0
S1/S2 Low input voltage
VIL-Vcc
–3.00
–1.47
S1/S2 High input current
IIH
S1/S2 Low input current
IIL
150
–90
V
µA
∗1 VEE = –5V, Tc = 0 to 85°C
• AC characteristics
Item
Data rate
D/D input resistance
(Vcc = 0V, VEE = –5V ± 10%, VTT = –2V, Tc = –40 to 85°C)
Symbol
Conditions
Min.
Typ.
Da
S2: open low
414.72
622.08
Db
S2: High
155.52
311.04
750
1000
RINM
D/D input identification max. voltage VmaxM
For single-end input, DC cut-off
Post Amp Gain
GP
Max.
Unit
Mbps
1250
Ω
1000
mVp-p
Internal signal: 400mV
45
dB
τd1
S2: open low
525
760
1075
τd2
S2: High
1050
1625
2150
SQ output amplitude
VoB
Output, DC cut-off, 50Ω load
480
670
850
SQ rise time
TrB
200
300
420
200
300
400
37.5
50
62.5
SQ output pulse width
50Ω load, 20% to 80%
SQ fall time
TfB
SC/SC input resistance
RinL
SC/SC input identification max
voltage
VinL
For single-end input, DC cut-off
Limit Amp Gain
GL
Internal signal: 400mV
Phase margin for the flip-flop block
∆θ
320
340
Q/Q rise time
TrQ
200
440
650
Q/Q fall time
TfQ
200
410
650
150
245
350
50Ω load, 20% to 80%
mV
ps
Ω
1000
mVp-p
30
dB
deg
CA/CA rise time
TrC
CA/CA fall time
TfC
120
215
350
CA/CA output duty cycle
Du
45
50
55
–6–
ps
ps
%
CXB1561Q-Y
Item
Symbol
Identification maximum voltage
amplitude of alarm level
VmaxA
Hysteresis width
∆P
SD/SD response assert time
Tas
SD/SD response deassert time
Tdas
Conditions
Min.
D·single-phase input
conversion
∗2
Typ.
Max.
30
mVp-p
2
Low → High∗2
High → Low∗2
Unit
12
6
100
2.5
100
∗2 CAP2/CAP3 pin capacitance 470pF, V (UP pin) – V (DOWN pin) = 10mV, D input voltage = 130mVp-p
Electrical Characteristics Measurement Circuit
For DC Characteristics
VTT
50
50
V
50
V
23
24
22
50
21
V
V
19
20
18
51
17
C6
Limit Amp
25
16
C4
VD RD C1
15
26
C3
Delay
VSC
VEEDB
D-FF
27
14
28
Post
Amp
C2
Differential
V
delay2
29
delay1
VS1
A
V
12
V
VEEDB 11
30
VS2
A
13
ALARM
peak hold
31
10
peak hold
V
9
32
510
1
2
4
3
6
5
7
8
510
A
VEE
C7
VUP
VDOWN
–7–
C8
V
dB
µs
CXB1561Q-Y
For AC Characteristics
Oscilloscope
50Ω input
Z0 = 50
Z0 = 50
Z0 = 50
Z0 = 50
Z0 = 50
23
24
22
21
20
19
18
Z0 = 50
17
100pF
Limit Amp
25
16
100pF
VD 470pF
15
26
Delay
VSC
470pF
VEEDB 14
D-FF
27
1000pF
0.033µF
Post
Amp
Differential
13
28
delay2
29
delay1
VS1
A
VEEDB 11
30
ALARM
peak hold
VS2
A
1000pF
12
31
10
peak hold
9
32
VCC
VEE
510
1
2
4
3
5
6
7
8
510
VUP
VDOWN
470pF 470pF
–8–
Oscilloscope
High impedance input
CXB1561Q-Y
Application Circuit
VTT
51
51
51
51
9
8
23
24
21
22
19
20
18
51
17
C6
Limit Amp
25
16
C4
VD RD C1
15
5
Delay
1
4
VEED
B
D-FF
27
RD C3
14
1000pF 51
6
SAW
26
13
Post
Amp
29
Differential
28
C2
delay2
2
delay1
30
ALARM
peak hold
31
51
12
3
1000pF
VEED 11
B
10
peak hold
7
32
1
2
4
3
6
5
9
7
8
10
510
510
A
VEE
R5
R6
C7
C8
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–9–
– 10 –
Post-amplifier output
Differentiator output (SQ)
SAW output (SC)
Limiter amplifier output
Delay block output
Shutdown signal
Data output (Q)
Clock output (CA)
Alarm output (SD)
2
3
4
5
6
7
8
9
10
Low level
Signal interruption
Q
—
Fixed at High level
SD
Low level
High level
Tsa
Only the data (Q. Q), not clock, is shut down for signal interruption.
High level
SD
td
Signal input
Optical signal input status
Alarm Block Logic
Input (D)
1
Alarm level set up by R5/R6
Timing Chart
Sectional waveforms of the Application circuit
Tdas
CXB1561Q-Y
CXB1561Q-Y
Description of Operation
1. Overall operations
The structure of optical-fiber communication receiver system is shown in Fig. 1. The CXB1561Q-Y performs
the 3R operations indicated below.
• Photodiode .........Converts a data optical signal to a current signal.
• Pre Amp..............Converts a data current signal to a voltage signal (however, the voltage level is feeble).
• 3R .......................1) Amplifies a feeble data voltage signal (Reshaping).
2) Outputs a data signal in sync with a clock signal (Retiming).
3) Outputs both data and clock signals as ECL level signals (Regenerating).
Optical signal Vcc
Pre Amp
Current signal
3R
Data signal
Voltage signal
Clock signal
Fig. 1. Optical fiber communication receiver system clock
The signal flow of the CXB1561Q-Y, including the SAW filter, is as shown in Fig. 2. First, the feeble signal
output of the pre-amplifier enters the post-amplifier and is amplified to an IC internal logic level. The amplified
signal is then divided into the clock and data sides shown below. The clock side derives a clock signal from a
data signal. First, the post-amplifier signal enters the differentiator, which generates a pulse output having an
uniform width at the signal rise and fall times. This output pulse enters the SAW filter, which generates
resonance at regular intervals and outputs a SIN wave having a resonance frequency. This signal output then
enters the limiter amplifier and is amplified to an IC internal logic level. This amplified signal is used as the DFF block clock signal. In the data side, on the other hand, the post-amplifier signal enters the delay section,
where the signal is delayed to accomplish data/clock synchronization at the D-FF block. The signals separated
into the clock and data sides are therefore synchronized with each other at the D-FF block and output to the
outside.
Clock side
Differentiator
Feeble signal
(from pre-amplifier)
SAW
Post-amplifier
Limit Amplifier
Data output
D-FF
Clock signal
Delay
Data side
Fig. 2. Signal flow
– 11 –
CXB1561Q-Y
2. Delay length selection for edge detector (differentiator) (S2 pin operations)
The larger the resonance frequency (SAW filter) component in the input signal, the greater the SAW filter
output. Therefore, the CXB1561Q-Y is designed to offer differing differentiator pulse widths in the 622.08Mbps
and 155.52Mbps of the SONET. The pulse width varies as follows according to the S2 pin input.
S2: open Low
S2: High
→ For 622.08Mbps, 531.25Mbps
→ For 155.52Mbps, 265.625Mbps
3. Timing phase fine adjustment (S1 pin operations)
As explained under overall operations, the data signal delay is adjusted by the delay block to synchronize the
clock and data signals at the D-FF block. However, as the clock signal is output to the outside when it passes
through the SAW filter, the clock delay varies with the SAW filter type and on-board wiring length. To
compensate for such a clock external delay variations more or less, the delay provided by the data delay
section can be varied by switching S1 pin input. The delay change ∆T is set up as follows.
∆T = T (S1: open Low) – T (S1: High) = 134ps (design target value)
The above indicates that the delay provided by the data delay block is ∆T greater when S1 is open Low than
when S1 is High.
4. Alarm output and data shutdown functions
When the input signal level is lower than the alarm setting level, the CXB1561Q-Y generates an alarm signal
and forcibly places the data output on a High level. For alarm level identification, a comparator having a
hysteresis function is used to prevent misoperations of alarm output. The hysteresis width is designed so that
the gain is always maintained constant (design target value: 6dB) without regard to the alarm setting level.
The alarm level setting is determined by the voltage difference between Pins 3 (UP) and 4 (DOWN).
Therefore, a desired voltage should be generated between the UP and DOWN pins and that the UP pin
voltage is higher than the DOWN pin voltage.
– 12 –
CXB1561Q-Y
Notes of Operation
1. Post-amplifier block
In the post-amplifier block, the DC bias is automatically fed back by capacitors C1 and C2 as shown in Fig. 3.
So, input with the DC cut-off. External capacitor C1 and IC internal resistor R1 determine the low input cut-off
frequency f2 for post-amplifier, and external capacitor C2 and IC internal resistor R2 determine the high cut-off
frequency f1 for DC bias feedback. Since peaking characteristics may occur in the lower frequency of the
amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the
occurrence of peaking characteristics. The R1 and R2 target values and C1 and C2 typical values are as
indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 27 to capacitor
C3 that has the same capacitance as capacitor C1.
As this circuit is designed for mark density 1/2.,it is not recommended to use for mark density substantially
different from 1/2.
R1 (internal) → 1kΩ
f2 → 340kHz
C1 (external) → 470pF
R2 (internal) → 10kΩ
f1 → 480Hz
C2 (external) → 0.033uF
26
C1
To IC interior
27
C3
R1
R1
6
R2
5
R2
C2
Fig. 3.
Gain
Feedback gain frequency
response characteristic
f1
f2
Frequency
Fig. 4.
– 13 –
Amplifier gain frequency
response characteristic
CXB1561Q-Y
2. Limiter amplifier block
In the limiter amplifier block, the DC bias is automatically fed back by capacitor C4 and IC internal capacitor C5
as shown in Fig. 5. So, input with the DC cut-off. As is the case with the post-amplifier, external capacitor C4
and IC internal resistor R3 determine the low input cut-off frequency f2 of limiter amplifier. Further, IC internal
capacitor C5 and IC internal resistor R4 determine the high cut-off frequency f1 for DC bias feedback. Since
peaking characteristics may occur in the lower frequency of the amplifier gain characteristics depending on the
f1/f2 combination, set the C4 value so as to avoid the occurrence of peaking characteristics. The R3, R4, and
C5 target values and C4 typical value are as indicated below. When a single-ended input is used, provide AC
grounding by connecting Pin 16 to capacitor C6 that has the same capacitance as capacitor C4.
R3 (internal) → 50Ω
f2 → 32MHz
C4 (external) → 100pF
R4 (internal) → 1kΩ
f1 → 1.6MHz
C5 (internal) → 100pF
R4
C5
R4
R3
R3
16
C6
To IC interior
15
C4
Fig. 5.
– 14 –
CXB1561Q-Y
3. Alarm block
As shown in Fig. 6, the alarm block requires alarm level setting external resistors R5 and R6 and peak hold
capacitors C7 and C8. When the resistance value provided for resistor R5 is increased, the alarm setting level
rises. When the resistance value provided for resistor R6 is increased, the alarm setting level lowers. However,
the voltage of Pin 3 should be higher than the voltage of Pin 4. For the alarm level setting, see Fig. 7. In the
relationship between the alarm setting level and hysteresis width, the hysteresis width maintains a constant
gain (design target value: 6dB) as shown in Fig. 8. External capacitors C7 and C8 are used for input signal and
alarm level peak hold capacitance. The C7 and C8 capacitance values should be set so as to obtain desired
assert time and deassert time settings for the alarm signal. The additional resistances R10 and R11 make
deassert time smaller. The R5, R6, C7, and C8 typical values are as indicated below. (A capacitance of
approximately 10pF is built in Pins 5 and 6 respectively.)
R5 → 5k + αΩ
R6 → 5kΩ
C7, 8 → 470pF
From
MAIN
AMP
peak hold
SD
SD
peak hold
10p
10p
VccA
3
VccA
5
4
R5
R6
VEE
VEE
6
C7
R10
Vcc VEE
C8
R11
Vcc VEE
Fig. 6.
16
VAS
14
R8
100
R9
100
IC interior
4
3
IC exterior
RU
RD
VAS, VDAS (mVp-p)
12
VccA
The values of R7, R8,
and R9 are typical
R7
1k
VDAS
10
8
6
5k
4
VEE
VEE
2
0
5.0
5.2
5.4
RU (kΩ)
Fig. 7.
– 15 –
5.6
SD output
CXB1561Q-Y
High
level
VDAS → Deassert level
VAS → Assert level
Low
level
VDAS
VAS
Small
Great
3dB
3dB
Alarm setting
input level
Hysteresis
Input electric signal amplitude
Fig. 8.
4. SAW peripheral board design
In the signal flow from the differentiator through the SAW filter to the limiter amplifier, the signal is output to the
outside at the SAW filter. To assure proper timing in the IC, therefore, the board wiring length must be
appropriately designed. For the data and clock timing adjustment at the D-FF in the IC, the Typ. state position
must conform to Fig. 9 because the D-FF phase margin is the greatest when the clock is positioned at the
center of data. Further, the Min. state must comply with the D-FF setup time, and the Max. state must conform
to the D-FF hold time. Since the clock signal occurs at regular intervals, synchronization must be accomplished
at least at a certain integer multiple of the clock period. The above timing setup is derived from the equation
below. The board wiring must therefore be designed to satisfy the equation.
– 16 –
CXB1561Q-Y
T = T (SAW filter delay time) + T (wiring delay time)
{+ T (delay time for the IC which amplifies the SAW filter output when it is feeble)}
(1)
(2)
(3)
Typical value
Construction shown in Fig. 10-a): T(typ.) = (n + 3/4) ∗ Tsaw – Tsdc (typ.)
Construction shown in Fig. 10-b): T(typ.) = (n + 1/4) ∗ Tsaw – Tsdc (typ.)
Minimum value
T (min.) > T (typ.) + Tsff – 1/2 ∗ Tsaw + (Tsdc (typ.) – Tsdc (min.))
Maximum value
T (max.) < T (typ.) – Thff + 1/2 ∗ Tsaw + (Tsdc (typ.) – Tsdc (max.))
IC exterior
IC interior
Clock side
2
SAW
Differentiator
Limiter Amplifier
From Post-amplifier
D-FF
Delay
1
Data side
Data minimum pulse width TW
1
D-FF section data signal
Tw/2
Tsff
D-FF section clock signal
Min.
Typ.
Max.
Fig. 9. D-FF timing
16
15
15
SAW
16
SAW
2
Thff
13
13
VEE
VEE
12
IC interior
12
IC exterior
IC interior
Fig. 10-a)
IC exterior
Fig. 10-b)
– 17 –
CXB1561Q-Y
For the constants in the equation on the preceding page, see the table below.
n = integer (0,1,2, · · ·)
Tsaw = SAW resonance frequency cycle
622.08Mbps → Tsdc = Tsdc1
155.52Mbps → Tsdc = Tsdc2
S2 pin: open Low → T'sdc = Tsdc
S2 pin: High
→ T'sdc = Tsdc – ∆T
(Vcc = 0V, VEE = –5V ± 10%, Tc = 0 to 85°C)
Item
Symbol
Min.
Typ.
Max.
622.08Mbps
Tsdc1
613
747
929
155.52Mbps
Tsdc2
822
1050
1549
Variable delay time
∆T
100
134
163
D-FF setup time
Tsff
70
D-FF hold time
Thff
100
Time difference
for timing
Unit
ps
When, for instance, the standard board wiring length is calculated for a data rate of 622Mbps, the following
result is obtained.
Tsaw = 1607.5ps
Assuming the absolute phase of SAW filter = –10deg;
Board wiring delay time → 5.85ps/mm
Construction → Fig. 10-a)
n=0
Under the above conditions, the following results.
T (typ.) = (n+3/4) ∗ Tsaw – Tsdc (typ.) = (0 + 3/4) ∗ 1607.5 – 747 = 458.6ps
T wiring length (typ.) = T (typ.) – TSAW filter = 458.6 – 1607.5 ∗ (10/360) = 413.9ps
Wiring length (typ.) = T wiring length (typ)/(board wiring delay time) = 413.9/5.85 = 70.8mm
5. Order of power ON
The CXB1561Q-Y has a number of power supplies. Note that the IC may break down if the following powerON order is not observed (no problem occurs when all the power supplies are turned ON simultaneously).
(1) When all Vcc power supplies are turned ON first
(The VCCA, VCCAL, VCCD, VCCDA, and VCCDB may be turned in any order.)
Turn ON the VEE power supplies in any order.
(2) When all VEE power supplies are turned ON first
(The VEE, VEEA, VEEAL, VEED, VEEDA, and VEEDB may be turned in any order.)
Turn ON the VCCAL, VCCDA, and VccDB (in any order) → the VCCD → VCCA.
– 18 –
CXB1561Q-Y
6. Differential Output Waveform
The DC cut-off capacitance is connected between the differential output block and SAW filter as shown in
Fig. 11 so that the waveforms are varied according to the ratio of the High level and Low level for the output
waveform as shown in Fig. 12. So, note that the waveforms are different for SQ and SQ.
Differential output block
B1
A1
12
SAW
1000pF
50Ω
50Ω
13
A2
1000pF
B2
VEE
Fig. 11.
A1
A2
B1
B2
The High level for the SQ output pulse close to 50%
A1
A2
B1
The High level for the SQ output pulse close to 25%
Fig. 12.
– 19 –
B2
CXB1561Q-Y
7. Evaluation Board
Saw peripheral board design is important for system performance. Fig.13 shows Evaluation board for
622.08Mbps and the characteristics of the test circuit (Fig.14) is shown in Fig.15 to 18.
front
back
VTT
VEE
VCC
SD
SD
D
D
Q
Q
CA
CA
Fig. 13. Evaluation board pattern
Error Det
Clock
Data
Clock
CXB1561Q-Y
Evaluation
Board
PPG
Data
Z = 50Ω
D
Q
Z = 50Ω
Q
51Ω
PPG: Pulse Pattern Generator
Vtt
CA
Z = 50Ω
CA
51Ω
Vcc = +2V, Vee = –3V, Vtt = GND
Vtt
Oscilloscope
Fig. 14. Measurement Circut
– 20 –
CXB1561Q-Y
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A
A
A
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A
A
A
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A
A
A
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A
A
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A
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A
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A
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A
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A A A
10-4
VEE = –5.0V
Tc = 27°C
DIN = 622.08Mbps
10-5
pattern: PRBS 223 – 1
10-6
Err Ratio
10-7
10-8
10-9
10-10
10-11
3
3.5
4
4.5
5
DIN (mVp-p)
Fig. 15. Error rate vs. Input signal (mark density 1/2, pattern 2N23-1, Tc = 27°C)
AA
A
AA
A
A
A
A
A
A
AA
A
A
A
A
AA
A
A
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AAA
A
A
A
A
AA
A
A
A
A
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A
A
AA
A
A
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A
A
A
A
A
AA
A
A
A
A
AA
A
A
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AAA
A
A
A
A
AA
A
A
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A
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A
A
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A
A
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AA
A
A
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50
Tr
Tf
40
Jitter (ps)
30
20
10
0
1
10
100
1000
DIN (mVp-p)
Fig. 16. Clock jitter vs. Input signal (mark density 1/2, pattern 2N23-1, Tc = 27°C)
– 21 –
CXB1561Q-Y
Fig. 17. jitter transfer (mark density 1/2, pattern 2N23-1, input voltage = 6mVp-p, Tc = 27°C)
Fig. 18. jitter tolerance (mark density 1/2, pattern 2N23-1, input voltage = 6mVp-p, Tc = 27°C)
– 22 –
CXB1561Q-Y
Unit: mm
32PIN QFP (CERAMIC)
14.73 ± 0.3
4.92 MAX
0.15 ± 0
.05
17
24
25
16
32
9
10.63 MAX
1
0.76
1.016
0.48 ± 0.1
0° to 10°
PACKAGE STRUCTURE
SONY CODE
QFP-32C-L01
EIAJ CODE
XQFP023-G-0000-A
JEDEC CODE
PACKAGE MATERIAL
CERAMIC
LEAD TREATMENT
TIN PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
– 23 –
(0.825)
8
0.635 ± 0.125
Package Outline