CXB1577Q Post-Amplifier for Optical Fiber Communication Receiver Description The CXB1577Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is equipped with the signal detection function, which is used to enable TTL/ECL outputs. Also, the output disable function performs the output shutdown. 3.3V/5.0V can be used for the supply voltage. 40 pin QFP (Plastic) Features • Output disable function (TTL input) • Signal detection function (TTL/ECL output) • Supply voltage supports both 3.3V/5.0V Applications • SONET/SDH: • Fibre Channel: : • Gigabit-Ethernet: 622.08Mbps 531.25Mbps 1.062Gbps 1.25Gbps Recommended Operating Conditions • Supply voltage • Termination voltage (for data) • Termination voltage (for alarm 1,alarm 2) • Termination resistance (for data) • Termination resistance (for alarm 1) • Termination resistance (for alarm 2) • Operating temperature VCC – VEE VCC – VTD VTA RTD RTA1 RTA2 Ta — VCC – VEE Tstg Vdif Vi IOQ/SD-ECL IOH SD-TTL IOL SD-TTL — Absolute maximum Ratings • Supply voltage • Storage temperature • Input voltage difference VD – VD • SW input voltage • ECL output current • TTL output current (High level) • TTL output current (Low level) –0.3 to +7 –65 to +150 0 to +2 VEE to VCC –30 to 0 –20 to 0 0 to 20 V °C V V mA mA mA 3.3 ± 0.2/5 ± 0.25 1.8 to 2.2 VEE 46 to 56 240 to 300 460 to 560 –40 to +85 V V V Ω Ω Ω °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96Z24-PS CXB1577Q N.C. VEE4 VC3 CAP3 CAP2 VEE2 VEEI DN UP N.C. Block Diagram and Pin Configuration 30 29 28 27 26 25 24 23 22 21 VCC4 31 20 VCC2 VC1 32 19 ∆V VEE1 18 D SD-TTL 33 peak hold peak hold 17 DB SD-ECL 35 16 CAP1 SDB-ECL 36 15 CAP1B Q 37 14 N.C. QB 38 13 VC0 VCC3 39 12 VCC1 SDB-TTL 34 N.C. 40 VCC2 7 8 9 10 VEE1 SW 6 VEE2 ODIS 5 N.C. 4 N.C. 3 N.C. 2 VC2 1 VEE3 11 TM –2– CXB1577Q Pin Description Pin No. Symbol Typical pin voltage DC 1 VEE3 Equivalent circuit Description AC –3.3V / –5V Negative power supply for ECL output buffer. VCC2 10k 0V (Open) 2 ODIS or VREF 2 300 10k –3.3V / –5V Controls the output shutdown function. High voltage when open; the Q output is fixed to Low. Low voltage when connected to VEE; the D input results in the Q output with ECL level. TTL level is also available. VEE2 VCC2 0V Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 40mVp-p. Low voltage when connected to VEE; the amplitude becomes 20mVp-p. 60k (Open) 3 SW or 3 40k –3.3V / –5V VEE2 4 VCC2 Positive power supply for digital block. 0V VCC2 6k 5 VC2 Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE. 5 0V /–1.7V 2k (Open) VEE2 6 7 N.C. No connected. 8 9 VEE2 –3.3V / –5V Negative power supply for digital block. 10 VEE1 –3.3V / –5V Negative power supply for analog block. 11 TM –1.8V / –3.5V 10 11 Chip temperature monitor. VEE1 –3– CXB1577Q Pin No. Symbol Typical pin voltage DC 12 VCC1 Equivalent circuit Description AC Positive power supply for analog block. 0V VCC3 6k 13 VC0 Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE. 13 0V /–1.7V (Open) 2k VEE3 14 N.C. 15 CAP1B No connected. VCC1 16 17 CAP1 DB –0.9V to –1.3V –1.7V 7.5k 18 200 16 100p 17 15 1k 7.5k 200 1k Pins 15 and 16 connect a capacitor which determines the cut-off frequency for DC feedback block. Pins 17 and 18 are input pins for limiting amplifier block. Input the signal with AC coupled. 18 D –0.9V to –1.3V –1.7V 19 VEE1 –3.3V /–5V Negative power supply for analog block. 20 VCC2 0V Positive power supply for digital block. 21 N.C. 22 UP 23 DN VEE1 No connected. VCC2 986 140.9 140.9 Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEE. 22 100 23 100 SW VCS 24 VEEI SW –3.3V /–5V VEE2 24 25 VEE2 Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 22 and 23) as alarm setting level by connecting this pin to VEE. Negative power supply for digital block. –3.3V /–5V –4– CXB1577Q Pin No. Symbol Typical pin voltage DC Equivalent circuit Description AC 26 VCC2 80 10p 26 CAP2 –1.8V 200 5µA VEE2 27 VCC2 80 10p 27 CAP3 –1.8V Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to Vcc each. CAP2 pin connects a peak hold capacitor for alarm level setting block. CAP3 pin connects a peak hold capacitor for limiting amplifier signal. 200 5µA VEE2 VCC3 6k 0V 28 VC3 Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE. 28 /–1.7V 2k (Open) VEE3 29 VEE4 30 N.C. 31 VCC4 Negative power supply for TTL output buffer. –3.3V /–5V No connected. Positive power supply for TTL output buffer. 0V VCC3 6k 0V 32 VC1 –1.7V Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE. 32 2k (Open) VEE3 –5– CXB1577Q Pin No. Symbol Typical pin voltage DC Equivalent circuit Description AC VCC4 33 SD-TTL VEE or VEE + 3V Alarm signal TTL level output. 33 40k VEE4 VCC4 34 SDB-TTL VEE or VEE + 3V Alarm signal TTL level output. 34 40k VEE4 35 SD-ECL –0.9V or –1.7V VCC3 35 36 36 SDB-ECL –0.9V or –1.7V VEE3 –6– Alarm signal ECL level output. Terminate this pin in 510Ω to VEE at VEE = 5V; in 270Ω to VEE at VEE = 3.3V. CXB1577Q Pin No. Symbol Typical pin voltage DC 37 Equivalent circuit AC –0.9V or –1.7V Q Description VCC3 37 Data signal output. Terminates this pin in 50Ω to VTT = Vcc–2V. 38 38 –0.9V or –1.7V QB 39 VCC3 40 N.C. VEE3 Positive power supply for ECL output buffer. 0V No connected. –7– CXB1577Q Electrical Characteristics DC Characteristics VCC = GND, VEE = –5V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = open, or VCC = GND, VEE = –3.3V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = GND Item Symbol Supply current IEE Q/QB High output voltage VOH Q/QB Low output voltage VOL SD-ECL/SDB-ECL High output voltage VOH-E SD-ECL/SDB-ECL Low output voltage VOL-E Conditions Min. Typ. Max. Unit –74 –51 –34 mA 50Ω to VTT Ta = 0 to +85°C –1100 –860 –1860 –1620 When Vcc – VEE = 5.0V, 510Ω to VEE; when Vcc – VEE = 3.3V, 270Ω to VEE Ta = 0 to +85°C –1100 –860 –1890 –1650 IOH = –0.4mA, SD-TTL/SDB-TTL High output voltage 1 VOH-T1 VCC – VEE = 3.3V, Ta = 0 to +85°C VEE + 2.2 IOH = –0.4mA, SD-TTL/SDB-TTL High output voltage 2 VOH-T2 VCC – VEE = 5V, Ta = 0 to +85°C VEE + 2.4 V SD-TTL/SDB-TTL Low output voltage VOL-T IOL = 2mA Ta = 0 to +85°C SW High input voltage VIHSW at SW pin Open: High VCC – 0.5 SW Low input voltage VILSW SW High input current IIHSW SW Low input current IILSW ODIS High input voltage VIHOD ODIS Low input voltage VILOD ODIS High input current IIHOD ODIS Low input current IILOD –400 D/DB input resistance Rin 765 VEE + 0.5 VCC VEE VEE + 0.5 10 –100 at ODIS pin Open: High VEE + 2.0 VCC + 0.5 VEE VEE + 0.8 20 –8– mV 1020 1275 µA V µA Ω CXB1577Q AC Characteristics VCC = GND, VEE = –5V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = open, or VCC = GND, VEE = –3.3V ± 5%, Ta = –40 to +85°C, VC0 to VC3 = GND Item Maximum input voltage amplitude Symbol Vmax Conditions single-ended input Amplifier gain (excluding the output buffer) GL Identification maximum voltage amplitude of alarm level VmaxA1 SW pad: Low, single-ended input Min. Typ. Max. 1600 mVp-p 52 dB 20 mVp-p SW pad: Open High, VmaxA2 single-ended input 40 ∆P1 SW pin: Low, at default alarm level 3 ∆P2 SW pin: Open High, at default alarm level 3 6 7 Alarm setting level for default Vdef UP/DOWN pin: open, VEEI = VEE, Differential voltage input 7.0 8.4 9.7 Q/QB rise time TrQ 230 350 Q/QB fall time TfQ 230 350 SD-TTL/SDB-TTL rise time TrSDT SD-TTL/SDB-TTL fall time TfSDT SD-ECL/SDB-ECL rise time TrSDE SD-ECL/SDB-ECL fall time TfSDE Propagation delay time TPD SD response assert time Tas SD response deassert time SD/SDB hysteresis width Unit 6 7 dB 20% to 80% 50Ω to VTT mV ps 10 VEE + 0.8V to VEE + 2.0V CL = 10pF 10 20% to 80% When Vcc – VEE = 5.0V, 510Ω to VEE, when Vcc – VEE = 3.3V, 270Ω to VEE 1.6 ns 1.6 0.4 1.9 ∗1 0 100 Tdas ∗2 2.3 100 SD response assert time for alarm level default Tasd ∗3 0 100 SD response deassert time for alarm level default Tdasd ∗4 2.3 100 µs ∗1 VUP – VDOWN = 100mV, Vin = 100mVp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI to VEE. ∗2 VUP – VDOWN = 100mV, Vin = 1Vp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI to VEE. ∗3 Vin = 50mVp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE. ∗4 Vin = 1Vp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE. –9– CXB1577Q DC Electrical Characteristics Measurement Circuit 30 28 29 26 25 24 UP DN VEEI VEE2 CAP2 27 N.C. C3 CAP3 VC3 VEE4 N.C. C3 23 22 21 VCC2 VCC4 31 20 VEE1 VC1 32 19 ∆V C1 VD D SD-TTL 18 33 peak hold SDB-TTL C1 DB peak hold 34 17 SD-ECL CAP1 35 16 36 15 37 14 38 13 39 12 N.C. 40 11 510 CAP1B SDB-ECL 270 510 C2 Q 270 N.C. 51 VC0 QB 51 VCC3 VCC1 9 10 VEE1 8 VEE2 7 N.C. SW VSW 6 N.C. ODIS VODIS 5 4 3 VC2 2 VCC2 1 N.C. TM VEE3 VTT –2V VEE –5.0V/–3.3V ∗ When VEE = –5.0V: VC0 to VC3 = open When VEE = –3.3V: VC0 to VC3 = Vcc – 10 – CXB1577Q AC Electrical Characteristics Measurement Circuit 30 29 470p 28 27 25 24 UP DN VEEI VEE2 26 N.C. REX1 CAP2 CAP3 VC3 VEE4 N.C. 470p 23 22 21 VCC4 VCC2 31 20 VEE1 VC1 32 19 ∆V SD-TTL D 0.047µF DB 0.047µF 18 33 peak hold Oscilloscope Hi-Z input SDB-TTL peak hold 34 17 SD-ECL CAP1 35 16 36 15 37 14 N.C. 38 13 39 12 N.C. 40 11 Z0 = 50 SDB-ECL Z0 = 50 Oscilloscope 50Ω input CAP1B Q Z0 = 50 VC0 QB Z0 = 50 VCC3 VCC1 VCC +2V VEE –3V/ –1.3V ∗ When VEE = –3.0V: VC0 to VC3 = open When VEE = –1.3V: VC0 to VC3 = Vcc – 11 – 8 N.C. 9 10 VEE1 7 VEE2 6 N.C. VCC2 SW 5 4 3 VC2 2 ODIS VEE3 1 N.C. TM 1µF CXB1577Q Application Circuit VEE 30 29 27 28 26 25 UP DN 24 N.C. REX1 VEEI VEE2 470p CAP2 CAP3 VC3 VEE4 N.C. 470p 23 22 21 VCC4 31 20 VCC2 VC1 32 19 ∆V SD-TTL DB 0.047µF Signal Generator 51Ω VIN peak hold SDB-TTL peak hold 34 17 SD-ECL ECL Output 0.047µF 51Ω 18 33 TTL Output VEE1 VTT D 51Ω 35 16 36 15 37 14 N.C. 38 13 VC0 VCC3 39 12 VCC1 SDB-ECL 51Ω VTT CAP1 51Ω VTT CAP1B 1µF Q ECL Output 51Ω VTT –2.0V QB N.C. 40 TTL Input 6 7 8 9 10 N.C. VEE2 VEE1 5 N.C. 4 N.C. SW 3 VC2 2 ODIS VEE3 1 VCC2 11 TM VEE ∗ When VEE = –3.3V: VC0 to VC3 = Vcc When VEE = –5.0V: VC0 to VC3 = open Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – CXB1577Q Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 17 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1kΩ R2 (internal): 7.5kΩ f2: 3.4kHz f1: 21Hz C1 (external): 0.047µF C2 (external): 1µF 18 D C1 To IC interior 17 C1 R1 R1 R2 16 C2 R2 15 Fig. 1 Gain Feedback frequency response f1 f2 Frequency Fig. 2 – 13 – Amplifier frequency response CXB1577Q 2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 22 and 23 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect Pin 24 to VEE and leave Pins 22 and 23 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 24 to VEE and set a desired alarm level using the external resistors REX1, REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 22 and 23 or connect REX3 between Pin 23 and Vcc when less alarm level is desired to be set than its default value; connect REX2 between Pin 22 and Vcc when more alarm level is desired to be set than its default value. However, the Pin 22 voltage must be higher than that of Pin 23. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. REX1: 100Ω (when the alarm level is set to 4mV for input conversion.) REX2: 8kΩ (when the alarm level is set to 10mV for input conversion.) REX3: 4kΩ (when the alarm level is set to 4mV for input conversion.) C3: 470pF The table below shows the alarm logic. The table below shows the output disable function logic. SD SD Optical signal input state Q Q Signal input High level Low level ODIS: Open High Fixed Low Fixed High Signal interruption Low level High level ODIS: Low Data Data Optical signal input state Ra1, Ra2A and Ra2B values are typical values. From limiting amplifier Peak Hold SD-TTL SDB-TTL VCCA Ra1 986 Ra2A 141 SD-ECL SDB-ECL Peak Hold Ra2B 141 VCCA VCS VCCA 10p 10p ∆V 3 23 22 24 26 27 IC interior 24 REX2 VEEI 23 DN UP 22 IC exterior VEE Fig. 3 – 14 – REX1 VCC C3 C3 REX3 VCC VCC VCC CXB1577Q VDAS → Deassert level VAS → Assert level Peak hold output voltage SD output High level Low level VDAS VAS Small Large 3dB 3dB Alarm setting input level Hysteresis SW → Low SW → Open High 0 Input electrical signal amplitude Fig. 4 20 40 Input voltage [mVp-p] Fig. 5 Data input (D) Hysteresis width Alarm setting level Data output (Q) Alarm output (SD) Assert time Deassert time Fig. 6 – 15 – CXB1577Q Example of Representative Characteristics 1. Q/QB output waveform VCC = GND VEE = –3.3V VTT = –2V Ta = 27°C D = 622Mbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 7 VCC = GND VEE = –3.3V VTT = –2V Ta = 27°C D = 622Mbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 8 VCC = GND VEE = –3.3V VTT = –2V Ta = 27°C D = 1.25Gbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 9 – 16 – CXB1577Q VCC = GND VEE = –3.3V VTT = –2V Ta = 27°C D = 1.25Gbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Q QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 10 2. Bit error rate Bit error rate vs. Data input level 10 –3 10 622Mbps 1.0Gbps 1.25Gbps –4 Bit error rate 10 –5 VCC = GND VEE = –3.3V VTT = –2V Ta = 27°C Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT 10 –6 10 –7 10 –8 10 –9 10 –10 1.5 2 2.5 3 3.5 Data input level [mVp-p] Alarm level vs. REX1 Alarm level temperature 6.0 9 SW = H SW = L 5.0 Alarm level [mV] Alarm level [mV] SW = H SW = L 5.5 7 6 5 4 4.5 4.0 3.5 3.0 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 3 2 102 4.5 Fig. 11 3. Alarm level 8 4 fin = 100Mbps VCC – VEE = 3.3V Up-Down = 200Ω (REX1) 2.5 2.0 103 UP-DOWN (REX1) [Ω] 104 Fig. 12 –40 –20 0 40 20 Ta [°C] Fig. 13 – 17 – 60 80 CXB1577Q Alarm level supply voltage Alarm level vs. REX2 6.0 16 SW = H SW = L 5.5 14 Alarm level [mV] 5.0 Alarm level [mV] fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 15 4.5 4.0 3.5 13 12 11 10 3.0 fin = 100Mbps Ta = 27°C Up-Down = 200Ω (REX1) 2.5 2.0 3.0 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 SW = H SW = L 9 8 103 3.6 104 VCC-UP (REX2) [Ω] Fig. 14 Fig. 15 Alarm level temperature Alarm level supply voltage 15.0 15.0 SW = H SW = L 14.5 SW = H SW = L 14.5 14.0 Alarm level [mV] 14.0 Alarm level [mV] 105 13.5 13.0 12.5 12.0 13.5 12.0 12.5 12.0 fin = 100Mbps VCC – VEE = 3.3V VCC-UP = 5kΩ (REX2) 11.5 11.0 –40 –20 0 40 20 Ta [°C] 60 fin = 100Mbps Ta = 27°C VCC-UP = 5kΩ (REX2) 11.5 11.0 3.0 80 3.1 3.2 3.4 3.3 VCC – VEE [V] Fig. 16 3.5 3.6 Fig. 17 Alarm level vs. REX3 Alarm level temperature 6.0 9 SW = H SW = L 8 fin = 100Mbps VCC – VEE = 3.3V VCC-Down = 3kΩ (REX3) SW = H SW = L 5.5 Alarm level [mV] Alarm level [mV] 5.0 7 6 5 3 103 4.0 3.5 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 4 4.5 3.0 2.5 104 VCC-DOWN (REX3) [Ω] –40 105 Fig. 18 –20 0 20 Ta [°C] Fig. 19 – 18 – 40 60 80 CXB1577Q Alarm level supply voltage Hysteresis width vs. Alarm level 6.0 8.0 5.0 6.0 4.5 5.0 4.0 4.0 3.5 3.0 3.0 2.0 2.5 1.0 2.0 3.0 3.3 3.2 3.4 VCC – VEE [V] 3.1 3.5 SW = H SW = L 7.0 HYS [dB] Alarm level [mV] fin = 100Mbps Ta = 27°C VCC-Down = 3kΩ (REX3) SW = H SW = L 5.5 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C 0.0 2.0 3.6 4.0 6.0 10.0 8.0 Alarm level [mV] Fig. 20 14.0 Fig. 21 Hysteresis width temperature Hyteresis width supply voltage 8.0 8.0 SW = H SW = L 7.0 SW = H SW = L 7.0 6.0 6.0 5.0 5.0 HYS [dB] HYS [dB] 12.0 4.0 4.0 3.0 3.0 2.0 2.0 fin = 100Mbps VCC – VEE = 3.3V Up, Down = Open VEEI = VEE 1.0 1.0 0.0 –40 –20 0 20 40 Ta [°C] 60 fin = 100Mbps Ta = 27°C Up, Down = Open VEEI = VEE 0.0 3.0 80 3.1 3.3 3.2 3.4 VCC – VEE [V] Fig. 22 3.5 3.6 Fig. 23 Alarm level vs. Data rate Hysteresis width vs. Data rate 16 12 SW = H SW = L 14 SW = H SW = L 10 8 HYS [dB] Alarm level [mV] 12 10 8 6 4 6 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 4 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 2 2 0 0 200 400 600 800 fin [Mbps] 1000 1200 1400 0 Fig. 24 200 400 600 800 fin [Mbps] Fig. 25 – 19 – 1000 1200 1400 CXB1577Q 4. DC voltage SD-ECL "H" level supply voltage SD-ECL "H" level temperature –860 –860 Ta = 27°C SD-ECL SDB-ECL –900 –900 –940 –940 "H" level [mV] "H" level [mV] SD-ECL SDB-ECL –980 –1020 –1060 –1060 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 –1100 –50 3.6 0 50 Fig. 27 SD-ECL "L" level supply voltage SD-ECL "L" level temperature Ta = 27°C –1680 SD-ECL SDB-ECL VCC – VEE = 3.3V –1720 "L" level [mV] –1720 –1760 –1800 –1840 –1760 –1800 –1840 –1880 –50 –1880 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 0 50 Fig. 29 SD-TTL "H" level supply voltage SD-TTL "H" level temperature 3.4 3.4 Ta = 27°C VCC – VEE = 3.3V 3.2 3.0 3.0 "H" level [V] 3.2 2.8 2.8 2.6 2.6 2.4 2.4 2.2 3.0 100 Ta [°C] Fig. 28 "H" level [V] 100 Ta [°C] Fig. 26 SD-ECL SDB-ECL –1680 "L" level [mV] –980 –1020 –1100 VCC – VEE = 3.3V 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 2.2 –50 3.6 0 50 Ta [°C] Fig. 30 Fig. 31 – 20 – 100 CXB1577Q SD-TTL "L" level supply voltage SD-TTL "L" level temperature 400 400 Ta = 27°C VCC – VEE = 3.3V 350 "L" level [mV] "L" level [mV] 350 300 250 300 250 200 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 200 –50 3.6 0 Fig. 32 Q "H" level supply voltage Q "H" level temperature –860 Ta = 27°C Q-H QB-H Q-H QB-H –900 –900 –940 –940 "H" level [mV] "H" level [mV] 100 Fig. 33 –860 –980 –1020 –1060 –1060 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 –1100 –50 3.6 VCC – VEE = 3.3V –980 –1020 –1100 0 50 100 Ta [°C] Fig. 34 Fig. 35 Q "L" level supply voltage Q "L" level temperature –1620 –1620 Ta = 27°C Q-L QB-L Q-L QB-L –1660 –1660 –1700 –1700 "L" level [mV] "L" level [mV] 50 Ta [°C] –1740 –1740 –1780 –1780 –1820 –1820 –1860 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 –1860 –50 3.6 VCC – VEE = 3.3V 0 50 Ta [°C] Fig. 36 Fig. 37 – 21 – 100 CXB1577Q Package Outline Unit: mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 ± 0.12 M 0.5 ± 0.2 (8.0) + 0.15 0.1 – 0.1 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 22 –