CXB1596AR 10-bit Transceiver Description The CXB1596AR is a transceiver IC with a built-in PLL for Fibre Channel and Gigabit Ethernet. For a receiver 1.0625/1.25Gbaud serial data is received and output as 10-bit parallel data; for a transmitter 10-bit parallel data is received and output as 1.0625/1.25Gbaud serial data. Features • Transmitter and receiver in a single chip • ANSI X3T11 Fibre Channel compatible (FC_0) at 1.0625Gbaud • IEEE802.3z Gigabit Ethernet compatible at 1.25Gbaud • Conforms to 10-bit interface specification • TTL/ECL compatible • PLL for clock generation and clock & data recovery • Byte synchronization detector (positive character of Comma) • Frequency autolock function • Low power consumption (620mW typ.) • 64-pin plastic LQFP package (10mm × 10mm) Applications • 1.0625Gbaud Fibre Channel Interface • 1.25Gbaud Gigabit Ethernet Interface • Work Station/Server/HDD Interface • High-speed data communications • Switched networks 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VCC –0.3 to +4 • TTL DC input voltage VI_T –0.5 to +5.5 • ECL DC input voltage VI_E VCC – 2 to VCC • ECL differential input voltage amplitude VIS_E –4 to +4 • TTL high level output current IOH_T –20 to 0 • TTL low level output current IOL_T 0 to 20 • ECL output current IO_E –30 to 0 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 880 V V V V mA mA mA °C mW Recommended Operating Conditions • Supply voltage VCC 3.135 to 3.465 V (3.3V Typ.) • PECL AC coupling differential output load resistance RL (to VCC –2V) 50 Ω (to VEE) 150 Ω • Ambient temperature Ta 0 to +70 °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99212-PS CXB1596AR Block Diagram 10 TX0 to 9 REFCLK D Q 106.25MHz (125MHz) TXPLL Parallel to Serial CONV. 10 SDOUT SDOUT∗ LCLK 106.25MHz (125MHz) TCLK 1.0625GHz (1.25GHz) LPF_TX0 LPF_TX1 Transmitter block Receiver block LBEN I SDIN SDIN∗ RDATA O RXPLL 10 LCKREF∗ LPF_RX0 RX0 to 9 Serial to Parallel CONV. and BYTE SYNC RCLK 1.0625GHz (1.25GHz) BYTSYNC LPF_RX1 BYTSYNCEN Frequencies in parentheses are for Gigabit Ethernet, other frequencies are for Fibre Channel. DIV (1/10) RBC1 RBC0 RBC (1/2) FCLK 106.25MHz (125MHz) VEET RX9 RX8 RX7 VCCT RX6 RX5 RX4 RX3 VCCT RX2 RX1 VEET RX0 BYTSYNC LPF_RX0 Pin Configuration (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LPF_RX1 49 32 VEET VCCP_RX 50 31 RBC0 VEEP_RX 51 SDIN∗ 52 30 RBC1 VCCE 53 28 VCCG 29 VCCT VCCG 55 27 LCKREF∗ 26 TEST∗ SDIN 54 VEEG 56 25 VEEG VCCG 57 24 BYTSYNCEN VEEG 58 23 VCCG VCCG 59 22 REFCLK VCCE 60 21 VEEG SDOUT∗ 61 20 VCCG SDOUT 62 19 LBEN RDSELN TX3 TX4 TX5 9 10 11 12 13 14 15 16 –2– LPF_TX0 8 VEEP_TX 7 TX9 6 VEET 5 TX8 4 TX7 3 TX6 2 VCCG 1 TX2 17 LPF_TX1 TX1 VEEE 64 TX0 18 VCCP_TX VEET VCCE 63 CXB1596AR Pin Description Pin No. Symbol 1, 14, 32, 33, VEET 46 Type Typical pin voltage Power supply 0V Equivalent circuit Description Negative power supply for TTL output. VCCG 2 to 4, 6 to 9, TX0 to TX9 11 to 13 TTL input TTL level Parallel data inputs. Input data is converted to serial data in order from TX0. TTL_IN VEEG VEET 5 RDSELN 10, 20, 23, 28, VCCG 55, 57, 59 15 VEEP_TX Test input TTL High level Test input. Set to TTL high level or leave open. Power supply 3.3V Positive power supply for internal circuits. Power supply 0V Negative power supply for TXPLL. VCCP 16 17 LPF_TX0 LPF_TX1 External part connection pin LPF0 LPF1 External loop filter connection for TX. — VEEP 18 VCCP_TX Power supply Positive power supply for TXPLL. 3.3V VCCG 19 LBEN TTL input TTL level Loop back enable. When high, the TX serial output is serially input to the RX side inside the IC. When low, both transmit and receive are enabled. TTL_IN VEEG VEET –3– CXB1596AR Pin No. Symbol 21, 25, VEEG 56, 58 Type Typical pin voltage Power supply 0V Equivalent circuit Description Negative power supply for internal circuits. VCCG 22 REFCLK TTL input TTL level External reference clock input. TTL_IN VEEG VEET VCCG 24 BYTSYNCEN TTL input TTL level Byte synchronization enable. When high, the Comma detection circuit is enabled to perform byte synchronization. TTL_IN VEEG VEET VCCG 26 TEST∗ Test input TTL High level Test input. Set to TTL high level or leave open. TTL_IN VEEG VEET VCCG 27 LCKREF∗ TTL input TTL level TTL_IN VEEG VEET 29, 37, VCCT 42 Power supply Forced reference clock lock. When low, the PLL is forcibly locked to the external reference clock (REFCLK). Normally set to high: autolock mode. Positive power supply for TTL output. 3.3V –4– CXB1596AR Pin No. Symbol Type Typical pin voltage Equivalent circuit Description VCCT 30 31 RBC1 RBC0 TTL output TTL level TTL_OUT Receive side byte clocks recovered from the serial data. RBC1 and RBC0 output clocks which are 180 degrees out of phase. VEET VCCT 34 to 36, RX0 to 38 to 41, RX9 43 to 45 TTL output TTL level TTL_OUT Parallel data outputs. Serial data is converted to parallel data in order starting from RX0 and ending with RX9. VEET VCCT 47 BYTSYNC TTL output TTL level TTL_OUT Byte synchronization detection signal. This pin outputs high for a 1 byte period when the Comma signal is detected. VEET VCCP 48 49 LPF_RX0 LPF_RX1 External part connection pin LPF0 LPF1 External loop filter connection for RX. — VEEP 50 VCCP_RX Power supply 3.3V 51 VEEP_RX Power supply 0V Positive power supply for RXPLL. Negative power supply for RXPLL. –5– CXB1596AR Pin No. Symbol Type Typical pin voltage Equivalent circuit Description VCCE 52 54 SDIN∗ SDIN VCCG INP ECL input PECL level VCCE –1.3V Serial data inputs. INN VEEG VEEE 53, 60, VCCE 63 Power supply Positive power supply for ECL output. 3.3V VCCE 61 62 SDOUT∗ SDOUT ECL output PECL level OUTP Serial data outputs. OUTN VEEE 64 VEEE Power supply Negative power supply for ECL output. 0V –6– CXB1596AR Electrical Characteristics DC Characteristics Item (VCC = 3.135 to 3.465V, Ta = 0 to 70°C) Symbol Conditions Min. Typ. Max. Unit TTL high level input voltage VIH_T 2 5.5 V TTL low level input voltage VIL_T 0 0.8 V TTL high level input current IIH_T VIN = VCC 20 µA TTL low level input current IIL_T VIN = 0V TTL high level output voltage VOH_T IOH = –0.4mA TTL low level output voltage VOL_T IOL = 2mA ECL high level input voltage VIH_E ECL low level input voltage VIL_E ECL differential input voltage amplitude VIS_E∗1 ECL differential output voltage amplitude –400 µA 2.2 V 0.5 V VCC – 1.17 VCC – 0.88 V VCC – 1.81 VCC – 1.48 V AC coupling input, peak-to-peak 200 2000 mV VOS_E∗2 Peak-to-peak 1200 2000 mV Current consumption ICC Output pins open 188 255 mA Power consumption PD Output pins open 620 870 mW ∗1 ECL differential input voltage amplitude VCC VIS_E = | VI1 | + | VI2 | SDIN VIH_E VI1 VIL_E VI2 SDIN∗ VEE = GND ∗2 ECL differential output voltage amplitude VCC VOS_E = | Vo1 | + | Vo2 | SDOUT VOH_E Vo1 VOL_E Vo2 SDOUT∗ VEE = GND –7– CXB1596AR AC Characteristics Item (VCC = 3.135 to 3.465V, Ta = 0 to 70°C) Symbol Conditions Min. Typ. Max. Unit TX TTL input rise time Tir_Tx 0.8 to 2.0V 0.7 4.8 ns TX TTL input fall time Tif_Tx 2.0 to 0.8V 0.7 4.8 ns REFCLK input rise time Tir_REF 0.8 to 2.0V 0.7 2.4 ns REFCLK input fall time Tif_REF 2.0 to 0.8V 0.7 2.4 ns TTL output rise time Tor_T 0.8 to 2.0V, CL = 10pF 3.5 ns TTL output fall time Tof_T 2.0 to 0.8V, CL = 10pF 3.5 ns ECL output rise time Tor_E 20 to 80%, CL = 2pF 400 ps ECL output fall time Tof_E 80 to 20%, CL = 2pF 400 ps Operating transfer rate Br 1.052 1.262 Gbps REFCLK frequency F_REF 105.2 126.2 MHz REFCLK frequency tolerance Ftol_REF –100 TXPLL/RXPLL frequency pull-in time Tfa RXPLL bit synchronization time 100 ppm Loop damping capacitance = 0.01µF 500 µs Tbs Loop damping capacitance = 0.01µF 2500 bit TX serial output jitter Random RJ TX output data K28.7 6.2 TX serial output jitter Deterministic DJ TX output data ±K28.5 24 –8– ps 60 ps CXB1596AR Description of Operation 1. Transmitter block The input 10-bit parallel data (TX0 to TX9) is latched by the external reference clock (REFCLK), converted from parallel to serial (Parallel to Serial CONV.), and output as serial data (SDOUT/SDOUT∗). The TXPLL multiplies REFCLK by 10 times to generate TCLK, and then frequency-divides this by 1/10 to generate LCLK. Parallel/serial conversion uses these TCLK and LCLK as the clocks. [See P10 "Timing Charts 1) Transmitter block".] 2. Receiver block The RXPLL recovers RCLK from the input serial data (SDIN/SDIN∗), uses this RCLK to retime the serial data and outputs it as RDATA. The DIV (divider) frequency-divides RCLK by 1/10 to generate FCLK, and RDATA is converted from serial to parallel (Serial to Parallel CONV.) using these two clocks (RCLK and FCLK). At the same time the byte synchronization signal (Comma detect word) is detected during Serial to Parallel CONV., and 10-bit parallel data (RX0 to RX9) and the sync signal (BYTSYNC) are output. FCLK is initialized and the 10-bit parallel data is byte synchronized using this sync signal. RBC differentially outputs the clocks (RBC1 and RBC0) obtained by 1/20 frequency-dividing TCLK for loading the 10-bit parallel data. [See P11 "Timing Charts 2) Receiver block".] a. Input serial data amplitude detection The serial data input block has the amplitude detection and amplitude control circuits. When the differential amplitude of the input signal is 100mVp-p or less, the input signal is cut and the output is fixed to high level. All parallel output data (RX0 to RX9) are high. b. Frequency autolock If LCKREF∗ is set high while recovering RCLK with the RXPLL, autolock mode results. In autolock mode, RCLK is locked to 10 times REFCLK when the input serial data is no signal, or to the clock component of the serial data when serial data is input. When LCKREF∗ is set low, RCLK is forcibly locked to 10 times REFCLK. c. Byte synchronization When BYTSYNCEN is set high, Comma data within the input serial data is detected, and the detection signal and byte synchronized 10-bit parallel data are output. At this time RBC1 and RBC0 are also initialized and output. When BYTSYNCEN is set low, the 10-bit parallel data is output in the arbitrary order and the RBC1 and RBC0 edges also rise at the arbitrary position. d. Differential clock output (RBC1 and RBC0) RBC1 and RBC0 output at the positive phase when byte synchronization is synchronized properly and Comma data is detected one time or more. RBC1 and RBC0 are extended when byte synchronization is asynchronous and Comma data is detected one time. e. Loop back When LBEN is set high, the serial data is looped back internally. Set LBEN low to perform transmit and receive. –9– CXB1596AR Timing Charts 1) Transmitter block (VCC = 3.3V, Ta = 25°C) Symbol Item Min. Conditions Typ. Max. Unit TX setup time Ts_Tx 2.0 ns TX hold time Th_Tx 1.5 ns Latency time TLAT_Tx 1.0625GHz REFCLK input rise time Tir_REF 0.8 to 2.0V 0.7 2.4 ns REFCLK input fall time Tif_REF 2.0 to 0.8V 0.7 2.4 ns TX TTL input rise time Tir_Tx 0.8 to 2.0V 0.7 4.8 ns TX TTL input fall time Tif_Tx 2.0 to 0.8V 0.7 4.8 ns 4.7 Tir_REF ns Tif_REF 2.0V 1.4V REFCLK 0.8V Ts_Tx Th_Tx Tir_Tx Tif_Tx 2.0V DATA N TX0 to TX9 DATA N + 1 0.8V TLAT_Tx SDOUT/∗ 9 TX0 1 2 3 4 5 6 7 8 9 DATA N – 1 TX0 1 2 3 4 5 DATA N – 10 – 6 7 8 9 TX0 CXB1596AR 2) Receiver block (VCC = 3.3V, Ta = 25°C) Symbol Item Min. Conditions Typ. Max. Unit 1.0625GHz 3.0 ns 1.25GHz 2.5 ns 1.0625GHz 1.5 ns 1.25GHz 1.0 ns RX setup time Ts_Rx RX hold time Th_Rx Skew between RBC0 and RBC1 TSK_RBC 1.0625GHz Latency time TLAT_Rx 1.0625GHz TTL output rise time Tor_T 0.8 to 2.0V, CL = 10pF 3.5 ns TTL output fall time Tof_T 2.0 to 0.8V, CL = 10pF 3.5 ns SDIN COMMA1 RX0 to RX9 8.91 9.41 9.91 ns 18.0 COMMA2 VALID DATA N RX0 to RX9 RX0 to RX9 RX0 to RX9 ns RX0 to RX9 RX0 to TLAT_RX TLAT_RX 2.0V HOLD RBC0 1.4V 0.8V Tsk_RBC Tor_T Tof_T 2.0V 1.4V HOLD RBC1 0.8V TS_Rx Th_Rx 2.0V RX0 to RX9 COMMA1 VALID DATA N – 2 COMMA2 VALID DATA N VALID DATA N + 1 0.8V TS_RX Th_RX 2.0V BYTSYNC 0.8V – 11 – CXB1596AR Example of Representative Characteristics Random jitter 6.7ps (RMS) X: 50ps/div Y: 100mV/div 1.0625GHz mode a) TX random jitter (SDOUT) X: 200ps/div Y: 200mV/div 1.0625GHz mode b) TX eye pattern (SDOUT) – 12 – CXB1596AR Electrical Characteristics Measurement Circuit a) TX random jitter (K28.7 fixed) 0 0 1 1 1 1 1 0 0 0 TX0 TX9 Digital oscilloscope SDOUT 106.25MHz REFCLK Device under test 0.01µF SDOUT∗ Pulse pattern generator LPF TX1 TX0 ZO = 50Ω VCC = 3.3V VEE = GND TRIG 150Ω 0.01µF b) TX eye pattern Parallel data 1.0625Gbps random data RX0 to RX9 Digital oscilloscope TX0 to TX9 0.01µF SDIN SDOUT 100Ω Pulse pattern generator Device under test SDIN∗ ZO = 50Ω 106.25MHz REFCLK RX0 LPF TX0 RX1 SDOUT∗ ZO = 50Ω TX1 VCC = 2.0V VEE = –1.3V 0.01µF – 13 – 0.01µF LBEN Low BYTSYNCEN RDSELN TEST∗ LCKREF∗ High TRIG CXB1596AR Notes on Operation 1. External loop filters Connect 0.01µF capacitors as close to the two sets of external loop filter pins as possible. 16 17 48 0.01µF 49 0.01µF 2. Example of power supply circuit VCC 0.1µF VEE 0.1µF VEE VCC RX9 VEET RX8 RX7 RX6 VCCT RX5 RX4 RX3 RX2 VCCT RX1 RX0 VEET LPF_RX0 VCC BYTSYNC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 LPF_RX1 VEET 32 50 VCCP_RX RBC0 31 51 VEEP_RX 52 SDIN∗ RBC1 30 VCCT 29 53 VCCE 0.1µF VCCG 28 LCKREF∗ 27 TEST∗ 26 54 SDIN 55 VCCG VEE VCC 22µF BYTSYNCEN 24 58 VEEG VCCG 23 59 VCCG REFCLK 22 60 VCCE VEEG 21 61 SDOUT∗ VCCG 20 62 SDOUT LBEN 19 64 VEEE LPF_TX1 17 TX6 5 6 7 8 9 10 11 12 13 14 15 16 VEET TX5 4 TX9 TX4 3 TX8 TX3 2 TX7 RDSELN 1 VCCG TX2 LPF_TX0 VCCP_TX 18 VEEP_TX 63 VCCE TX1 VEE TX0 GND VEEG 25 57 VCCG VEET 3.3V 56 VEEG VCC VEE 0.1µF 22µF is an electrolytic capacitor, and should be located as close to the power supply as possible. 0.1µF are ceramic capacitors, and should be located as close to the IC power supply pins as possible. 3. Serial data I/O VCC = 3.3V VEE = GND VCC = 3.3V VEE = GND 0.01µF 150Ω 0.01µF 150Ω 150Ω ZO = 75Ω – 14 – CXB1596AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 + 0.08 0.18 – 0.03 16 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 15 –