SONY CXB1810FN

CXB1810FN
Post Amplifier for Optical Fiber Communication Receiver
Description
The CXB1810FN achieves 2R optical fiber
communication receiver functions (Reshaping and
Regenerating) on a single chip.
This IC is equipped with a signal detection function,
and outputs at TTL level.
16 pin HSOF (plastic)
Features
• Auto-offset canceler circuit
• Signal interruption alarm output
• Single 3.3V or 5.0V power supply
Applications
SONET/SDH
Absolute Maximum Ratings
• Supply voltage
VCC – VEE
• Input voltage difference
| VD – VDN |
• ECL/TTL output current (Continuous)
(Surge)
• Storage temperature
Tj
–0.3 to +6.0
2.5
50
70
–65 to +150
Recommended Operating Conditions
• Supply voltage
VCC – VEE
3.14 to 5.25
• Termination voltage (for Q/QB)
Vt1
VCC – 1.8 to Vcc – 2.2
• Termination resistance (for Q/QB) Rt
46 to 56
• Operating temperature
Ta
–40 to +85
V
V
mA
mA
°C
V
V
Ω
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99801D26-PS
CXB1810FN
Block Diagram
VEEO
1
VccO
2
16 Vcc
Q
3
15 D
QB
4
14 DB
13 VEE
12 CAP1
SDC
5
SDCB
6
11 CAP1B
10 SW
CAP3
7
9
CAP2
8
Pin Configuration
DOWN 9
8
CAP2
SW 10
7
CAP3
CAP1B 11
6
SDCB
CAP1 12
5
SDC
VEE 13
4
QB
DB 14
3
Q
D 15
2
VCCO
VCC 16
1
VEEO
–2–
DOWN
CXB1810FN
Pin Description
Pin
No.
Typical pin
voltage
(V)
Symbol
DC AC
Equivalent circuit
Description
1
VEEO
0
Ground for data output circuit.
2
VccO
3.3 or
5.0
Positive power supply for data
output circuit.
VCCO
3
4
1.7
to
2.4
or
3.4
to
4.1
Q
QB
3
Data outputs.
4
VEEO
VCC
5
0.2
to
2.9
or
0.2
to
4.7
SDC
Signal detection output (TTL).
The SDC output is driven to low
level while signal interruption is
detected.
5
VEE
VCC
6
0.2
to
2.9
or
0.2
to
4.7
SDCB
Signal detection output (TTL).
The SDCB output is driven to
high level while signal
interruption is detected.
6
VEE
7
8
1.3
to
1.8
or
3.0
to
3.5
CAP3
CAP2
VCC
7
8
1.6 or
3.3
VEE
–3–
Connect a peak hold capacitor
for the signal detection circuit.
470pF (typ.)
CXB1810FN
Pin
No.
Typical pin
Symbol voltage (V)
DC AC
Equivalent circuit
Description
VCC
9
2.4 or
DOWN
4.1
Connect a resistor between this
pin and the VCC pin to decrease
the signal detection level from
the default value.
9
VEE
Switches the maximum
identification voltage amplitude.
This pin is set to 50mVp-p
(single ended) when open or high
level, or to 15mVp-p (single
ended) when low level.
Setting to low level is
recommended when using a
resistor of 510Ω or less between
the VCC and DOWN pins.
VCC
10
SW
10
VEE
VCC
11
12
14
15
Connect an external capacitor
between these pins.
0.022µF (typ.)
CAP1B 2.2 or
3.9
CAP1
15
12
14
11
DB
D
Data inputs.
VEE
13
VEE
0
16
VCC
3.3 or
5.0
Ground.
Positive power supply.
–4–
CXB1810FN
Electrical Characteristics
DC Characteristics
(VCC = 3.14 to 5.25V, Ta = –40 to +85°C, unless otherwise specified)
Item
Symbol
Conditions
Min.
Q/QB high output voltage
Q/QB low output voltage
VOH1
VOL1
51Ω terminated to VCC – 2V
51Ω terminated to VCC – 2V
VCC – 1100
VCC – 1800
Q/QB output amplitude
Vp
51Ω terminated to VCC – 2V
500
IOH = –0.2mA
IOL = 2.1mA
2.4
SDC/SDCB high output voltage VOHT
SDC/SDCB low output voltage VOLT
SW high input voltage
SW low input voltage
VIHT
VILT
Maximum input voltage
amplitude
Vmax
D/DB input resistance
Rin
Supply current
ICC
AC Characteristics
Typ.
Unit
VCC – 650 mV
VCC – 1300 mV
VCC – 0.3
VEE
During single-phase input
Max.
1000
mVp-p
0.5
V
V
VCC
VEE + 0.3
V
V
1000
mVp-p
33
All outputs open
50
69
Ω
40
55
mA
(VCC = 3.14 to 5.25V, Ta = –40 to +85°C, unless otherwise specified)
Item
Symbol
Limiting amplifier gain
GL
Signal detection threshold voltage
Vth
Signal detection hysteresis width
∆P
Signal detection response assert time∗1
Signal detection response deassert time∗1
Tas
Tdas
Q/QB rise time (20 to 80%)
Q/QB fall time (20 to 80%)
TR
TF
Conditions
Min.
Typ.
Max.
45
During single ended input
dB
34
3
6
0
2.3
51Ω terminated to VCC – 2V
51Ω terminated to VCC – 2V
∗1 Data = PN23 – 1 pattern, 100mVp-p single ended, Rd = open, CAP2/CAP3 = 470pF
–5–
Unit
130
110
mVp-p
8
dB
100
100
µs
µs
ps
ps
CXB1810FN
DC Electrical Characteristics Measurement Circuit
2V
1
2
16
3
15
4
14
V
51Ω
51Ω
V
13
V
12
V
5
11
V
V
6
10
470pF
7
9
470pF
8
3.14 to 5.25V
–6–
CXB1810FN
AC Electrical Characteristics Measurement Circuit
50Ω input
Oscilloscope
ZO = 50
ZO = 50
1
2
16
0.01µF
3
15
4
14
0.01µF
13
12
5
11
6
10
7
470pF
9
8
470pF
Hi-Z input
Oscilloscope
2V
–1.14 to –3.25V
–7–
0.022µF
CXB1810FN
Application Circuit
1
51Ω
2
16
3
15
4
14
0.01µF
0.01µF
13
12
5
0.022µF
11
6
10
470pF
7
9
470pF
8
3.3/5.0V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–8–
CXB1810FN
Notes on Operation
1. Limiting amplifier block
The limiting amplifier block is equipped with an auto-offset canceler circuit. When external capacitors C1 and
C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block.
External capacitor C1 and internal resistor R1 determine the input low cut-off frequency f2 as shown in Fig. 2.
Similarly, external capacitor C2 and internal resistor R2 determine the high cut-off frequency for DC feedback.
Since a peak may occur in the low frequency area of the gain characteristics depending on the f1/f2
combination, set the C1 and C2 values so as to avoid the occurrence of this peak. The typical values of R1,
R2, C1 and C2 are indicated below.
Also, when a single ended input is used, provide AC grounding by connecting Pin 14 to a capacitor which has
the same capacitance as capacitor C1.
R1 (internal): 50Ω
R2 (internal): 10kΩ
f2: 318kHz
f1: 723Hz
C1 (external): 0.01µF
C2 (external): 0.022µF
C1
15
To inside the IC
C1
14
R1
R1
12
R2
C2
R2
11
Fig. 1
Amplifier frequency
response
Gain
DC feedback frequency
response
f1
f2
Frequency
Fig. 2
–9–
CXB1810FN
2. Alarm block
In this block, the input signal amplitude is detected and the signal interruption alarm is output when the
amplitude becomes lower than the set alarm level. The alarm level setting can be adjusted by connecting an
external resistor Rd between the DOWN and VCC pins.
Also, this IC can set the maximum identification voltage amplitude to two levels. The maximum identification
voltage amplitude is set to 50mVp-p (single ended) when the SW pin is open or high level, or to 15mVp-p
(single ended) when the SW pin is low level.
Figs. 15 and 16 show the relation of Rd and the alarm assert/deassert level. Setting the SW pin to low level is
recommended when Rd is 510Ω or less.
VDAS → Deassert level
VAS → Assert level
SW → Low
SD output
High level
SW → High
Low level
VDAS
VAS
3dB
15
3dB
50
Input voltage (mVp-p, single phase)
Hysteresis
Fig. 4
Fig. 3
In addition, the SD response deassert time is guaranteed only under the conditions noted in the AC Electrical
Characteristics item, but the response becomes delayed as the input signal amplitude becomes larger. This is
because the input resistor R1 shown in Fig. 1 is small at 50Ω, so the charge accumulated in C2 is relatively
large and the discharge time for this charge accounts for most of the SD response deassert time. The SD
response deassert time can be shortened by using the external circuit shown in Fig. 5 or by shorting the CAP1
and CAP1B pins. However, care should be taken as the auto-offset canceler circuit does not operate in this
case causing the reception sensitivity to deteriorate. Fig. 14 shows the relation between the SD response
deassert time and the electrical input amplitude when using the connection shown in Fig. 5.
C1
15
100Ω
C1
To inside the IC
14
R1
R1
1.5kΩ
12
R2
C2
1.5kΩ
R2
11
Fig. 5
– 10 –
CXB1810FN
3. Substrate layout
The exposed metal portions on the rear surface of the package used for the CXB1810FN are electrically
connected to the silicon substrate. Superior thermal radiation characteristics can be obtained by connecting
the rear surface of the package and these exposed metal portions to the ground surface on the PCB.
Providing lands directly below the package as shown in the figure below and connecting as many thermal vias
as possible to the inner layer ground surface is recommended.
0.4mm
0.25mm
1.45mm
0.75mm
2.0mm
4. Other
• Be careful when handling this IC as its electrostatic discharge strength is weak.
• Be sure to connect all power supply pins (VCCO, VCC) and ground pins (VEEO, VEE) to power supplies or
grounds, respectively. For example, if only VCCO is left open and power is supplied to the other pin, the IC
may malfunction.
– 11 –
CXB1810FN
Example of Representative Characteristics
ICC vs. Supply voltage
ICC vs. Temperature
42.0
41.5
Ta = 40°C
Output pins open
41.0
41.0
40.5
ICC [mA]
40.5
ICC [mA]
VCC = 3.14V/5.25V
Output pins open
41.5
40.0
39.5
40.0
39.5
39.0
38.5
38.0
39.0
VCC = 3.14V
VCC = 5.25V
37.5
38.5
3.0
3.5
4.0
4.5
5.0
37.0
–40
5.5
–20
0
20
40
VCC [V]
Ta [°C]
Fig. 6
Fig. 7
Q/QB output voltage vs. Supply voltage
60
80
100
Q/QB output voltage vs. Temperature
–0.8
–0.6
Q/QB output voltage [V, ref to VCC]
Q/QB output voltage [V, ref to VCC]
VCC = 3.14V/5.25V
–0.9
Ta = 40°C
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
–1.6
3.0
3.5
4.0
4.5
5.0
H level (VCC = 3.14V)
H level (VCC = 5.25V)
L level (VCC = 3.14V)
L level (VCC = 5.25V)
–1.2
–1.4
–1.6
–1.8
–40
–20
0
20
40
60
80
VCC [V]
Ta [°C]
Fig. 8
Fig. 9
Q/QB output voltage amplitude
vs. Supply voltage
Q/QB output voltage amplitude
vs. Temperature
100
0.700
Vp-p, Ta = 40°C
0.695
Q/QB output voltage amplitude [Vp-p]
Q/QB output voltage amplitude [Vp-p]
–1.0
5.5
0.700
0.690
0.685
0.680
0.675
0.670
0.665
0.660
0.655
0.650
–0.8
3.0
3.5
4.0
4.5
5.0
5.5
0.695
VCC = 3.14V/5.25V
0.690
0.685
0.680
0.675
0.670
0.665
0.660
VCC = 3.14V
VCC = 5.25V
0.655
0.650
–40
VCC [V]
–20
0
20
40
Ta [°C]
Fig. 10
Fig. 11
– 12 –
60
80
100
CXB1810FN
SDC/SDCB output voltage vs. Supply voltage
SDC/SDCB output voltage vs. Temperature
6
VCC = 3.14V/5.25V,
IOH = –0.2mA, IOL = +2.1mA
Ta = 40°C,
IOH = –0.2mA, IOL = +2.1mA
5
SDC/SDCB output voltage [V]
SDC/SDCB output voltage [V]
6
4
3
2
1
0
3.0
3.5
4.0
4.5
5.0
3
H level (VCC = 3.14V)
H level (VCC = 5.25V)
L level (VCC = 3.14V)
L level (VCC = 5.25V)
2
0
–40
5.5
150
100
50
0.4
40
Fig. 13
200
0.2
20
Fig. 12
250
0
0
Ta [°C]
Recommended circuit
Fig. 5 connection
300
–20
VCC [V]
350
SD response deassert time [µs]
4
1
Input voltage amplitude
vs. SD response deassert time
0
5
0.6
0.8
1.0
1.2
Input voltage amplitude [mVp-p, single ended]
Fig. 14
– 13 –
60
80
100
CXB1810FN
Rd vs. SD assert/deassert level
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level [mVp-p, single ended]
Rd vs. SD assert/deassert level
60
VCC = 3.3V
SW = H level
50
40
30
20
VAS
VDAS
10
0
0.1
1
10
100
16
12
10
8
6
4
0
100
20
VAS
VDAS
10
4.0
4.5
5.0
5.5
30
20
0
–40
0
20
40
10
5
VAS
VDAS
4.0
4.5
VCC [V]
5.0
60
80
100
SD assert/deassert level vs. Temperature
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level [mVp-p, single ended]
–20
Fig. 18
15
3.5
VAS (VCC = 3.14V)
VDAS (VCC = 3.14V)
VAS (VCC = 5.25V)
VDAS (VCC = 5.25V)
10
SD assert/deassert level vs. Supply voltage
3.0
VCC = 3.14V/5.25V,
DOWN pin open,
SW = H level
40
Fig. 17
Ta = 40°C,
Rd = 2kΩ,
SW = H level
700
50
Ta [°C]
25
600
60
VCC [V]
30
0
500
SD assert/deassert level vs. Temperature
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level [mVp-p, single ended]
30
20
400
Fig. 16
Ta = 40°C,
DOWN pin open,
SW = H level
3.5
300
Fig. 15
50
3.0
200
Rd [Ω]
SD assert/deassert level vs. Supply voltage
0
VAS
VDAS
2
Rd [kΩ]
60
40
VCC = 3.3V
SW = L level
14
5.5
30
25
20
VCC = 3.14V/5.25V,
Rd = 2kΩ,
SW = H level
15
10
VAS (VCC = 3.14V)
VDAS (VCC = 3.14V)
VAS (VCC = 5.25V)
VDAS (VCC = 5.25V)
5
0
–40
–20
0
20
40
Ta [°C]
Fig. 19
Fig. 20
– 14 –
60
80
100
CXB1810FN
SD assert/deassert level vs. Temperature
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level vs. Supply voltage
14
12
Ta = 40°C,
Rd = 510Ω,
SW = L level
10
8
6
4
VAS
VDAS
2
0
3.5
3.0
4.0
4.5
5.5
5.0
14
12
8
6
4
2
0
–40
4
3
2
VAS
VDAS
1
4.0
4.5
VCC [V]
5.0
5.5
80
100
6
5
4
VCC = 3.14V/5.25V,
Rd = 150Ω,
SW = L level
3
2
VAS (VCC = 3.14V)
VDAS (VCC = 3.14V)
VAS (VCC = 5.25V)
VDAS (VCC = 5.25V)
1
0
–40
–20
0
20
40
60
80
100
Ta [°C]
Fig. 24
Input amplitude vs. Bit error rate (VCC = 3.3V)
Input amplitude vs. Bit error rate (VCC = 5.0V)
1.00E-03
1.00E-03
Ta = –40°C
Ta = 0°C
Ta = 40°C
Ta = 85°C
1.00E-04
1.00E-05
1.00E-06
1.00E-07
1.00E-06
1.00E-07
1.00E-08
1.00E-08
1.00E-09
1.00E-09
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Ta = –40°C
Ta = 0°C
Ta = 40°C
Ta = 85°C
1.00E-04
Bit error rate
1.00E-05
Bit error rate
60
7
Fig. 23
1.00E-10
2.0
40
SD assert/deassert level vs. Temperature
SD assert/deassert level [mVp-p, single ended]
SD assert/deassert level [mVp-p, single ended]
20
Fig. 22
Ta = 40°C,
Rd = 150Ω,
SW = L level
3.5
0
Fig. 21
6
3.0
–20
Ta [°C]
SD assert/deassert level vs. Supply voltage
0
VAS (VCC = 3.14V)
VDAS (VCC = 3.14V)
VAS (VCC = 5.25V)
VDAS (VCC = 5.25V)
Ta [°C]
7
5
VCC = 3.14V/5.25V,
Rd = 510Ω,
SW = L level
10
1.00E-10
2.0
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input amplitude [mVp-p, single ended]
Input amplitude [mVp-p, single ended]
Fig. 25
Fig. 26
– 15 –
6.0
CXB1810FN
100mV/div
Q output waveform
VCC = 3.3V, Ta = 40°C
D = 100mVp-p
(single ended)
PN23 pattern
100ps/div
Fig. 27
100mV/div
Q output waveform
VCC = 5.0V, Ta = 40°C
D = 100mVp-p
(single ended)
PN23 pattern
100ps/div
Fig. 28
100mV/div
Q output waveform
VCC = 3.3V, Ta = 40°C
D = 10mVp-p
(single ended)
PN23 pattern
100ps/div
Fig. 29
100mV/div
Q output waveform
VCC = 5.0V, Ta = 40°C
D = 10mVp-p
(single ended)
PN23 pattern
100ps/div
Fig. 30
– 16 –
CXB1810FN
Package Outline
Unit: mm
HSOF 16PIN(PLASTIC)
0.05 S
∗5.6 ± 0.1
0.45 ± 0.15
0.9 ± 0.1
(5.5)
(3.1)
A
(1.5)
(0.7)
(0.5)
3.8 ± 0.1
4.4 ± 0.1
(1.75)
9
16
8
1
0.65
(0.2)
S
(0.2)
(4.4)
0.05 M S A
(0.2)
0.2
+ 0.1
0.32 – 0.03
+ 0.05
0
Solder Plating
B
+ 0.1
0.26 – 0.03
DETAILB
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
HSOF-16P-02
SONY CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.06g
Kokubu & SCT Ass'y
HSOF 16PIN(PLASTIC)
0.05 S
∗5.6 ± 0.1
0.45 ± 0.15
0.9 ± 0.1
(5.5)
(3.1)
A
(1.5)
(0.7)
(0.5)
3.8 ± 0.1
4.4 ± 0.1
(1.75)
9
16
8
1
0.65
(0.2)
S
(0.2)
(4.4)
0.05 M S A
(0.2)
0.2
+ 0.1
0.32 – 0.03
+ 0.05
0
Solder Plating
B
+ 0.1
0.26 – 0.03
DETAILB
NOTE: Dimension “∗” does not include mold protrusion.
HSOF-16P-02
SONY CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.06g
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 17 –
Sony Corporation