CXD1170M 6-bit 40MSPS High Speed D/A Converter For the availability of this product, please contact the sales office. Description The CXD1170M is a 6-bit 40MHz high speed D/A converter. The adoption of a current output system reduces power consumption to 80mW (200Ω load at 2Vp-p output). This IC is suitable for digital TV and graphic display applications. Features • Resolution 6-bit • Max. conversion speed 40MSPS • Non linearity error within ±0.1LSB • Low glitch noise • TTL CMOS compatible input • +5V single power supply • Low power consumption 80mW (200Ω load at 2Vp-p output) 24 pin SOP (Plastic) Structure Silicon gate CMOS IC Function 6-bit 40MHz D/A converter Block Diagram and Pin Configuration NC 1 24 DVDD NC 2 23 DVDD (LSB) D0 3 22 AVDD D1 4 D2 5 DECODER CURRENT CELLS LATCHES D3 6 D4 7 D5 8 IO 20 IO 19 AVDD 18 AVDD DECODER 17 VG 16 VREF BLK 9 CURRENT CELLS (FOR FULL SCALE) DVSS 10 BIAS VOLTAGE GENERATOR VB 11 CLK 12 21 CLOCK GENERATOR 15 IREF 14 AVSS 13 DVSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89X37B6X-PS CXD1170M Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD • Input voltage VIN • Output current IOUT • Storage temperature Tstg 7 VDD to VSS 15 –55 to +150 V V mA °C Recommended Operating Conditions • Supply voltage AVDD, AVSS DVDD, DVSS • Reference input voltage VREF • Clock pulse width Tpw1 Tpw0 • Operating temperature Topr 4.75 to 5.25 4.75 to 5.25 2.0 12.5 (Min) 12.5 (Min) –20 to +75 V V V ns ns °C Pin Description and I/O Pins Equivalent Circuit No. Symbol Equivalent circuit Description DVDD 3 3 to 8 D0 to D5 to Digital input 8 DVSS DVDD 9 BLK Blanking pin No signal at "H" (Output 0V) Output condition at "L" 9 DVSS DVDD DVDD 11 VB Connect a capacitor of about 0.1µF 11 DVSS DVDD 12 CLK Clock pin Moreover all input pins are TTL-CMOS compatible 12 DVSS 10, 13 DVSS Digital GND 14 AVSS Analog GND –2– CXD1170M No. Symbol Equivalent circuit AVDD 15 Description AVDD Connect a resistance 16 times "16R" that of output resistance value "R" IREF 15 AVDD 16 VREF 17 VG AVSS AVDD 16 Set full scale output value 17 AVSS Connect a capacitor of about 0.1µF AVSS 18, 19, 22 AVDD Analog VDD AVDD 20 IO Current output pin Voltage output can be obtained by connecting a resistance 20 AVSS AVDD 21 Inverted current output pin Normally dropped to analog GND 21 IO AVSS 23, 24 DVDD Digital VDD Eleoctrical Characteristics Item (fCLK = 40MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V, Ta = 25°C) Symbol Resolution Measurement conditions Min. n Typ. Max. 6 bit 40 Maximum conversion speed fMAX Unit MSPS Minimum conversion speed fMIN 0.5 Linearity error EL –0.3 0.5 LSB Differential linear error ED –0.1 0.1 LSB Full scale output voltage VFS 1.85 1.95 2.05 V Full scale output current IFS 10 15 mA Offset output voltage VOS 1 mV Power supply current IDD 16 mA 5 µA Digital input current 14.3MHz, at COLOR BAR DATA input 13 MHz 14.5 High level IIH Low level IIL –5 µA 5 ns 10 ns Propagation delay time tS tH tPD Glitch energy GE Setup time Hold time ROUT = 75Ω –3– 10 ns 30 pV-s CXD1170M Maximum conversion speed test circuit 6bit COUNTER with LATCH OSCILLOSCOPE IO 20 3 D0 (LSB) 200 • •• 4 8 D5 AVDD VG 17 9 BLK 0.1µ 0.1µ VREF 16 11 VB CLK 40MHZ SQUARE WAVE 1k 2V AVss 12 CLK IREF 15 3.3k DC characteristics test circuit DVM IO 20 3 D0 (LSB) 200 CONTROLLER • •• 4 8 D5 AVDD VG 17 9 BLK 0.1µ 0.1µ VREF 16 11 VB CLK 40MHZ SQUARE WAVE 1k 2V AVss 12 CLK IREF 15 3.3k Propagation delay time test circuit OSCILLOSCOPE IO 20 3 D0 (LSB) 200 • •• 4 8 D5 AVDD VG 17 CLK 10MHZ SQUARE WAVE FREQUENCY DEMULTIPLIER 9 BLK 0.1µ 0.1µ VREF 16 1k 11 VB AVss 12 CLK IREF 15 3.3k Setup hold time and glitch energy test circuit 6bit COUNTER with LATCH IO 20 3 D0 (LSB) OSCILLOSCOPE 75 • • • 4 8 D5 AVDD VG 17 DELAY CONTROLLER CLK 1MHZ SQUARE WAVE DELAY CONTROLLER 9 BLK 0.1µ 0.1µ VREF 16 11 VB 1k 1V AVss 12 CLK IREF 15 1.2k –4– CXD1170M Operation Timing Chart TPW1 TPW0 CLK AA AAA AA AA AA AAA AA AA AAAAAAAAA tS tH DATA tS tH tS tH tPD D/A OUT 100% 50% tPD tPD 0% Application Circuit DVDD 1 24 2 23 3 22 4 21 5 20 AVDD (LSB) AGND 6bit DIGITAL INPUT D/A OUT 200 6 19 7 18 8 17 9 16 10 15 11 14 12 13 0.1µ 2V 0.1µ 1k 3.3k DGND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. I/O Chart (when full scale output voltage at 2.00V) Input code MSB 1 1 1 1 : 1 0 0 0 : 0 0 0 0 Output voltage LSB 1 1 2.0V 0 0 1.0V 0 0 0V –5– CXD1170M Notes on Operation • How to select the output resistance The CXD1170M is a D/A converter of the current output type. To obtain the output voltage connect the resistance to IO pin. For specifications we have: Output full scale voltage VFS = less than 2.0 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS × R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF × 16R/R'. R is the resistance connected to IO while R' is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • VDD, VSS To reduce noise effects separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of about 0.1µF, as close as possible to the pin. • Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. –6– CXD1170M Output full scale voltage vs. Reference voltage Output resistance vs. Glitch energy 2.0 Glitch energy [pV-s] VFS – Output scale voltage [V] 200 1.0 100 VDD = 5.0V R = 200Ω 16R = 3.3kΩ Ta = 25°C 0 2.0 1.0 100 VREF – Reference voltage [V] Output resistance [Ω] Output full scale voltage [V] Output full scale voltage vs. Ambient temperature 2.0 1.9 VDD = 5.0V VREF = 2.0V R = 200Ω 16R = 3.3kΩ Ta = 25°C 0 –25 0 25 50 75 Ambient temperature [°C] –7– 200 CXD1170M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 + 0.4 1.85 – 0.15 13 6.9 + 0.2 0.1 – 0.05 12 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 ± 0.12 M PACKAGE STRUCTURE SONY CODE SOP-24P-L01 EIAJ CODE ∗SOP024-P-0300-A JEDEC CODE MOLDING COMPOUND EPOXY/PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY / 42ALLOY PACKAGE WEIGHT 0.3g –8–