CXD1268M CCD Vertical Clock Driver Description The CXD1268M is a clock driver for CCD vertical register drive. 20 pin SOP (Plastic) Features • On-chip 4-channel driver. (Binary driver × 2, and trinary driver × 2) • Low output ON resistance provides optimal drive for large load capacity CCD. Applications CCD cameras Structure CMOS Absolute Maximum Ratings (GND = 0V, Ta = 25°C) • Supply voltage VH VL to VL + 25 V ∗ 1 • Supply voltage VM VL to VL + 17 V • Supply voltage VDD GND to GND + 7 V • Supply voltage VL GND – 10 to GND V • Input voltage VI –0.5 to VDD + 0.5 V • Input/output clamp diode current IIC, IOC –10 to +10 mA • Maximum DC load current IODC –3 to +3 mA • Maximum load capacity CL to 30,000 pF/pin • Allowable power dissipation PD to 200 mW • Storage temperature Tstg –60 to +150 °C ∗1 Use VM at less than VDD. Recommended Operating Conditions • Supply voltage VH VM + 6.5 to VM + 15.5 • Supply voltage VL VM – 10.0 to VM – 7.0 • Supply voltage VM 0.0 to 4.0 • Supply voltage VDD 4.75 to 5.25 ∗ 2 • High level input voltage VIH 3.5 to VDD • Low level input voltage VIL∗2 0.0 to 1.0 • Operating temperature Topr –10 to +60 ∗2 VDD = 5V V V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96635-PS CXD1268M Block Diagram XSG1 XV1 9 VDD VM1 VH 6 3 16 SG Input Gate Level Converter Level Converter 8 XSG2 12 SG Input Gate Level Converter Level Converter XV3 13 Trinary Driver 5 Trinary Driver 18 Vφ3 Vφ1 XV2 10 Level Converter Binary Driver 2 Vφ2 XV4 11 Level Converter Binary Driver 19 Vφ4 15 20 1 GND VM2 VL Pin Configuration (Top View) VL 1 20 VM2 Vφ2 2 19 VM1 3 18 Vφ3 NC 4 17 NC Vφ4 Vφ1 5 16 VH VDD 6 15 GND NC 7 14 NC XV1 8 13 XV3 XSG1 9 12 XSG2 XV2 10 11 XV4 –2– CXD1268M Pin Description Pin No. Symbol I/O Description 1 VL — Low level power supply 2 Vφ2 O High-voltage output (2 levels: VM2, VL) 3 VM1 — Middle level power supply for trinary 4 NC 5 Vφ1 O High-voltage output (3 levels: VH, VM1, VL) 6 VDD — Input section power supply 7 NC 8 XV1 I Output control (Vφ1) 9 XSG1 I Output control (Vφ1) 10 XV2 I Output control (Vφ2) 11 XV4 I Output control (Vφ4) 12 XSG2 I Output control (Vφ3) 13 XV3 I Output control (Vφ3) 14 NC 15 GND — GND 16 VH — High level power supply for trinary 17 NC 18 Vφ3 O High-voltage output (3 levels: VH, VM1, VL) 19 Vφ4 O High-voltage output (2 levels: VM2, VL) 20 VM2 — Middle level power supply for binary X: Don’t care Truth Table Input Output XV1, XV3 XSG1, XSG2 XV2, XV4 Vφ1, Vφ3 Vφ2, Vφ4 H L X VL X H H X VL X L L X VH X L H X VM1 X X X L X VM2 X X H X VL –3– CXD1268M Electrical Characteristics 1. DC Characteristics (Unless otherwise specified, VH = 14.5V, VM = 1V, VDD = 5V, GND = 0V, VL = –6V, VIL = GND, VIH = VDD, Ta = –10 to +60°C) Item Symbol Conditions Min. Typ. Max. Unit “H” level output voltage VφH IφH = –1mA VH – 0.1 VH V “M” level output voltage VφM IφM = –1mA VM – 0.1 VM V “L” level output voltage VφL IφL = 1mA VL VL + 0.1 V Input current II 1.0 µA “H” level output ON resistance Ron (H) IφH = –50mA 18 30 Ω “M” level output ON resistance Ron (M) IφM = –50mA 18 30 Ω “L” level output ON resistance Ron (L) IφL = 50mA 18 30 Ω Static current consumption IDD + IH + IM 10–4 100 µA Typ. Max. Unit 2. AC Characteristics Item Symbol Conditions Min. Propagation delay time L → M, M → L tPLH, tPHL Waveform diagram (1), no load 100 200 ns Propagation delay time M → H, H → M tPLH, tPHL Waveform diagram (2), no load 200 400 ns Rise time L → M Fall time M → L tTLH, tTHL Refer to waveform diagram (1), output load circuit diagram 200 300 ns Rise time M → H Fall time H → M tTLH, tTHL Refer to waveform diagram (2), output load circuit diagram 200 300 ns 6.0 10.0 mA 0.02 0.2 mA 3.8 5.0 mA Idyn (IDD + IH + IM + IL) Operating current consumption IDD IH + IM Refer to input pulse timing diagram, output load circuit diagram –5.0 IL –4– –3.8 mA CXD1268M Waveform Diagram (1) tr tf VDD 90% input XV1 to XV4 tr = tf = 20ns 50% 10% GND tPHL tPLH VφM 90% output Vφ1 to Vφ4 50% 10% VφL tTHL tTLH Waveform Diagram (2) tr input XSG1, XSG2 tf VDD 90% tr = tf = 20ns 50% 10% GND tPHL tPLH VφH 90% output Vφ1, Vφ3 50% 10% VφM tTLH tTHL Output Load Circuit Diagram 1600pF 2000pF 1000pF Vφ1 Vφ4 3000pF 3000pF 1000pF Vφ2 Vφ3 2000pF 1600pF –5– CXD1268M Input Pulse Timing Diagram 63.5µs 127µs 2µs XV1 XV2 XV3 XV4 XSG1, XSG2 5µs 15.7ms Application Circuit CCD image sensor Vφ1 Vφ2 –7.5V 5V timing generator 1 VL VM2 20 2 Vφ2 Vφ4 19 Vφ4 3 VM1 Vφ3 18 Vφ3 4 NC NC 17 5 Vφ1 VH 16 6 VDD GND 15 7 NC XV1 8 XV1 XSG 9 XSG1 XV2 10 XV2 15V NC 14 XV3 13 XSG2 12 XV4 11 XV4 XV3 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Notes on Operation 1. When applying power, be sure to apply VH before VDD and VM. 2. XSG1 (Pin 9) and XSG2 (Pin 12) can be input separately, although they are also common input. –6– CXD1268M Package Outline Unit: mm 20PIN SOP (PLASTIC) 1.8MAX 13.0MAX 11 20 1.1 1.55 1 + 0.1 0.4 – 0.05 0.6 ± 0.2 7.7 ± 0.3 5.6 0.1 ± 0.1 10 0.12 M 1.27 0.78MAX + 0.1 0.2 – 0.05 PACKAGE STRUCTURE SONY CODE EIAJ CODE PACKAGE MATERIAL EPOXY RESIN SOP-20P-L071 LEAD TREATMENT SOLDER PLATING SOP020-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE –7–