SONY CXD1961Q

CXD1961Q
DVB-S Front-end IC (QPSK demodulator + FEC)
Preliminary
For the availability of this product, please contact the sales office.
Description
The CXD1961Q is a single chip DVB Satellite
Broadcasting Front-end IC, including dual ADC for
analog I/O inputs, QPSK demodulator, Viterbi
decoder, de-interleaver, Reed-Solomon decoder
and Energy Dispersal descrambler.
It is suitable for use in a DVB Integrated Receiver
Decoder.
Features
• Dual 6 bit A/D converters
• QPSK demodulator
Multi-symbol rate operation
Nyquist roll off filter (α = 0.35)
Clock recovery circuit
Carrier recovery circuit
AGC control circuit
• Viterbi decoder
Constraint length K =7
Punctured rate R = 1/2 –7/8
Truncation length 144
Punctured rate search function
BER monitor
• De-interleaver
Packet synchronization
Convolutional de-interleaver
• Reed-Solomon decoder (204, 188)
• Energy dispersal descrambler
• CPU interface
l2C bus interface/8 bit CPU bus
TTL interface level (5V input capability)
• JTAG(IEEE std 1149.1–1990) test mode
• Package : QFP-100pin
• Single +3.3V Power Supply
• Symbol rate max:32MSPS min:TBD
• Power consumption TBD
• 0.4um CMOS Technology
100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25°C, GND=0V)
• Supply voltage
VDD
–0.5 to 4.6
V
• Input voltage
VIN
–0.5 to VDD+0.5 V
• Output voltage
VOUT –0.5 to VDD+0.5 V
• I/O voltage
VI/O –0.5 to VDD+0.5 V
V
• CPU I/F pin
VCPUIF –0.5 to 5.5
• Operating temperature Topr
0 to +75
°C
• Storage temperature Tstg
–55 to +150 °C
DC Recommended Operating Conditions
(Ta=0°C to 75°C, GND=0 V)
• Supply voltage
VDD
3.15 to 3.45
V
• Input Hi-level
VIH VDD–0.7 to VDD+0.5 V
• Input Lo-level
VIL
0.3 to VDD +0.2 V
Applications
• DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
PE96417-TE
CXD1961Q
Block Diagram
100 99 98
97 96 95
94 93 92
91 90 89
88 87
86 85 84
83 82 81
80
1
Analog I/Q
2
Sampling
Clock
3
2ch ADC
79
78
VCO
77
4
PLL
5
76
75
6
74
7
QPSK
Demodulator
Digital
Filter
8
73
9
72
10
71
11
70
12
69
NCO
Viterbi Decoder
13
68
14
67
15
66
16
65
64
17
JTAG
Oscillator
De-interleaver
18
19
63
62
61
20
60
21
Reed-Solomon
Decoder
22
59
CPU I/F
23
l2C
bus
24
58
57
56
25
26
55
Energy Dispersal
27
54
28
53
29
8bit CPU bus
Decoded
data & clock
30
31 32
33 34 35
52
51
36 37 38 39
40 41 42
43 44 45 46
47 48 49 50
Typical Application Block Diagram
LNB
QPSK+FEC
I/Q
Detector
Amp
SAW
Data
LPF
SONY
CXD1961Q
LPF
VCO
PLL
90°
Reference
OSC
Micro Controller
—2—
LPF
Crystal
Clock
CXD1961Q
VSS10
TEST6
VDD11
TEST7
VSS11
CPOUT
VCOC
AVD2
OPX IN
OPOUT
AVS2
VCOEN
RT1
QIN
AVD1
AVS1
RB1
AVD0
RT0
IIN
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 VDD10
AVS0 1
RB0 2
79 CR7
VDD0 3
78 CR6
VSS0 4
77 CR5
CPUSEL 5
76 CR4
PLLSEL 6
75 VSS9
TEST1 7
74 VDD9
TEST2 8
72 CR3
TEST3 9
73 CR2
VDD1 10
71 CR1
VSS1 11
70 CR0
SDATA 12
69 CKV
SCLK 13
68 AGCPWM
SEN 14
67 VSS8
VDD2 15
66 VDD8
VSS2 16
65 TEST5
TCK 17
64 TEST4
TMS 18
63 XI
TDO 19
62 XO
TDI 20
61 VSS7
CK8OUT 21
60 VDD7
RESET 22
59 SDA
TE 23
58 SCL
VDD3 24
57 ADD3
VSS3 25
56 ADD2
PKTCLK 26
55 ADD1
BYTCLK 27
54 VSS6
PKTERR 28
53 VDD6
DATA0 29
52 ADD0
DATA1 30
51 CS
—3—
DS
RW
D7
D5
D6
VSS5
VDD5
D3
D4
D2
D1
D0
DATA7
DATA6
VSS4
DATA5
VDD4
DATA4
DATA2
DATA3
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXD1961Q
Pin Description
No.
1
2
3
4
5
6
7–9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29–33
34
35
36–38
39–43
44
45
46–48
49
50
51
52
53
54
Symbol
AVS0
RB0
VDD0
VSS0
CPUSEL
PLLSEL
TEST1–3
VDD1
VSS1
SDATA
SCLK
SEN
VDD2
VSS2
TCK
TMS
TDO
TDI
CK8OUT
RESET
TE
VDD3
VSS3
PKTCLK
BYTCLK
PKTERR
DATA0–4
VDD4
VSS4
DATA5–7
D0–D4
VDD5
VSS5
D5–D7
RW
DS
CS
ADD0
VDD6
VSS6
I/O
—
—
—
—
I
I
I
—
—
O
O
O
—
—
I
I
O
I
O
I
I
—
—
O
O
O
O
—
—
O
I/O
—
—
I/O
I
I
I
I
—
—
Description
Analog Ground
ADC0 bottom reference voltage
Digital Power Supply (+3.3 V)
Digital Ground
CPU interface select (L : I2C bus)
Connect Digital Ground
Test input (connect Digital Ground)
Digital Power Supply (+3.3 V)
Digital Ground
SONY internal use
SONY internal use
SONY internal use
Digital Power Supply (+3.3 V)
Digital Ground
JTAG test clock
JTAG test mode select
JTAG test data output
JTAG test data input
Divide by 8 clock of Crystal clock
Reset input (L : reset)
Test Enable (H : test enable)
Digital Power Supply (+3.3 V)
Digital Ground
R/S Packet clock
R/S Byte clock
R/S uncorrectable Packet flag
R/S data output (DATA0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
R/S data output (DATA7 : MSB)
8 bit CPU bus data I/O (D0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
8 bit CPU bus data I/O (D7 : MSB)
8 bit CPU bus Read/Write (H : Read)
8 bit CPU bus Data strobe
8 bit CPU bus Chip Select
8 bit CPU bus Address0 (LSB)
Digital Power Supply (+3.3 V)
Digital Ground
—4—
CXD1961Q
No.
55–57
58
59
60
61
62
63
64, 65
66
67
68
69
70–73
74
75
76–79
80
81
82, 83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
ADD1–3
SCL
SDA
VDD7
VSS7
XO
XI
TEST4, 5
VDD8
VSS8
AGCPWM
CKV
CR0–3
VDD9
VSS9
CR4–7
VDD10
VSS10
TEST6, 7
VDD11
VSS11
CPOUT
AVD2
VCOC
OPXIN
OPOUT
AVS2
VCOEN
RT1
AVD1
QIN
AVS1
RB1
RT0
AVD0
IIN
I/O
I
I
I/O
—
—
O
I
O
—
—
O
O
O
—
—
O
—
—
O
—
—
O
—
I
I
O
—
I
—
—
I
—
—
—
—
I
Description
8 bit CPU bus Address1–3 (ADD3 : MSB)
I2C bus serial clock
I2C bus serial data
Digital Power Supply (+3.3 V)
Digital Ground
Oscillator output (for Crystal)
Oscillator input (for Crystal)
Test output (VSS level)
Digital Power Supply (+3.3 V)
Digital Ground
PWM output for AGC
Sampling Clock monitor output
Clock Recovery data 0–3 (CR0 : LSB)
Digital Power Supply (+3.3 V)
Digital Ground
Clock Recovery data 4–7 (CR7 : MSB)
Digital Power Supply (+3.3 V)
Digital Ground
Test output (VSS level)
Digital Power Supply (+3.3 V)
Digital Ground
PLL Charge pump output
Analog Power Supply (+3.3 V)
VCO control voltage input
Embedded OP-Amp Negative input
Embedded OP-Amp output
Analog Ground
VCO enable (H : enable)
ADC1 top reference voltage
Analog Power Supply (+3.3 V)
Analog Q input (ADC1 input)
Analog Ground
ADC1 bottom reference voltage
ADC0 top reference voltage
Analog Power Supply (+3.3 V)
Analog input (ADC0 input)
Note)
Apply 0.1 µF capacitor to every power supply terminal.
Apply 0.1µF capacitor to RB0, RT0, RB1, RT1 for stable A to D conversion.
—5—
CXD1961Q
CPU Interface Register
Sub
R/W
address
MSB 7
6
5
4
3
2
1
LSB 0
0
R
ADC_IN7 ADC_IN6 ADC_IN5 ADC_IN4 ADC_IN3 ADC_IN2 ADC_IN1 ADC_IN0
1
R
BECNT15 BECNT14 BECNT13 BECNT12 BECNT11 BECNT10 BECNT9
BECNT8
2
R
BECNT7
BECNT6
BECNT5
BECNT4
BECNT3
BECNT2
BECNT1
BECNT0
3
R
QSYNC
AFC3
AFC2
AFC1
AFC0
VSYNC
RSYNC BEM_END
4
W
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
5
W
VS_N4
VS_N3
VS_N2
VS_N1
VS_N0
RATE2
RATE1
RATE0
6
W
QS_N3
QS_N2
QS_N1
QS_N0
AC2
AC1
BC2
BC1
7
W
AK2
AK1
S_INV
TIMER1
TIMER0
8
W
PLL_CTL MON_SW
9
W
DF_SKIP DOUT_INV RS_SKIP
A
W
SFD18
SFD17
SFD16
SFD15
SFD14
B
W
SFD10
SFD9
SFD8
SFD7
C
W
SFD2
SFD1
SFD0
D
W
NC023
NC022
E
W
NC015
F
W
NC07
VS_T3
AGC_INV AGC_MOD TIMER2
VS_T2
SSEL
VS_T1
VS_T0
AFC_MOD BER_T2
CE_LEV1 CE_LEV0
BER_T1
BER_T0
SFD13
SFD12
SFD11
SFD6
SFD5
SFD4
SFD3
PCD2
PCD1
PCD0
NC021
NC020
NC019
NC018
NC017
NC016
NC014
NC013
NC012
NC011
NC010
NC09
NC08
NC06
NC05
NC04
NC03
NC02
NC01
NC00
REF_SEL REF_LSB
Note)
1. Above Registers are shared by I2C bus interface and 8 bit CPU bus interface.
2. To select CPU interface, use CPUSEL (Pin 5) ; H : 8 bit CPU bus / L : I2C bus.
3. I2C bus interface slave address;
MSB 6
5
4
3
2
1
LSB 0
1
1
0
1
1
1
0
Write mode : DC (Hex)
Read mode : DD (Hex)
—6—
R/W
CXD1961Q
CPU Interface Register Brief Explanation
ADD 0
ADD 1, 2
ADD 3
ADD 4
ADD 5
ADD 6
ADD 7
ADD 8
ADD 9
ADD A
ADD A, B, C
ADD C
ADD D, E, F
ADC_IN (7 : 0)
BECNT (15 : 0)
QSYNC
AFC (3 : 0)
VSYNC
RSYNC
BEM_END
AGC (7 : 0)
ADC input level (I2+Q2 at QPSK demodulator)
Bit Error Count at QPSK demodulator output
QPSK Synchronization Flag (H : in sync.)
Auto Frequency Control data
Viterbi dec. Synchronization Flag (H : in sync)
Reed-Solomon dec. Synchronization Flag (H : in sync)
Bit Error Monitor enable Flag (H : enable)
(when AGC mode is H) AGC Gain control data
(when AGC mode is L) Reference data for self AGC
VS_N (4 : 0)
V sync threshold Bit Error Count (see Fig. 1)
RATE (2 : 0)
Punctured rate (see Fig. 2)
QS_N (3 : 0)
Threshold data for QPSK sync. judgement (see Fig. 3)
AC (2 : 1), BC (2 : 1) Parameter for Carrier recovery loop filter (see Fig. 4)
AK (2 : 1)
Parameter for Clock recovery loop filter (see Fig. 4)
S_INV
I/Q exchange (H : enable)
AGC_INV
AGC control voltage polarity (H : positive)
AGC_MOD
H : controlled by CPU (slave) L : self AGC mode (master)
TIMER (2 : 0)
Timer for AGC master mode (see Fig. 5)
PLL_CTL
For SONY internal use (input 0 for norma use)
MON_SW
For SONY internal use (input 0 for norma use)
VS_T (3 : 0)
Monitor period for Viterbi sync. (see Fig. 6)
CE_LEV (1 : 0)
Clock recovery Error feed back level (see Fig. 7)
DF_SKIP
Digital Filter skip mode (H : enable)
DOUT_INV
Data output timing invert (H : falling edge)
RS_SKIP
R/S decode skip mode (H : enable)
SSEL
For SONY internal use (input 0 for normal use)
AFC_MOD
For SONY internal use (input 0 for normal use)
BER_T (2 : 0)
Monitor period for Bit error Count (see Fig. 8)
HS_PLL
For SONY internal use (input 0 for normal use)
SFD (17 : 11)
For SONY internal use (input 0 for normal use)
PCD (2 : 0)
For SONY internal use (input 0 for normal use)
REF_SEL
For SONY internal use (input 0 for normal use)
REF_LSB
For SONY internal use (input 0 for normal use)
NC0 (23 : 0)
Sampling Frequency 2*Fs=NC0 (0 : 23)*8*Fxtal/224
(Fxtal=Crystal Frequency)
Fig. 1 V sync threshold (Error Counter Preset data)
Register
VS_N4
VS_N3
VS_N2
VS_N1
VS_N0
9
8
7
6
Limit
×2
×2
×2
×2
×25
(ex. VS_N (4 : 0)=(1, 1, 0, 0, 1) Limit=0×29+0×28+1×27+1×26+0×25=192)
max. : 992
min. : 32
Fig. 2 Punctured Rate
Punc. rate
RATE2
RATE1
RATE0
1/2
0
0
1
2/3
0
1
0
3/4
0
1
1
4/5
1
0
0
—7—
5/6
1
0
1
6/7
1
0
0
7/8
1
1
1
Auto
0
0
0
CXD1961Q
Fig. 3 QPSK Synchronization monitor
QSYNC Threshold
QSYNC Monitor Period
(QS_N3)×27+(QS_N2)×26+(QS_N1)×25+(QS_N0)×24
256 (fix)
Fig. 4 Costas Loop Filter co-efficiency
Parameter
(0, 0)
(0, 1)
(1, 0)
(AC2, AC1)
×1
1/2
1/4
(BC2, BC1)
×1
×2
×4
(AK2, AK1)
×1
1/2
1/4
(1, 1)
1/8
×8
1/8
Item
Carrier recovery IIR filter
Carrier recovery tracking range
Clock recovery IIR filter
Fig. 5 Timer period (Sampling Frequency = 60 MHz)
TIMER2
1
1
1
1
0
0
0
0
TIMER1
1
1
0
0
1
1
0
0
TIMER0
1
0
1
0
1
0
1
0
Period (ms)
140 70
35 17.5 8.75 4.38 2.19 1.09
Frequency (kHz) 7.14 14.3 28.6 57.1 114 229 457 914
Fig. 6 V sync monitor period (measurement period counter preset data)
Register
VS_T3 VS_T2 VS_T1 VS_T0
max. : 6656
12
11
10
9
Period (viterbi clock)
×2
×2
×2
×2
min. : 512
12
11
10
9
(ex. VS_T (3:0)=(0, 1, 1, 1) → Limit=1×2 +0×2 +0×2 +0×2 =4096)
(viterbi clock)
Fig. 7 Clock recovery error data (8 bit) feed back level
NCO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_LEV
(1, 1)
(1, 0)
(0, 1)
(0, 0)
Fig. 8 Bit Error Monitor period (Viterbi clock)
BER_T2
1
1
1
1
0
BER_T1
1
1
0
0
1
BER_T0
1
0
1
0
1
19
18
17
16
Period
2
2
2
2
215
0
1
0
214
0
0
1
213
—8—
0
0
0
26
CXD1961Q
Functional Description
(1) CPU Interface
CXD1961Q has two CPU interface, an 8 bit CPU bus and an I2C bus interface. Fix CPUSEL (Pin 5) to DC L or
H level depending on the choice of bus.
CPUSEL=L : I2C bus / H : 8 bit bus
I2C bus Interface
The CXD1961Q's slave address is "1101110", and the read/write operation is based on Philips standard.
<Write Data>
In write operation, the second byte is input as the sub-address of the start position. The 3rd byte then forms
the data to be written to the start register.
Successive data bytes are written to successive sub-address register.
S Slave
A SubT Address 0 C Address
A 1101110
K Nhex
A
Input data
C
for "N"
K
A
Input data
C
for "N+1"
K
A
C
K
• • •
A S
C T
K P
STA : Start condition
ACK : Acknowledgment by CXD1961Q
STP : Stop Condition
Note)
Registers of Sub-Address 0hex to 3hex are read only
<Read Data>
Before read operation, the sub-address of the start register to be read is input by using write operation, and
terminated by a stop condition.
Read operation then begins with the second byte which is the data of the start register. Data of successive
sub-address registers are read successively following by the second byte.
S Slave
A SubT Address 0 C Address
A 1101110
K Nhex
A S
C T
K P
S Slave
A
A
A
Output data
Output data
T Address 1 C
C
C
from "N"
from "N+1"
A 1101110
K
K
K
• • •
Note)
Registers of Sub-Address 4hex to Fhex are write only
—9—
A S
C T
K P
CXD1961Q
8 bit CPU bus Interface
(Write cycle)
DS
RW
D [7:0]
Valid input
ADD [3:0 ]
Valid Address
CS
T1
T2
T3
Timing
Description
T2–T1
Address, CS to Data valid
T3–T1
R/W to DS
T3–T2
Data valid to DS
T4–T3
DS pulse width
T5–T4
Data hold time
T6–T4
Address, CS, R/W hold time
Note)
Registers of Address 0hex to 3 hex are read only
T4
T5
T6
T5
T6
Min (nsec) Max (nsec)
25
24
10
70
21
24
(Read cycle)
DS
RW
D [7:0]
Valid output
ADD [3:0]
Valid Address
CS
T1
Timing
T2–T1
T3–T2
T4–T2
T5–T4
T6–T4
T2
T3
Description
Address, CS, R/W to DS
DS to Data valid
DS pulse width
Data hold time
Address, CS, R/W hold time
T4
Min (nsec) Max (nsec)
24
75
105
24
24
Note)
Registers of Address 4hex to Fhex are write only
—10—
CXD1961Q
(2) Analog to Digital Converters
The Dual 6 bit A to D converters quantize the analog I/Q input data. The input range of the ADC's is
determined by external resistors. RT0 (RT1) is the top reference voltage, and RB0 (RB1) is the bottom
reference voltage. RT0 (RT1) and RB0 (RB1) are connected internally with a 320 Ω (Typical value) resistor.
In the example shown in the following figure, input range is approximately 1.1 V, and center voltage 1.65 V.
AVD (+3.3V)
CXD1961Q
330Ω
RT
Top reference level
Input range
320Ω
330Ω
Bottom reference level
RB
AVS (0V)
(3) AGC
Input signal level of the A to D Converter is estimated by calculating I2+Q2 in 16 bit precision, and the upper
8 bits of the estimated data are sent via the CPU I/F as ADC_IN [7:0]. CXD1961Q has two AGC modes that
can be selected by AGC_MOD. In AGC slave mode, ADC_IN[7:0] is checked and an appropriate gain level
AGC[7:0] is returned by the micro controller. This value is converted into 8 bit PWM format and output from
AGCPWM (Pin 68).
In AGC master mode, reference level AGC[7:0] is set via the CPU I/F and compared to ADC_IN[7:0]
internally. The updated gain level is then output at the AGCPWM pin. In normal operation, ADC_IN[7:0]
becomes almost equal to reference level. In AGC master mode, AGC control interval is set by TIMER[2:0].
In both modes, AGCPWM output should be low pass filtered, and if needed, the level should be converted
to satisfy the AGC gain control range. Depending on AGC_INV, the polarity can be inverted. (H:positive /
L:negative)
CPU Register
ADC_IN [7 : 0]
AGC_MOD
Reference level
ADC_IN [7 : 0]
0F
3F
7F
FF
→
→
ADD 0h
ADD 7h
AGC [7 : 0]
TIMER [2 : 0]
→
→
Input signal level
to ADC input range ratio
0.25
0.5
0.7
1.0 or over range
Note)
ADC input range is subject to temperature and VDD level.
—11—
ADD 4h
ADD 7h
AGC_INV
→
ADD 7h
CXD1961Q
(4)Clock Recovery
Initial sampling clock frequency is set by a 24 bit word via the CPU I/F. This 24 bit word is written to the
NCO(Numerically Controlled Oscillator).
The sampling frequency is:
Fsample= 8*NCO [23:0]*Fxtal/224
where: NCO [23:0] is the parameter for sampling frequency, "8" is the divider gain of the PLL, Fxtal is the
reference crystal frequency, whose value should be more than 30MHz (32MHz is recommended).
The internal digital clock recovery loop feeds clock error data to the above NCO to provide sampling timing
correction .
AK [2:1] is the Loop Filter coefficient and CE_LEV [1:0] is the Loop Gain.
This value limits clock recovery range and resolution. (see the CPU Interface Register
Brief Explanation Fig.7)
Sampling clock is output from CKV (pin 69).
CPU I/F Register
AK [2:1] → ADD 7h
CE_LEV [1:0] → ADD 8h
NCO [23:0] → ADD D, E, Fh
(Example)
CE_LEV [1:0]=(0,1), NCO [23:0]=(001110000000000000000000), Fxtal=32 MHz
Sampling Frequency
= 8*(221+220+219)*32*106/224
= 23*7*106 = 56*106
→
56 MHz
Clock recovery range
= 29/(221+220+219)
= 1/210/7 = 139.5..*10–6
→
±140 ppm
1
6
24
Clock recovery
= 8*2 *32*10 /2 = 30.5. . .
→
31 Hz
resolution
(5)Carrier Recovery
The Analog I/Q inputs have a carrier offset frequency, which is not corrected by the tuner's PLL
Synthesizer. The offset is compensated by a Costas Loop, using a frequency multiplier, loop filter and the
NCO. AC [2:1] is the coefficient of the loop filter and BC [2:1] is the loop gain parameter. QPSK
synchronization(QSYNC) is determined by monitoring the output of loop filter. The internal sync detector
monitors 256 cycles, and checks the value with the threshold set by QS_N [3:0]. In QPSK synchronization,
AFC [3:0] indicates the offset proportional value which remains at that point. This value is the average data
of the loop filter output. If AFC3(=MSB) is high, tuner PLL has a negative offset to the carrier frequency ,
and vice versa if AFC3 is low. By feeding the AFC [3:0] to the tuner's PLL Synthesizer, carrier offset can be
corrected with the PLL step size.
CPU I/F Register
QSYNC,AFC [3:0]
→ ADD 3h
QS_N [3:0], AC [2:1], BC [2:1]
—12—
→ ADD 6h
CXD1961Q
(6)Viterbi decoder
By using QPSK demodulated data and Viterbi decoded data, the existence of errors is detected. Bit error
measured over a certain period is used to determine the correct punctured rate and phase synchronization
as well as bit error rate (BER). VS_N[4:0] is used to set the error count threshold, and VS_T[3:0] is used to
set the error count duration. (see Fig.1 and Fig. 6 of CPU Interface Register Brief Explanation)
For example)
VS_N[4:0]=(1, 1, 0, 0, 1)
→ Error Count threshold =192
VS_T[3:0] =(1, 0, 1, 1)
→ Error Count duration = 2048
In this case, bit error is checked for 2048 cycles. If the error count is less than 192, CXD1961Q judges that
punctured decoding is in sync and VSYNC goes high.
Punctured rate is set by RATE[2:0]. When a certain rate is set by RATE[2:0], only punctured phase search
is performed. Punctured rate and phase search is performed if RATE[2:0] is set to (0, 0, 0).
CXD1961Q has 216 (= 65536) bit counter for BER estimation. BER monitor period is set by BER_T[2:0]
(see Fig. 8), and the error count is read by CPU I/F as BECNT[15:0]. If BEM_END is low, punctured rate or
phase search is not finished and the error count is not reliable at that moment.
CPU I/F Register
BERCNT[15:0] → ADD 1, 2h
VS_N[4:0]
→ ADD 5h
VSYNC
VS_T[3:0]
→ ADD 3h
→ ADD 8h
BEM_END
BER_T[2:0]
→
→
ADD 3h
ADD 9h
(7) Packet synchronization and De-inter leaver
2 dimensional sync protection starts once sync word 47 hex or inverted sync word B 8 hex is detected. In
this algorithm, sync status changes with hysteresis depending on sync or non-sync detection every 204
byte, so that the probability of false-LOCK or Sync-loss is minimized.
When the packet synchronization is achieved,the convolutional de-inter leaver
(Forney, depth=12) starts operating.
(8) Reed - Solomon decoder
The Galois Field is generated by F(x) = x8+x4+x3+x2+1
Code is generated by G(x) = (x-α0)(x-α1)(x-α2) • • (x-α15)
If RS_SKIP is high, no correction is performed.
CPU I/F Register
RS_SKIP → ADD 9h
(9) Energy Dispersal
Energy dispersal descrambling is represented by the polynomial x15+ x14 +1. Initial sequence is loaded
when inverted sync word B8hex is detected. 1 dimensional sync protection circuit checks the inverted sync
word every 8 packets. When it is in sync, RSYNC goes high. Even if the sync is lost, the initial sequence
continues to be loaded at previous time step.
CPU I/F Register
RSYNC → ADD 3h
—13—
CXD1961Q
(10) Output Data Format
The following figure shows the output format of BYTCLK, PKTCLK, PKTERR. BYTCLK is generated by
dividing the internal viterbi clock by 8. Data output DATA[7:0] is output in sync with BYTCLK. DOUT_INV
determines whether DATA[7:0] is output on the rising edge or the falling edge of BYTCLK. PKTCLK HighTime is equal to 188 data bytes period and PKTCLK Low-Time is equal to 16 parity bytes period. PKTERR
goes H if an uncorrectable error packet is encountered.
CPU I/F Register
DOUT_INV → ADD 9h
no error
data
correctable error
parity
data
uncorrectable error
parity
data
pa
BYTCLK
PKTCLK
PKTERR
BYTCLK and PKTCLK have varying forms, depending on the punctured rate. The following figure shows
Minimum and Maximum values for each rate.
One unit represents 1 sampling clock (=2∗Symbol rate) cycles.
R=1/2
R=2/3
R=3/4
R=4/5
R=5/6
R=6/7
R=7/8
Period
Min. Max.
16
16
12
12
10
11
10
10
9
10
9
10
9
10
BYTCLK
High-Time
Min. Max.
8
8
6
6
5
6
5
5
4
5
4
5
4
5
Low-Time
Min. Max.
8
8
6
6
5
6
5
5
4
5
4
5
4
5
(For example)
SACLK
R=1/2
Viterbi
clock
Byteclock
R=7/8
Viterbi
clock
Byte clock
—14—
Period
Min. Max.
3264 3264
2448 2448
2176 1276
2040 2040
1948 1949
1904 1904
1865 1866
PKTCLK
High-Time
Min. Max.
3008 3008
2256 2256
2005 2006
1880 1880
1804 1805
1754 1755
1718 1719
Low-Time
Min. Max.
256
256
192
192
170
171
160
160
153
154
149
150
146
147
CXD1961Q
Package Outline
Unit : mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
—15—