CXD2309Q 10-bit 85MSPS 3-Channel D/A Converter Description The CXD2309Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel input/output. This is ideal for use in high-definition TVs and high-resolution displays. Features • Resolution 10-bit • Maximum conversion speed 85MSPS • RGB 3-channel input/output • Differential linearity error ±0.5 LSB • Low power consumption 275 mW (200 Ω load for 2 Vp-p output) • Single +5 V power supply • Low glitch • 48-pin QFP package Structure Silicon gate CMOS IC 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD+0.5 to VSS–0.5 V • Output current IOUT 0 to 15 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 DVDD, DVSS 4.75 to 5.25 • Reference input voltage VREF 0.5 to 2.0 • Clock pulse width TPW1, TPW0 9 (min.) • Operating temperature Topr –20 to +85 V V V ns °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E94341B01 CXD2309Q Block Diagram (LSB) R0 1 R1 2 R2 3 R3 4 R4 5 6 R6 7 R5 R7 8 R8 9 4LSB’S CURRENT CELLS 43 AVSS 42 RO 6LSB’S CURRENT CELLS LATCHES DECODER DECODER CLOCK GENERATOR (MSB) R9 10 RCK 31 (LSB) G0 11 4LSB’S CURRENT CELLS G1 12 45 AVSS 44 GO G2 13 G3 14 G4 15 G5 16 6LSB’S CURRENT CELLS LATCHES DECODER G6 17 G7 18 G8 19 DECODER CLOCK GENERATOR (MSB) G9 20 GCK 32 (LSB) B0 21 4LSB’S CURRENT CELLS B1 22 47 AVSS 46 BO B2 23 B3 24 B4 25 B5 26 6LSB’S CURRENT CELLS LATCHES DECODER B6 27 41 AVDD 40 AVDD 39 AVDD B7 28 B8 29 DECODER CLOCK GENERATOR (MSB) B9 30 38 VG BCK 33 DVDD 48 BIAS VOLTAGE GENERATOR CURRENT CELLS (FOR FULL SCALE) VB 35 DVSS 34 —2— 37 VREF 36 IREF CXD2309Q IREF VB DVSS BCK GCK RCK B9 (MSB) B8 B7 B6 B5 B4 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 VREF 37 24 B3 VG 38 23 B2 AVDD 39 22 B1 AVDD 40 21 B0 (LSB) AVDD 41 20 G9 (MSB) RO 42 19 G8 AVSS 43 18 G7 GO 44 17 G6 AVSS 45 16 G5 BO 46 15 G4 47 14 G3 AVSS 3 4 5 6 7 8 9 R2 R3 R4 R5 R6 R7 R8 (MSB) R9 12 G1 2 11 (LSB) G0 1 R1 13 G2 10 (LSB) R0 DVDD 48 1 to 35 , 48 Digital system 36 to 47 Analog system Pin Description and Equivalent Circuit Pin No. Symbol 1 to 10 R0 to R9 I/O Equivalent circuit 11 to 20 G0 to G9 21 to 30 B0 to B9 31 RCLK 32 GCLK 33 BCLK 34 DVSS Digital input. 1 pin R0 (LSB) to 10 pin R9 (MSB) 11 pin G0 (LSB) to 20 pin G9 (MSB) 21 pin B0 (LSB) to 30 pin B9 (MSB) DVDD I Description 1 to 33 DVSS Clock input. — Digital ground. DVDD DVDD 35 VB Connect an approximately 0.1µF capacitor. O 35 DVSS —3— CXD2309Q Pin No. 36 Symbol IREF I/O Equivalent circuit O AVDD Description AVDD Reference current output. Connect an “RIR” resistor which are 16 times the output resistance “ROUT”. 36 AVDD 37 VREF I AVDD Reference voltage input. Sets an output full-scale value. AVSS Connect an approximately 0.1µF capacitor. AVSS 37 38 AVSS 38 VG O 39 to 41 AVDD — 42 RO Analog power supply. AVDD 42 Current output. Output can be obtained by connecting a resistor (200 Ω typ.). 44 44 GO O 46 AVSS 46 BO 43, 45, 47 48 AVSS DVDD AVSS — — Analog ground. Digital power supply. —4— CXD2309Q (fCLK=85 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, RIR=3.3 kΩ, Ta=25°C) Electrical Characteristics Resolution Item Symbol n Conversion speed fCLK Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale ratio ∗1 EL ED Output full-scale current Output offset voltage Glitch energy Unit bit 0 85 MSPS –2.0 –0.5 2.0 0.5 LSB LSB 2.0 V VFS FSR IFS VOS GE 1.8 0 9.0 1.92 2.0 3 10 1 V % mA mV pV•s SNR Supply current IDD Analog input resistance Input capacitance Output capacitance RIN CI CO VIH VIL IIH IIL ts th tPD tr tf ∗1 Endpoint Max. 1.92 SN ratio Setup time Hold time Propagation delay time Rise time Fall time Ta=–20 to +85 °C When “0000000000” data input ROUT=100 Ω, 1 Vp-p output When 10 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 1 MHz FCLK=50 MHz sin wave input FCLK=85 MHz When 10 MHz FCLK=50 MHz sin wave output FCLK=85 MHz VREF 40 50 9.6 50 42 40 55 50 48 55 dB dB 58 1 9 125 AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C 2.15 0.85 –5 5 4 1 14 26.5 26.0 Full-scale voltage of channel –1 Average of the full-scale voltage of the channels Full-scale output ratio = Typ. 10 1.8 CT Digital input current AVDD=DVDD=4.75 to 5.25 V Min. VOC Crosstalk Digital input voltage Measurement conditions Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current } +5.25V AVDD, DVDD A CXD2309Q V AVSS, DVSS —5— × 100 (%) mA MΩ pF pF V µA ns ns ns ns ns CXD2309Q Conversion Rate Measurement Circuit R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 10bit COUNTER with LATCH 35 VB 200 AVSS OSCILLOSCOPE 200 AVSS 45 0.1µ AVSS BO 46 200 DVSS CLK 50MHz SQUARE WAVE 31 RCK AVSS 47 32 GCK VG 38 33 BCK AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3k AVSS Setup Time Hold Time Glitch Energy } Measurement Circuit R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 21 to 30 GO 44 10bit COUNTER with LATCH VB 35 CLK 50MHz SQUARE WAVE AVSS OSCILLOSCOPE 200 AVSS 45 0.1µ DELAY CONTROLLER 200 AVSS BO 46 DVSS 31 RCK AVSS 47 GCK VG 38 32 DELAY CONTROLLER 33 BCK 200 AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3k AVSS Crosstalk Measurement Circuit DVDD R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 21 to 30 GO 44 DIGITAL WAVEFORM GENERATOR 35 VB 0.1µ AVSS 200 AVSS 45 AVSS BO 46 DVSS CLK 50MHz SQUARE WAVE 200 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 2V 200 AVSS AVDD 0.1µ IREF 36 3.3k AVSS —6— SPECTRUM ANALYZER CXD2309Q DC Characteristics Measurement Circuit R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 CONTROLLER 35 VB AVSS DVM 200 AVSS 45 0.1µ AVSS BO 46 DVSS CLK 50MHz SQUARE WAVE 200 31 RCK AVSS 47 GCK VG 38 32 33 BCK 200 AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3k AVSS Propagation Delay Time Measurement Circuit R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 10bit COUNTER with LATCH 35 VB CLK 50MHz SQUARE WAVE AVSS OSCILLOSCOPE 200 AVSS 45 0.1µ DELAY CONTROLLER 200 AVSS BO 46 DVSS 31 RCK AVSS 47 GCK VG 38 32 DELAY CONTROLLER 33 BCK 200 AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3k AVSS SNR Measurement Circuit DIGITAL WAVEFORM GENERATOR R0 to R9 RO 42 1 to 10 G0 to G9 11 to 20 AVSS 43 B0 to B9 GO 44 21 to 30 ALL “1” ALL “1” 35 VB 0.1µ AVSS 200 AVSS 45 AVSS BO 46 DVSS CLK 50MHz SQUARE WAVE 200 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 2V 200 AVSS AVDD 0.1µ IREF 36 3.3k AVSS —7— SPECTRUM ANALYZER CXD2309Q Description of Operation Timing Chart tPW1 tPW0 1.5V CLK AA AA AA AAA AA AA AA AAA AA AAAAAAA ts th ts th ts th DATA 1.5V D/A OUT 100% 90% 50% tPD tr I/O Correspondence Table (output full-scale voltage: 2.00 V) Input code Output voltage MSB LSB 1 1 1 1 1 1 1 1 1 1 2.0 V : 1 0 0 0 0 0 0 0 0 0 1.0 V : 0 0 0 0 0 0 0 0 0 0 0V —8— tf 10% 0% CXD2309Q Notes on Operation • Selecting the Output Resistance CXD2309Q is a current output type D/A converter. The output voltage can be obtained by connecting the resistor ROUT to the current output pins RO, GO and BO. Specifications: Output full-scale voltage VFS = 1.8 to 2.0 [V] Output full-scale current IFS = 9.0 to 10.0 [mA] Calculate the output resistance from VFS = IFS × ROUT. Connect a resistance sixteen times the output resistance to the reference current output pin IREF. In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following. VFS = VREF × 16ROUT/RIR VREF is the voltage set at the reference voltage input pin VREF, ROUT is the resistor to be connected to the current output pins RO, GO, BO and RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data setting time. Set the best values according to the purpose of use. • Correlation between Data and Clock For CXD2309Q to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in “Electrical Characteristics”. • Power supply, ground Separate the analog and digital signals around the device to reduce noise effects. Bypass the power supply pin to each ground with a 0.1 µF ceramics capacitor as near as possible to the pin for both the digital and analog signals. • Latch up Analog and digital power supplies must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. • IREF The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. • VG pin It is recommended to use a 1 µF capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1 µF. • Output full-scale voltage For the applications using the RGB signal, the color balance may be broken up when the RO, GO and BO output full-scale voltages are used with not adjustment. —9— CXD2309Q Application Circuit C C R2 MSB Clock input 36 35 34 33 32 31 30 29 28 27 26 25 R3 C R1 R1 R1 24 38 23 39 22 40 21 LSB 41 20 MSB 42 19 43 18 44 17 45 16 46 15 47 14 48 13 2 3 4 LSB 1 • • • • • • 5 6 R ch input AVDD DVDD AVSS DVSS 7 8 9 10 11 LSB C 37 MSB C R4 B ch input G ch input 12 When the power supply (AVDD and DVDD) is 5.0 V. R1=200 Ω R2=3.3 kΩ R3=3.0 kΩ R4=2.0 kΩ C=0.1 µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —10— CXD2309Q Latch Up Prevention The CX2309Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pin 39, 40 and 41) and DVDD (Pin 48), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 39 40 41 48 AVDD +5V DVDD +5V CXD2309Q C AVSS 43 45 C DIGITAL IC DVSS 47 34 AVSS b. When analog and digital supplies are from a common source (i) DVDD 39 40 41 AVDD 48 DVDD +5V CXD2309Q C AVSS 43 45 C DIGITAL IC C DIGITAL IC DVSS 47 34 AVSS (ii) DVDD 39 40 41 AVDD 48 DVDD +5V CXD2309Q C AVSS 43 33 45 DVSS 47 31 34 AVSS —11— CXD2309Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 39 40 41 48 AVDD +5V DVDD +5V CXD2309Q C AVSS 43 45 C DIGITAL IC DVSS 47 34 AVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 39 40 41 AVDD 48 DVDD +5V CXD2309Q C AVSS 43 45 C DIGITAL IC C DIGITAL IC DVSS 47 34 AVSS (ii) DVDD AVDD 39 40 41 AVDD 48 DVDD +5V CXD2309Q AVSS 43 45 DVSS 47 34 AVSS —12— CXD2309Q 2.0 Glitch energy GE [pV•s] Output full-scale voltage VFS [V] Example of Representative Characteristics 1.0 0 1.0 100 50 2.0 0 100 200 Output resistance ROUT [Ω] Fig. 2. Output resistance vs. Glitch energy Reference voltage VREF [V] Fig. 1. Reference voltage vs. Output full-scale voltage 1.95 Supply current IDD [mA] Output full-scale voltage VFS [V] 70 1.90 ∆V=0.02mV/°C 0 –25 0 25 50 sin wave output 60 50 40 75 1 2 Ambient temperature Ta [°C] Fig. 3. Ambient temperature vs. Output full-scale voltage 5 10 20 30 40 42 Output frequency Fo [MHz] Fig. 4. Output frequency vs. Supply current Standard Measurement Conditions • AVDD=DVDD=5.0 V • VREF=2.0 V • FCLK=85 MHZ • ROUT=200 Ω • RIR=3.3 kΩ • Ta=25 °C —13— CXD2309Q fout=1MHz sin wave 50 IDD 40 IA [Analog] 30 20 10 fout=10MHz sin wave 60 Supply current IDD [mA] Supply current IDD [mA] 60 IDD 40 IA [Analog] 30 20 ID [Digital] 10 ID [Digital] 20 50 85 50 20 Clock frequency FCLK [MHz] Fig. 5. Clock frequency vs. Supply current Clock frequency FCLK [MHz] Fig. 6. Clock frequency vs. Supply current 0 sin wave output Output level [dBm] Cross talk CT [dB] 60 50 85 50 40 30 20 –10 –20 10 0 1 2 5 10 20 42 0 1 2 5 10 20 50 Output frequency Fo [MHz] Fig. 8. Output frequency vs. Output level (Including primary hold characteristics sinx/x) Output frequency Fo [MHz] Fig. 7. Output frequency vs. Cross talk Standard Measurement Conditions • AVDD=DVDD=5.0 V • VREF=2.0 V • FCLK=85 MHZ • ROUT=200 Ω • RIR=3.3 kΩ • Ta=25 °C —14— CXD2309Q 1000 Input current [µA] SNR [dB] 50 40 500 30 0 1 2 5 10 20 50 –1 0 1 5 6 Input voltage [V] Output frequency Fo [MHz] Fig. 9. Output frequency vs. SNR 500 1000 Fig. 10. Input terminal V-I characteristics Standard Measurement Conditions • AVDD=DVDD=5.0 V • VREF=2.0 V • FCLK=85 MHZ • ROUT=200 Ω • RIR=3.3 kΩ • Ta=25 °C —15— CXD2309Q Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 13.5 37 48 + 0.2 0.1 – 0.1 13 12 0.8 + 0.15 0.3 – 0.1 0.24 M 0.9 ± 0.2 1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE QFP048-P-1212 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g —16—