SONY CXD2310

CXD2310AR
10-bit 20MSPS Video A/D Converter
Description
The CXD2310AR is a 10-bit CMOS A/D converter
for video applications. This IC is ideally suited for the
A/D conversion of video signals in TVs, VCRs,
camcorders, etc.
Features
• Resolution: 10-bit ±1.0 LSB (D.L.E.)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 150mW (at 20MSPS typ.)
(Not including reference current)
• TTL compatible input
• Tri-state TTL compatible output (DVDD = 3.3V)
• Low input capacitance
• Reference impedance: 280Ω (typ.)
48 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
7
V
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5 V
• Input voltage (analog)
VIN
VDD + 0.5 to VSS – 0.5 V
• Input voltage (digital)
VIH, VIL
VDD + 0.5 to VSS – 0.5 V
• Output voltage (digital)
VOH, VOL
VDD + 0.5 to VSS – 0.5 V
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
AVDD, AVSS
5.0 ± 0.25
DVDD, DVSS
3.0 to 5.25
| DVSS – AVSS |
0 to 100
• Reference input voltage VRB
More than 1.8
VRT
to AVDD – 0.4
• Analog input
VIN
More than 1.8Vp-p
• Clock pulse width
TPW1
25 (min.)
TPW0
25 (min.)
• Operating ambient temperature
Topr
–20 to +75
V
V
mV
V
V
ns
ns
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95429B5X-PK
CXD2310AR
Block Diagram
VIN 39
VRT 29
VRT 30
AA
AA
AAA
AAAA
AA
AAAAAAA
AAAA
AAAA
AAA
AAA
AAAA
AAAA
AAA
AAA
AAAA
AAAA
AAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAAAAAAAAA
AAAA
AAA
AAA
AAAA
AAAAA
AAAA
AAAAA
AAAAA
S/H
Amp
AVDD
27 28 36
18 26
×8
+
+
AVSS
12 D9
Sense
Amp
–
Coarse
Correction
&
Latch
11 D8
10 D7
9 D6
8 D5
DAC
Fine
Comparate
&
Encode
Coarse
Comparate
&
Encode
5 D4
4 D3
Fine
Latch
VRB 35
D2
2 D1
Calibration
Unit
VRB 34
3
1 D0 (LSB)
21 MINV
Sense
Amp
20 LINV
19 TESTMODE
CLK 22
OE 23
CE 24
Timing Gen
41 CAL
Auto Calibration
Pulse Generator
17 SEL
15 RESET
Pin Configuration
AVDD
AVDD
AVSS
VRT
AVSS
VRT
NC
NC
NC
VRB
37 TSTR
38 AT
VRB
AVSS
36 35 34 33 32 31 30 29 28 27 26 25
CE 24
OE 23
39 VIN
CLK 22
40 NC
MINV 21
41 CAL
LINV 20
42 TS
TESTMODE 19
43 AVSS
AVDD 18
44 AVSS
SEL 17
45 DVDD
DVSS 16
D6
4
5
6
7
8
9 10 11 12
–2–
D8
D5
3
D9
DVDD
2
D7
DVSS
1
D4
TO 13
D3
48 DVSS
D2
TIN 14
D1
RESET 15
D0
46 NC
47 NC
CXD2310AR
Pin Description
Pin No
Symbol
Equivalent circuit
Description
DVDD
1 to 5
8 to 12
D0 (LSB) to D9 (MSB)
output.
D0 to D9
DVSS
TO
Test pin.
TS = High:
High impedance state
7, 45
DVDD
Digital VDD.
6, 16, 48
DVSS
Digital VSS.
27, 28, 36,
43, 44
AVSS
Analog VSS.
13
AVDD
17
SEL
Calibration input pulse
select after completion of
the startup calibration.
High : Internal pulse
generation
Low : External input
17
AVSS
AVDD
22
CLK
Clock pin.
22
AVSS
AVDD
41
CAL
Calibration pulse input.
41
AVSS
AVDD
15
RESET
Calibration circuit reset
and startup calibration
restart.
15
AVSS
–3–
CXD2310AR
Pin No.
14
Symbol
Equivalent circuit
Description
Test signal input.
Normally fixed to AVDD or
AVSS.
TIN
AVDD
29, 30
Reference top.
VRT
29
30
AVSS
34, 35
VRB
34
Reference bottom.
35
38
AT
Test signal output.
TS = High:
High impedance state
42
TS
Test signal input.
Normally fixed to AVDD.
37
TSTR
Test signal input.
Normally fixed to AVSS.
AVDD
23
OE
D0 to D9 output enable.
Low : Output state
High : High impedance
state
23
AVSS
AVDD
24
CE
Chip enable.
Low : Active state
High : Standby state
24
AVSS
–4–
CXD2310AR
Pin No.
Symbol
Equivalent circuit
Description
AVDD
19
TESTMODE
Test mode.
High : Output state
Low : Output fixed
19
AVSS
AVDD
20
LINV
Output inversion.
High : D0 to D8 are
inverted and
output.
20
AVSS
AVDD
21
MINV
Output inversion.
High : D9 is inverted and
output.
21
AVSS
18, 25, 26
AVDD
Analog VDD.
AVDD
39
VIN
Analog input.
39
AVSS
–5–
CXD2310AR
Digital Output
The following table shows the correlation between the analog input voltage and the digital output code
(TESTMODE = 1, LINV, MINV = 0)
Input signal voltage
Step
Digital output code
MSB
LSB
VRT
0
1 1 1 1 1 1 1 1 1 1
511
512
1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1
1023
0 0 0 0 0 0 0 0 0 0
VRB
The following table shows the output state for the combination of TESTMODE, LINV, and MINV states.
TESTMODE
LINV
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0
0
1
1
0
0
1
1
P
N
P
N
1
0
1
0
P
N
P
N
0
1
0
1
P
N
P
N
1
0
1
0
P
N
P
N
0
1
0
1
P
N
P
N
1
0
1
0
P
N
P
N
0
1
0
1
P
N
P
N
1
0
1
0
P
N
P
N
0
1
0
1
P
N
P
N
1
0
1
0
P
P
N
N
0
0
1
1
P: Forward-phase output N: Inverted output
Timing Chart 1
tPW0
tPW1
1.65V
Clock
A
AA
tSD
Analog input
A
N+1
N
tDL
Data output
N–3
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
Timing Chart 2
Data output
N–1
: Indicates point at which analog data is sampled
tPZE
1.65V
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
Active
High Impedance
–6–
N+4
N
A
1.65V
Output enable (OE)
N+3
N–2
tPEZ
AA
A
N+2
Active
CXD2310AR
Electrical Characteristics
Item
Max. conversion rate
Min. conversion rate
Analog
Supply
current
Digital
Analog
Standby
current
Digital
Reference pin current
Analog input band
Analog input capacitance
Reference resistance value
(VRT – VRB)
(Fc = 20MSPS, AVDD = 5V, DVDD = 3.3V, VRB = 2.0V, VRT = 4.0V, Ta = 25°C)
Symbol
Conditions
Fc max
Fc min
IADD
IDDD
IAST
IDST
IRT
IRB
BW
CIN
FIN = 1.0kHz
triangular wave input
20
FIN = 1.0kHz
triangular wave input
20
Offset voltage
EOB
5.0
–11.0
–1dB
EOT = theoretical value-actual
measured value
EOB = actual measured valuetheoretical value
40
90
140
–120
tPEZ
Clock not synchronized for
active → high impedance
20
Tri-state output enable time
tPZE
Clock not synchronized for high
impedance → active
Integral non-linearity error
Differential non-linearity error
Differential gain error
Differential phase error
Output data delay
Sampling delay
EL
ED
DG
DP
Digital input current
Digital output current
Digital output current
tDL
tSD
40
–40
VIH = DVDD
VIL = 0V
–7–
µA
mA
Ω
V
0.8
50
5
5
3.5
3.5
V
µA
µA
mA
1
1
µA
25
30
ns
10
15
20
ns
±2.0
±1.0
LSB
8
2
±1.3
±0.5
1.0
0.3
13
4
NTSC 40 IRE mod
ramp, Fc = 14.3MSPS
CL = 20pF
mA
–20
2.3
–50
DVDD = max
–70
2.5
1.0
VIN = 4V
VIN = 2V
MSPS
mV
AVDD – AVSS
VRT – VRB
AVDD = 4.75V to 5.25V
Unit
MHz
pF
380
Tri-state output disable time
Analog input current
7.0
–7.0
70
9
0.5
34
5
1.0
1.0
11.0
–5.0
280
OE = AVSS VOH = DVDD – 0.5V
DVDD = min VOL = 0.4V
OE = AVDD VOH = DVDD
DVDD = max VOL = 0V
Digital input voltage
27
3.0
Max.
180
VCAL1
VCAL2
VIH
VIL
AIH
AIL
IIH
IIL
IOH
IOL
IOZH
IOZL
Startup calibration start
voltage
Typ.
CE = High
RREF
EOT
Min.
%
deg
18
6
ns
ns
CXD2310AR
Symbol
Item
SNR
SNR
SFDR
SFDR
Conditions
Min.
Typ.
Max.
53
52
53
54
47
45
60
59
60
65
50
49
FIN = 100kHz
FIN = 500kHz
FIN = 1MHz
FIN = 3MHz
FIN = 7MHz
FIN = 10MHz
FIN = 100kHz
FIN = 500kHz
FIN = 1MHz
FIN = 3MHz
FIN = 7MHz
FIN = 10MHz
Unit
dB
dB
Application Circuit 1. Startup calibration + internal auto calibration
4.0V
AVDD
2.0V
4.0V
MINV 21
41 CAL
LINV 20
AVSS
Clock input
AVDD
TESTMODE 19
43 AVSS
AVDD 18
44 AVSS
SEL 17
45 DVDD
DVSS 16
5
6
7
8
9 10 11 12
AVSS
AVDD
DVSS
D9
4
D7
3
D6
2
DVDD
1
D5
TO 13
DVSS
48 DVSS
D3
TIN 14
D4
RESET 15
47 NC
D2
46 NC
D1
DVSS
AVDD
40 NC
D0
AVSS
AVDD
AVSS
AVSS
VRT
VRT
NC
NC
NC
OE 23
CLK 22
42 TS
DVDD
CE 24
39 VIN
D8
AVDD
37 TSTR
38 AT
VRB
AVSS
VRB
2.0V
AVSS
36 35 34 33 32 31 30 29 28 27 26 25
is all 0.1µF
Digital output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–8–
CXD2310AR
Application Circuit 2. Startup calibration + external sync calibration
4.0V
AVDD
2.0V
4.0V
AVDD
AVDD
AVSS
AVSS
VRT
NC
VRT
NC
NC
VRB
VRB
41 CAL
LINV 20
AVSS
Clock input
AVDD
TESTMODE 19
42 TS
43 AVSS
AVDD 18
44 AVSS
SEL 17
45 DVDD
DVSS 16
47 NC
TIN 14
48 DVSS
TO 13
4
5
6
7
8
9 10 11 12
AVSS
AVDD
DVSS
D9
3
D8
2
D7
1
D6
RESET 15
DVDD
46 NC
D5
DVSS
MINV 21
DVSS
AVSS
40 NC
D3
DVDD
OE 23
CLK 22
D4
AVDD
CE 24
39 VIN
D2
Calibration pulse
37 TSTR
38 AT
D1
AVSS
D0
2.0V
AVSS
36 35 34 33 32 31 30 29 28 27 26 25
is all 0.1µF
Digital output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–9–
CXD2310AR
Application Circuit 3. Only startup calibration
(Less than supply voltage fluctuation range of AVDD = ±100mV and reference voltage fluctuation range of
|VRT – VRB| = 200mV)
4.0V
AVDD
2.0V
4.0V
MINV 21
41 CAL
LINV 20
AVSS
Clock input
AVDD
TESTMODE 19
43 AVSS
AVDD 18
44 AVSS
SEL 17
45 DVDD
DVSS 16
2
3
4
5
6
7
8
9 10 11 12
AVSS
AVDD
DVSS
D9
D6
1
D7
D5
TO 13
DVDD
48 DVSS
DVSS
TIN 14
D4
47 NC
D3
RESET 15
D2
46 NC
D0
DVSS
AVDD
40 NC
D1
AVSS
AVDD
AVSS
VRT
AVSS
NC
VRT
NC
NC
OE 23
CLK 22
42 TS
DVDD
CE 24
39 VIN
D8
AVDD
37 TSTR
38 AT
VRB
AVSS
VRB
2.0V
AVSS
36 35 34 33 32 31 30 29 28 27 26 25
is all 0.1µF
Digital output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 10 –
CXD2310AR
1. Calibration Function
In order to achieve superior linearity, the CXD2310AR has a built-in calibration circuit. In order to eliminate the
necessity for the externally input calibration pulse required by the earlier CXD2310R, a startup calibration
function and an auto calibration pulse generation function have been newly added to the CXD2310AR. Fig. 1
shows a block diagram of the calibration pulse generation circuit.
AVDD
1
16
CLK
D Q
14 bit
Counter
CLR
CLR
AVDD
AVSS
Sence
Amp 1
VRT
VRB
Sence
Amp 2
OUT
CO
24 bit
Counter
CLR
CO
SEL
RESET
CE
CAL
Fig. 1. Calibration Pulse Generation Circuit
(1) Startup Calibration Function
Over 600 calibration pulses are needed to complete the initial calibration process when the power is first
supplied to the IC. The startup calibration function automatically generates these pulses internally and
completes the initial calibration process.
The following five conditions must be satisfied to initiate the
startup calibration function.
When RESET = High and CE = Low
[V]
AVDD
5
VRT
2.5
VRB
1V
0
[t]
a) The voltage between AVDD and AVSS is approximately
2.5V or more.
b) The voltage between VRT and VRB is approximately 1V
or more.
c) The RESET pin (Pin 15) must is high.
d) The CE pin (Pin 24) must is low.
e) Condition b is met after condition a.
Sence Amp 1
Sence Amp 2
CLR
Once all five of these conditions have been met, the calibration
pulses are generated. The pulses are generated by counting 16
main clock cycles on a 14-bit counter and closing the gate when
the carry-out occurs. Therefore, the time required for startup
calibration after the above five conditions have been met is
determined by the following formula:
Startup calibration time = main clock cycle × 16 × 16,384
For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.
– 11 –
CXD2310AR
(2) Auto Calibration Pulse Generation Function
After startup calibration is completed, this function periodically generates calibration pulses so that calibration
can be performed constantly without any need for input of calibration pulses from an external source. This
function counts 16 main clock cycles on a 24-bit counter and uses the carry-out as the calibration pulse. The
cycle of the calibration pulse generated in this fashion is as follows:
Internal calibration pulse generation cycle = main clock cycle × 16 × 16,777,216
Therefore, if the main clock frequency is 14.3MHz, the calibration pulse cycle is approximately 19 seconds;
since calibration is performed once every seven pulses, the calibration cycle is approximately 130 seconds. In
order to use this function, the SEL pin (Pin 17) must be high.
Note that this function cannot be used if fixing the lower bits in the calibration operation as described below will
cause problems because this function is executed asynchronously without regard to the input signals.
(3) External Calibration Pulse Input Function
If the auto calibration function cannot be used, calibration can be performed in synchronization with the input
signals when a calibration pulse is input from the CAL pin (Pin 41) by setting the SEL pin (Pin 17) low.
10ns or more
7clock
CLK
CAL
1clock or more
D5 to D9
N–3
N–2
N–1
D0 to D4
N–3 N–2
N–1
N
N+1 N+2
N
N+3 N+4
N+5
N+5
Fig. 2. Calibration Timing Chart
Calibration starts when the falling edge of the pulse input to the CAL pin (Pin 41) is detected. Because the
lower comparator is occupied for four clock cycles at this point, the previous lower data is held for four clock
cycles after seven clock cycles since the rising edge of the clock cycle in which the falling edge of CAL was
detected. Calibration can be performed outside of video intervals by using the sync signal, etc., to input the
CAL signal. An example of this is shown below.
(1) Inputting CAL every H-sync
Input
CLK
CAL
– 12 –
CXD2310AR
(2) Inputting CAL every V-sync
Input
CLK
RESET
CAL
It is also possible to use only the startup calibration function by leaving the SEL pin (Pin 1/) low and fixing the
CAL pin (Pin 41) either high or low. Note that this method requires restriction of the fluctuation range of the
supply voltage and the reference voltage.
(4) Re-initiating the Startup Calibration Function
The startup calibration function can be re-initiated after the power and reference voltage are supplied by using
the CE pin (Pin 24) and the RESET pin (Pin 15). Particularly in cases where the riseup characteristics of the
power supply and the reference voltage are unstable or the order of the riseup is not kept, it is possible to
initiate startup calibration properly by connecting a CR and delaying startup until after power supply riseup.
AVDD
[V]
AVDD
VRT
R
RESET
RESET 15
VRB
C
AVSS
[t]
Fig. 3. Initiation of the Startup Calibration Function Using the RESET pin
– 13 –
CXD2310AR
2. Power supply
To prevent the influence of noise, connect the power supply to a 0.1µF by-pass capacitor as near the device
as possible.
3. DVDD
Either a 3.3V or 5.0V digital power supply can be used. Compared to the 5.0V power supply, the 3.3V power
supply generates a decreased amount of radiation noise but offers a decreased drive capacity. These two
power supplies do not virtually differ in static and dynamic characteristics. Further, the High output level rises
up to DVDD.
4. Reference input
The voltage to be supplied to the reference pins must be driven by a buffer having a 10mA or more drive
capacity. For supplied voltage stabilization, connect the buffer to a 0.1µF by-pass capacitor as near the pins as
possible.
5. Latch-up
Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may
be caused by power ON time-lag.
6. Board
To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern
for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate
its characteristics adequately.
– 14 –
CXD2310AR
Example of Representative Characteristics
29
28
27
0
25
50
75
Maximum operating frequency vs.
Ambient temperature
35
fin = 1kHz ramp wave
AVDD = 5.0V
DVDD = 3.3V
30
25
20
–20
25
50
75
Ambient temperature [°C]
Output data delay vs Ambient temperature
Sampling delay vs. Ambient temperature
17
15
AVDD = 5.0V
DVDD = 3.3V
Fc = 1MHz
CL = 20pF
13
–20
0
25
50
AVDD = 5.0V
DVDD = 3.3V
Fc = 1MHz
6
4
2
75
–20
0
25
50
75
Ambient temperature [°C]
Ambient temperature [°C]
Input frequency vs. SNR
Input frequency vs. SFDR
AVDD = 5.0V
DVDD = 3.3V
Fc = 20MHz
VIN = 2Vp-p
Ta = 25°C
60
50
60
40
50
AVDD = 5.0V
DVDD = 3.3V
Fc = 20MHz
VIN = 2Vp-p
Ta = 25°C
40
100k
1M
10M
Input frequency [Hz]
100k
Input frequency vs. Effective bits
AVDD = 5.0V
DVDD = 3.3V
Fc = 20MHz
VIN = 2Vp-p
Ta = 25°C
9
8
7
100k
1M
1M
10M
Input frequency [Hz]
Input band
Output level [dB]
Effective bits [bit]
0
Ambient temperature [°C]
Sampling delay [ns]
Output data delay [ns]
–20
SNR [dB]
Maximum operating frequency [MHz]
Fc = 20MHz
fin = 1kHz ramp wave
AVDD = 5.0V
DVDD = 3.3V
SFDR [dB]
Supply current [mA]
Supply current vs. Ambient temperature
10M
1
0
–1
–2
–3
AVDD = 5.0V
DVDD = 3.3V
Fc = 20MHz
VIN = 2Vp-p
Ta = 25°C
100k
Input frequency [Hz]
1M
10M
Input frequency [Hz]
– 15 –
CXD2310AR
Package Outline
Unit : mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
25
A
13
48
(0.22)
0.5 ± 0.2
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 16 –