CXD2400R Timing Controller for CCD cameras Description The CXD2400R is a timing controller for CCD camera systems which use the ICX044/045, ICX054/055 or other black/white CCD image sensors. Features • Supports EIA/CCIR standards • Electronic iris (electronic shutter) function • Sync signal generation function • Supports external synchronization • Supports non-interlacing • Supports field/frame∗ accumulation • Oscillator frequency: 1212 fh (EIA: 19.0699MHz; CCIR: 18.9375MHz) ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. 48 pin LQFP (Plastic) Applications CCD cameras Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) Vss – 0.5 to +7.5 V • Supply voltage VDD • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage Vo Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage 5.0V ± 0.25 • Operating temperature –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93308D75-PS –2– 5 25 26 8 7 RG SHP SHD XV1 XV2 XV4 12 10 1 AVDD XV3 3 2 H1 H2 4 AVSS CKI 48 47 46 LCOUT 12 12fH L LCIN Block Diagram 11 GATE 45 35 CBLK 36 1/2 HD1 FLD 32 30 29 TG/SSG 1/606 VR1 CLP1 CLP2 SYNC SEP 34 37 40 38 39 HD ESYNC HPLL VR/SYNC EXT HCOMP XSG1 XSG2 SYNC 9 LPF PS CVss 16 1/525 1/625 24 41 RESET GEN 42 LSEL NIL 27 EIA Field/ Frame 28 FL/FR SPDNV /ED2 17 IRIN /ED1 UP/DOWN ADDER O/E 22 33 VD 43 19 21 SPUPV /ED0 23 CVDD P/S DECODE 18 LPF ED0 ED1 ED2 Vreg 20 SELECTOR D COUNTER IRIS/SHUTTER CK GEN CK 6 44 TEST XSUB 15 IRENB 14 ENB 13 VIDEO SIG. GATE 31 Vss1 Vss2 Vss3 TEST CIRCUIT VDD2 VDD1 CXD2400R EXT SHP 29 28 27 26 25 EIA FL/FR CLP2 VSS3 CLP1 FLD HD 34 33 32 31 30 SHD 36 35 VD CBLK Pin Configuration (Top View) SYNC CXD2400R 24 CVSS 37 HPLL 38 23 SPUPV/ED0 VR/SYNC 39 22 SPDNV/ED2 21 CVDD ESYNC 40 20 Vreg LSEL 42 19 VDD1 VDD2 43 18 VSS2 TEST 44 17 IRIN/ED1 HCOMP 45 16 PS LCIN 46 15 IRENB NIL 41 14 ENB LCOUT 47 13 2 3 4 5 6 7 8 9 10 11 12 H1 H2 AVSS RG VSS1 XV2 XV1 XSG1 XV3 XSG2 XSUB XV4 1 AVDD CKI 48 Pin Description Pin No. Symbol I/O Description 1 AVDD 2 H1 — O∗2 3 H2 O∗2 4 AVss 5 RG 6 Vss1 — GND 7 XV2 O XV2 clock output for CCD vertical register drive 8 XV1 O XV1 clock output for CCD vertical register drive 9 XSG1 O CCD sensor charge readout pulse output 10 XV3 O XV3 clock output for CCD vertical register drive 11 XSG2 O CCD sensor charge readout pulse output 12 XV4 O XV4 clock output for CCD vertical register drive 13 XSUB O CCD discharge pulse output 14 ENB I XSUB pulse output ON/OFF control (with pull-up resistance) Low: XSUB pulse output stop; high: XSUB pulse output 15 IRENB I Low: Electronic shutter mode; high: electronic iris mode (with pull-up resistance) 16 PS I Electronic shutter speed input switchover (with pull-up resistance) Low: Serial input; high: parallel input 17 IRIN/ED1 I∗1 Iris signal input/shutter speed setting; clock input in serial mode. 18 Vss2 — GND 19 VDD1 — Power supply — O∗5 Power supply (for H1, H2) H1 clock output for CCD horizontal register drive H2 clock output for CCD horizontal register drive GND (for H1, H2) Reset gate pulse output –3– CXD2400R Pin No. Symbol I/O Description 20 Vreg — Bias current supply for comparator 21 CVDD — Power supply (for comparator) 22 SPDNV /ED2 I∗1 Shutter speed down reference voltage/ Shutter speed setting; data input in serial mode 23 SPUPV /ED0 I∗1 Shutter speed up reference voltage/ Shutter speed setting; strobe input in serial mode 24 CVss GND (for comparator) 25 SHP — O∗1 26 SHD O∗1 27 EIA I Low: EIA; high: CCIR (with pull-down resistance) 28 FL/FR I Field accumulation/frame accumulation, odd field/even field switchover (with pull-down resistance) 29 CLP2 O Pulse output for clamp 30 CLP1 O Pulse output for clamp 31 Vss3 — GND 32 FLD O Field identification signal output High: odd field; low: even field 33 VD O Vertical drive output 34 HD O Horizontal drive output 35 SYNC O Composite sync output 36 CBLK O Composite blanking output 37 EXT O External sync/internal sync identification signal High: external sync; Low: internal sync 38 HPLL I Horizontal drive signal input (with pull-up resistance) 39 VR/SYNC I Vertical drive signal input/composite sync input (with pull-up resistance) 40 ESYNC I Low: SYNC sync or internal sync; high: VD/HD sync (with pull-down resistance) 41 NIL I Low: interlace mode; high: non-interlace mode (with pull-down resistance) 42 LSEL I Line number selection pin (with pull-down resistance) Low: EIA 262H/CCIR 312H; high: EIA 263H/CCIR 313H 43 VDD2 — 44 TEST 45 HCOMP I O∗4 46 LCIN 47 LCOUT I∗2 O∗3 48 CKI I∗3 Precharge level sample-and-hold pulse Data sample-and-hold pulse Power supply Fixed to low level (with pull-down resistance) H comparator output LC oscillation (crystal oscillator) inverter input LC oscillation (crystal oscillator) inverter output Clock input O∗1 → POWERED BUFFER O∗2 → Hdriver Cell O∗3 → OSCILLATOR Cell O∗4 → Phase Comparater O∗5 → RGdriver Cell I∗1 → Comparater Input I∗2 → OSCILLATOR Cell I∗3 → Input cell with feedback resistance –4– CXD2400R Electrical Characteristics 1) DC Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Item Symbol Conditions VDD Supply voltage Min. Typ. Max. Unit 4.75 5.0 5.25 V 0.7VDD VIH1 Input voltage 1 (All input pins except those below) VIL1 V 0.3VDD V Input voltage 2 (Pins 22, 23 only in electronic iris mode) VIN2 2.0 VDD V Input voltage 3 (Pin 17 only in electronic iris mode) VIN3 VSS VDD V Output voltage 1 (All output pins except those below) VOH1 IOH = –2mA VOL1 IOL = 4mA Output voltage 2 (Pins 25, 26) VOH2 IOH = –4mA VOL2 IOL = 8mA Output voltage 3 (Pin 5) VOH3 IOH = –8mA VOL3 IOL = 8mA Output voltage 4 (Pins 2, 3) VOH4 ICH = –20mA VOL4 ICL = 20mA Output voltage 5 (Pin 47) VOH5 IOH = –3mA VOL5 IOL = 3mA Output voltage 6 (Pin 45) VOH6 IOH = –4mA VOL6 IOL = 4mA Feedback resistance RFB VIN = Vss or VDD 250k Pull-up resistance RPU VIL = 0V Pull-down resistance RPD VIH = VDD Current consumption IDD VDD = 5V ICX054AL in normal operating state 0.4 Item 0.4 VDD – 0.8 Min. Typ. VDD – 0.8 V V 0.4 VDD/2 V V VDD/2 VDD – 0.8 V V 0.4 V 1M 2.5M Ω 25k 50k 75k Ω 25k 50k 75k Ω 36 Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF Input/output pin capacitance CI/O 11 pF –5– V V 0.4 (VDD = V1 = 0V, fM = 1MHz) Symbol V V VDD – 0.8 ∗ Power consumption: 180mW typ., ICX054AL load (in normal operating state) 2) Input/output capacitance V VDD – 0.8 mA CXD2400R 3) Comparator characteristics Item (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Symbol Input offest voltage VOS Indefinite region Vf Min. Typ. Note) 1. Input offset voltage and indefinite region Input offset voltage and indefintie region are existed in the comparator which builds in this IC as shown right figure. Note that this when designing external circuit. 2. Pins 22 and 23 for electronic iris mode Use it in this state of Pin 22 (SPDNV) > Pin 23 (SPUPV). Max. Unit 50 mV ± 10 mV 5.0V Indefinite region 50mV Input offset voltage 50mV Input offset voltage 10mV 10mV Pins 22 and 23 (SPDNV and SPUPV) 10mV 10mV Indefinite region GND Mode Control Pin No. I/O Low High ENB 14 I XSUB stop XSUB output IRENB 15 I Electronic shutter Electronic iris Valid only when ENB is high. PS 16 I Serial input Parallel input Valid only when ENB is high and IRENB is low. IRIN/ED1 17 I SPDNV/ED2 22 I SPUPV/ED0 23 I EIA 27 I FL/FR 28 I Symbol ESYNC 40 I HPLL 38 I VR/SYNC 39 I NIL 41 I LSEL 42 I EXT 37 O Remarks Electronic iris control signal input pin (IRENB = high) Shutter speed setting pin (IRENB = Low) Valid only when ENB is high. EIA CCIR Odd field Even field Field accumulation Frame accumulation∗ SYNC sync Internal sync VD/HD sync Internal sync : SYNC sync : VD/HD sync : : : All other modes. HPLL (Open) VR/SYNC (Open) HPLL (Open) VR/SYNC (SYNC input) HPLL (HD input) VR/SYNC (VD input) Interlace EIA CCIR Valid only when NIL is high and EXT is low. Non-interlace 262H 312H EIA CCIR Internal sync : : 263H 313H External sync Valid only when EXT is low. Valid only when EXT is low and NIL is high. Switchover between internal and external sync is autonatically identified by input state at Pins 38, 39 and 40. ∗ The characteristics of CCD image sensors are quaranteed for field acccumulation operation. –6– CXD2400R Mode Tables 1) Internal sync mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : Open ESYNC pin (Pin 40) : Open Non-interlace Interlace Odd field∗2 Even field∗2 Field readout Frame readout∗3 Field readout Frame readout∗3 Field readout Frame readout∗3 XSUB pulse OFF∗1 O O O × O × Electronic shutter ON O O O × O × Electronic iris ON O O O × O × ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation O: Can be used. ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. ×: Cannot be used. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. 2) SYNC sync (external sync) mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : SYNC input ESYNC pin (Pin 40) : Open Non-interlace Interlace Even field∗2 Odd field∗2 Field readout Frame readout∗3 Field readout Frame readout∗3 Field readout Frame readout∗3 XSUB pulse OFF∗1 O O × × × × Electronic shutter ON O O × × × × Electronic iris ON O O × × × × ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. O: Can be used. ×: Cannot be used. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. –7– CXD2400R 3) VD/HD sync (external sync) mode HPLL pin (Pin 38) : HD input VR/SYNC pin (Pin 39) : VD input ESYNC pin (Pin 40) : VDD (power supply) VD input with normal cycle Non-interlace Interlace Odd field∗2 Even field∗2 Frame Field readout readout∗3 Frame Field readout readout∗3 Frame Field readout readout∗3 VD input with longer cycle than normal interlace Frame Field readout readout∗3 XSUB pulse OFF∗1 O O O × O × O × Serial input electronic shutter ON O O O × O × × × Parallel input electronic shutter ON O O ∆ × ∆ × × × Electronic iris ON O O O × O × × × ∗1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation ∗2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. ∗3 The characteristics of CCD image sensors are guaranteed for field accumulation operation. O: Can be used. ∆: The shutter speed may change from its value in the interlace mode. ×: Cannot be used. Note) Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin. –8– CXD2400R Electronic Shutter/Iris By setting ENB pin (Pin 14) high, the XSUB pulse is output for a specific period to activate the electronic shutter and electronic iris. 1) Electronic iris (IRENB = high, PS = any level) Symbol Pin No. Function IRIN/ED1 17 Iris signal input SPDNV/ED2 22 Shutter speed down reference voltage SPUPV/ED0 23 Shutter speed up reference voltage 2) Parallel input electronic shutter (IRENB = low, PS = high) Symbol Pin No. Mode SPUPV/ED0 23 H L H L H L H L IRIN/ED1 17 H H L L H H L L SPDNV/ED2 22 H H H H L L L L EIA: 1/100 CCIR: 1/120 1/250 1/500 1/1000 1/2000 1/5000 Shutter speed –9– 1/10000 1/100000 CXD2400R 3) Serial input electonic shutter (IRENB = low, PS = high) Serial input data format D7 SPDNV/ED2 D6 D5 D4 D3 D2 D1 D0 IRIN/ED1 SPUPV/ED0 The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA CCIR Load value shutter speed Load value shutter speed 00h 1/100000 00h 1/80000 4Eh 1/10000 4Ah 1/10000 6Ah 1/5000 65h 1/5000 87h 1/2000 82h 1/2000 9Ch 1/1000 97h 1/1000 ACh 1/500 A7h 1/500 CAh 1/250 C5h 1/250 EDh 1/100 E1h 1/120 AC Characteristics SPDNV/ED2 ts2 th2 IRIN/ED1 ts1 ts0 SPUPV/ED0 tw0 Symbol Min. Max. ts2 SPDNV (ED2) setup time for IRIN (ED1) rise 20ns — th2 SPDNV (ED2) hold time for IRIN (ED1) rise 20ns — ts1 IRIN (ED1) setup time for SPUPV (ED0) rise 20ns — tw0 SPUPV (ED0) pulse width 20ns 50µs ts0 SPUPV (ED0) setup time for IRIN (ED1) rise 20ns — – 10 – CXD2400R External Synchronization 1) External/internal sync selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. Input pattern VR/SYNC pin: SYNC signal VR/SYNC pin: VD signal VR/SYNC pin: Open HPLL pin: Open HPLL pin: HD signal HPLL pin: Open ESYNC pin: Open ESYNC pin: VDD (power supply) ESYNC pin: Open EXT pin output Sync state High High Low External sync External sync Internal sync Note) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization. 2) Modes for external synchronization Field accumulation Frame accumulation∗ O O × (Cannot be accomplished since interlace operation is the prior condition.) × (Cannot be accomplished since interlace operation is the prior condition.) Interlace O O Non-interlace O × (Not practically applicable since the sensitivity is halved.) Interlace SYNC synchronization VD/HD synchronization Non-interlace ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. 3) Reset operation SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA, V reset is performed so that the VDO pulse falls at the count of 259H (262.5 – 3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VDO pulse falls at the count of 309H (312.5 – 3.5H). For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VDO pulse falls 1H later after detecting the fall of the VD (VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDR pulse and HDO pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.) – 11 – – 12 – VDR VR1 HD1 SYNC VDO HDO VDR VR1 HD1 SYNC VDO HDO VDR VR1 HD1 SYNC VDO HDO VDR VR1 HD1 SYNC VDO HDO FIELD. O FIELD. E FIELD. O FIELD. E External Synchronization Reset Operation 7.5H FIELD. E 7.5H FIELD. O 9H FIELD. E 9H FIELD. O CCIR EIA CXD2400R – 13 – CLP2 CLP1 CCD. OUT XV4 XV2 XV3 XSG2 XV1 XSG1 FLD BLKO SYNC VDO HDO CLP2 CLP1 CCD. OUT XV4 XV2 XV3 XV1 XSG2 XSG1 FLD BLKO VDO SYNC HDO TG+SG Timing Chart V derection, EIA 493 492 FIELD. O 492 491 FIELD. E 493 FIELD. E 9H FIELD. O 9H 20H 20H 1 2 1 3 2 4 3 CXD2400R – 14 – CLP2 CLP1 CCD. OUT XV4 XV1 XV2 XV3 XSG2 XSG1 SYNC BLKO FLD VDO HDO CLP2 CLP1 CCD. OUT XV4 XV1 XV2 XV3 XSG2 FLD XSG1 BLKO SYNC VDO HDO TG+SG Timing Chart V derection, CCIR 583 583 582 FIELD. O 582 581 FIELD. E 14H 14.5H 7.5H FIELD. E 7.5H FIELD. O 25H 25H 1 3 2 2 1 CXD2400R – 15 – 14 14 VSYNC FLD 23 20 26 32 30 36 Black areas show OB output timing of CCD (ICX044/ICX054). 14 EQ VD 14 7 10 HSYNC XSUB XV4 XV3 XV2 XV1 CLP2 CLP1 SHD SHP RG H2 H1 MCK HD/BLK TG+SG Timing Chart H derection, EIA 38 40 44 50 50 55 56 59 62 60 68 73 70 80 80 90 94 103 100 104 MCK = 104.87ns CXD2400R – 16 – 14 FLD Black areas show OB output timing of CCD (ICX045/ICX055). 14 VSYNC VD 14 55 59 EQ 43 49 50 59 36 37 40 14 31 30 HSYNC 23 20 60 7 10 XSUB XV4 XV3 XV2 XV1 CLP2 CLP1 SHD SHP RG H2 H1 MCK HD/BLK TG+SG Timing Chart H derection, CCIR 60 61 67 73 70 77 80 84 90 98 100 107 114 MCK = 105.6ns CXD2400R – 17 – XV4 XV3 XV2 XV1 EVEN XV4 XV3 XV2 XV1 ODD XSG2 XSG1 HD TG+SG Timing Chart Charge Readout Timing Field accumulation E: 38.38µs (366CK) C: 38.65µs (3CK) E: 0.315µs C: 0.317µs (12CK) E: 1.26µs C: 1.27µs E: 2.51µs (24CK) C: 2.53µs E: 1.99µs (19CK) C: 2.0µs E: 1.57µs (15CK) C: 1.58µs C: CCIR 1CK = 105.6ns E: EIA 1CK = 104.87ns CXD2400R – 18 – E: 39.64µs C: 39.92µs (378CK) ∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation. XV4 XV3 XV2 XV1 EVEN XV4 XV3 XV2 XV1 ODD XSG2 XSG1 HD TG+SG Timing Chart Charge Readout Timing Frame accumulation (3CK) E: 0.315µs C: 0.317µs E: 2.51µs (24CK) C: 2.53µs C: CCIR 1CK = 105.6ns E: EIA 1CK = 104.87ns CXD2400R CXD2400R TG+SG Timing Chart ICX054AL 52.4ns (EIA) 52.8ns (CCIR) CK H1 26.2ns (EIA) 26.4ns (CCIR) RG CCD OUT SHP SHD – 19 – – 20 – FLD VD VSYNC EQ HSYNC BLKO HDO FLD VD VSYNC EQ HSYNC BLKO HDO 2.3µs (22CK) 4.75µs (45CK) 12.04µs (114CK) 6.23µs (59CK) 1.478µs (14CK) 2.3µs (22CK) 4.72µs (45CK) 10.9µs (104CK) 6.187µs (59CK) 1.468µs (14CK) CCIR EIA TG+SG High-Speed Phase Timing Chart H effective period 4.75µs (45CK) 4.72µs (45CK) 1/2H 1/2H 1.478µs (14CK) 1.468µs (14CK) 1CK = 105.6ns 1CK = 104.87ns CXD2400R 2.2k 1.5µ/25V – 21 – 100k 0.01µ 0.01µ 1T33C 10k 7p 2.7µH 10p 270p 7p 470 33p 1000p 6.8µ /6.3V 0.1µ 1 3 47p 47p 4 2.2k 47p 2.2k 100 7 8 CXD1250M/N 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 100 10k 2SC3355 0.1µ /6.3V 0.1µ 36k 6.8µ 6.8µ /6.3V 50k CCD OUT 0.15µ 27 IRIS 3.9k 150k 2SC945 270k 50k 20 24 21 30 4 29 VIDEO OUT CXA1310AQ 25 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 6 CXD2400R 5 VSUB ADJ 0.1µ 2 RG ADJ 6.8µ/6.3V 48 47 46 45 44 43 42 41 40 39 38 37 2.2k 36 35 34 33 32 31 30 29 28 27 26 25 250K-pixel B/W CCD SYNC IN 47p 2.2k Application <Sync input external synchronization + CCD iris mode> CXD2400R CXD2400R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 25 A 13 48 (0.22) 0.5 ± 0.2 (8.0) 24 37 12 1 + 0.05 0.127 – 0.02 0.5 ± 0.08 + 0.2 1.5 – 0.1 + 0.08 0.18 – 0.03 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 22 –