CXD2424R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2424R is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • CCIR support • Electronic shutter function • Random trigger shutter function • Sync signal generator • Supports external synchronization • Supports non-interlaced operation • Base oscillation 1888fh (29.5MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr –20 to +75 V °C Applicable CCD Image Sensors ICX075AL, ICX075AK Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95306-PS CXD2424R CL CLD O2FH FLD BLK SYNC HDO VDO HDI VDI REND EXT OCTL REVH RM RDM XCPDM XCPOB PBLK ID WEN Block Diagram 47 46 45 44 43 42 41 39 38 37 36 59 58 61 60 57 54 53 51 50 49 RG 11 XH1 13 XH2 14 XSHP 28 OUTPUT CONTROL TG G A T E 63 VRI 62 HRI 20 TEST1 V-CONTROL PULSE GENERATOR XSHD 29 H-DECODER V-DECODER 1/472 1/625 XRS 30 XV1 26 XV2 25 XV3 22 21 TEST2 XSG 27 31 TEST3 XHHG1A 15 1/2 COUNTER XHHG1B 16 XHHG2 17 DECODE XVOG 18 TEST CIRCUIT 24 40 55 29.5MHz –2– 56 VDD 23 Vss ED2 12 Vss ED1 9 VDD ED0 7 Vss 6 XSUB 5 SMD2 4 SMD1 3 PS TRIG 8 10 Vss OSCI CKI 2 OSCO GATE 1 TEST4 48 TEST8 35 TEST7 34 TEST6 XVHOLD 19 64 32 33 TEST5 52 NC CXD2424R REND EXT TEST7 TEST6 TEST5 REVH 43 42 OCTL XCPDM 44 VSS XCPOB 45 41 40 39 38 37 36 35 34 33 RDM PBLK 47 46 RM ID 48 WEN TEST8 Pin Configuration CL 49 32 TEST4 CLD 50 31 TEST3 O2FH 51 30 XRS 29 XSHD NC 52 FLD 53 28 XSHP BLK 54 27 XSG VSS 55 26 XV1 VDD 56 25 XV2 CXD2424R (G/A) SYNC 57 24 VDD HDI 58 23 VSS VDI 59 22 XV3 HDO 60 21 TEST2 VDO 61 20 TEST1 19 XVHOLD HRI 62 –3– 10 11 12 13 14 15 16 XHHG1B 9 XHHG1A SMD1 8 XH2 7 XH1 6 XSUB 5 RG 4 TRIG 3 SMD2 2 Vss 1 ED2 17 XHHG2 ED1 64 ED0 CKI PS 18 XVOG OSCI 63 OSCO VRI CXD2424R Pin Description Pin No. Symbol I/O Description 1 OSCO O Inverter output for oscillation. 2 OSCI I Inverter input for oscillation. 3 PS I Switching for electronic shutter speed input method. (With pull-down resistor) Low: Parallel input, High: Serial input 4 ED0 I Shutter speed setting. Strobe input for serial mode. (With pull-up resistor) 5 ED1 I Shutter speed setting. Clock input for serial input. (With pull-up resistor) 6 ED2 I Shutter speed setting. Data input for serial input. (With pull-up resistor) 7 SMD1 I Shutter mode setting. (With pull-up resistor) 8 Vss 9 SMD2 I Shutter mode setting. (With pull-up resistor) 10 TRIG I Trigger input for random trigger shutter. 11 RG O Reset gate pulse output. 12 XSUB O CCD discharge pulse output. 13 XH1 O Clock output for CCD horizontal register drive. 14 XH2 O Clock output for CCD horizontal register drive. 15 XHHG1A O Clock output for transfer between CCD horizontal registers. 16 XHHG1B O Clock output for transfer between CCD horizontal registers. 17 XHHG2 O Clock output for transfer between CCD horizontal registers. 18 XVOG O Clock output for transfer from CCD vertical register to CCD horizontal register. 19 XVHOLD O Clock output for adjusting timing of transfer to CCD horizontal register. 20 TEST1 O Test output. Normally open. 21 TEST2 O Test output. Normally open. 22 XV3 O Clock output for CCD vertical register drive. 23 Vss — GND 24 VDD — Power supply. 25 XV2 O Clock output for CCD vertical register drive. 26 XV1 O Clock output for CCD vertical register drive. 27 XSG O CCD sensor charge readout pulse output. 28 XSHP O Precharge level sample-and-hold pulse. 29 XSHD O Data sample-and-hold pulse. 30 XRS O Sample-and-hold pulse. 31 TEST3 O Test output. Normally open. 32 TEST4 O Test output. Normally open. 33 TEST5 O Test output. Normally open. 34 TEST6 O Test output. Normally open. 35 TEST7 I Test input. Set at Low in normal operation. (With pull-down resistor) — GND –4– CXD2424R Pin No. Symbol I/O Description 36 EXT I Internal synchronization/external synchronization switching. (With pull-down resistor) Low: Internal synchronization, High: External synchronization 37 REND I Normal reset/direct reset switching. (With pull-down resistor) Low: Normal reset, High: Direct reset 38 REVH I V reset/HV reset switching. (With pull-down resistor) Low: V reset, High: HV reset 39 OCTL I O2FH output control. (With pull-down resistor) Low: No output, High: Output 40 Vss 41 RDM I Normal operation/random trigger shutter switching. (With pull-down resistor) Low: Normal operation, High: Random trigger shutter 42 RM I Switching for output mode. (With pull-down resistor) Low: Non-interlaced, High: Interlaced 43 XCPDM O Clamp pulse output. 44 XCPOB O Clamp pulse output. 45 PBLK O Blanking cleaning pulse output. 46 ID O Line identification output. 47 WEN O Write enable output. 48 TEST8 I Test input. (With pull-down resistor) 49 CL O fck clock output. (0°) 50 CLD O fck clock output. (180°) 51 O2FH O 2 fH output. 52 NC — 53 FLD O Field pulse output. 54 BLK O Composite blanking output. 55 Vss — GND 56 VDD — Power supply. 57 SYNC O Composite sync output. 58 HDI I Horizontal sync signal input. 59 VDI I Vertical sync signal input. 60 HDO O Horizontal sync signal output. 61 VDO O Vertical sync signal output. 62 HRI I Horizontal reset signal input. 63 VRI I Vertical reset signal input. 64 CKI I 2 fck clock input. — GND –5– CXD2424R Electrical Characteristics DC Characteristics Item (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Symbol Conditions Min. Typ. Max. Unit 5.0 5.25 V Supply voltage VDD 4.75 Input voltage 1 (Input pins other than those below) VIH1 0.7VDD Input voltage 2 (Pins 7, 9, 10, 58, 59, 62, 63, and 64) VIH2 Output voltage 1 (Output pins other than those below) VOH1 IOH = –2mA VOL1 IOL = 4mA Output voltage 2 (Pins 28, 29, 30, 31, 32, 33, 34, 49 and 50) VOH2 IOH = –4mA VOL2 IOL = 8mA Output voltage 3 (Pins 11, 13, and 14) VOH3 IOH = –12mA VOL3 IOL = 12mA VOH4 IOH = –12mA VOL4 IOL = 12mA Feedback resistor RFB VIN = Vss or VDD Pull-up resistor RPU VIL = 0V 50k Ω Pull-down resistor RPD VIN = VDD 50k Ω Current consumption IDD VDD = 5V ICX075AL in normal operating state 40 mA Output voltage 4 (Pin 1) VIL1 0.3VDD 0.7VDD 0.3VDD –0.8 0.4 –0.8 V V 0.4 VDD – 0.8 VDD/2 250k Typ. Max. Unit Input pin capacitance CIN — — 9 pF Output pin capacitance COUT — — 11 pF V V 0.4 Min. –6– V V (VDD = V = 0V, fM = 1MHz) Symbol V V VIL2 I/O Pin Capacitances Item V V V 1M VDD/2 V 2.5M Ω CXD2424R AC Characteristics 1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD tCK CK Vpp/2 tpd1 XH1 tpd2 0.7VDD 0.3VDD tpd3 tpd4 0.7VDD RG 0.3VDD tpd6 tpd5 XSHP 0.7VDD 0.3VDD tpd8 tpd7 XSHD 0.7VDD 0.3VDD tpd10 tpd9 0.7VDD XRS 0.3VDD tpd11 tpd12 CL 0.7VDD 0.3VDD tpd14 tpd13 0.7VDD CLD 0.3VDD (VDD = 5.0V, Topr = 25°C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF) Symbol tCK tpd1 tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 Definition Typ. Unit CK cycle 35 ns XH1 rising delay, activated by the falling edge of CK 8 ns XH1 falling delay, activated by the falling edge of CK 9 ns RG falling delay, activated by the rising edge of CK 11 ns RG rising delay, activated by the falling edge of CK 15 ns XSHP falling delay, activated by the rising edge of CK 18 ns XSHP rising delay, activated by the falling edge of CK 18 ns XSHD falling delay, activated by the rising edge of CK 20 ns XSHD rising delay, activated by the falling edge of CK 11 ns XRS falling delay, activated by the falling edge of CK 17 ns XRS rising delay, activated by the rising edge of CK 15 ns CL falling delay, activated by the rising edge of CK 32 ns CL rising delay, activated by the rising edge of CK 0 ns CLD falling delay, activated by the rising edge of CK 26 ns CLD rising delay, activated by the falling edge of CK 20 ns –7– CXD2424R Waveform Characteristics of XH1 and RG 0.9VDD XH1 0.1VDD tfH1 trH1 0.9VDD RG 0.1VDD trRG tfRG (VDD = 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF) Symbol trH1 tfH1 trRG tfRG Definition Typ. Unit XH1 rise time 2 ns XH1 fall time 3 ns RG rise time 2 ns RG fall time 2 ns –8– CXD2424R • In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp1 tp3 fH tp4 VDO tp5 fH L: ODD H: EVEN 1 ODD 309.5H VDO 2 Symbol tp1 tp2 tp3 tp4 tp5 EVEN 309.5H Definition Specified value Unit Range of resetting to ODD 22.0 µs Range of resetting to EVEN 31.8 µs Range of resetting to ODD 9.8 µs Prohibited area 200 ns Prohibited area 200 ns –9– CXD2424R • In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp1 tp2 tp3 fH tp4 VDO 1 VDO 2 tp5 Symbol tp1 tp2 tp3∗1 tp4 tp5 fH L: ODD H: EVEN EVEN ODD Definition Specified value Unit Range of resetting to ODD 22.0 µs Range of resetting to EVEN 31.8 µs Range of resetting to ODD — µs Prohibited area 200 ns Prohibited area 200 ns ∗1 In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified. – 10 – CXD2424R Description of Operation 1. Mode Control Symbol Pin No. L H Remarks RM 42 1/25s non-interlaced 1/50s interlaced RDM 41 Normal operation Random trigger shutter PS 3 Parallel Serial EXT 36 Internal synchronization External synchronization REND 37 Normal reset Direct reset REVH 38 V reset HV reset Electronic shutter speed input method 2. Mode Relationships RM EXT RDM L H 1/25s non-interlaced 1/50s interlaced L H L H Internal synchronization External synchronization Internal synchronization External synchronization L H Normal operation Random trigger shutter REND Normal operation Direct reset REVH L H Normal operation Random trigger shutter Normal operation L H Normal reset Direct reset L H L H V reset HV reset V reset HV reset : Disabled – 11 – CXD2424R 3. Electronic Shutter <Shutter Modes> SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/50 Low-speed shutter: Shutter speed slower than 1/50 No shutter operation <Shutter Mode and Speed Setting Method> PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input Shutter Speed Compatibility Chart Mode PS SMD1 SMD2 ED0 ED1 ED2 Shutter speed OFF L H H X X X Shutter off Flickerless L L L X X X 1/120 (s) L L H H H H 1/50 (s) L L H L H H 1/125 (s) L L H H L H 1/250 (s) L L H L L H 1/500 (s) L L H H H L 1/1000 (s) L L H L H L 1/2000 (s) L L H H L L 1/4000 (s) L L H L L L 1/10000 (s) L H L H H H 2FLD L H L L H H 4FLD L H L H L H 6FLD L H L L L H 8FLD L H L H H L 10FLD L H L L H L 12FLD L H L H L L 14FLD L H L L L L 16FLD High-speed shutter Low-speed shutter – 12 – CXD2424R 3-2. Serial input • For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0. AC Characteristics ED2 ts2 th2 ED1 tw1 ts0 ts1 ED0 tw0 Definition Min. Max. ED2 set-up time, activated by the falling edge of ED1 20ns — ED2 hold time, activated by the rising edge of ED1 20ns — ED1 rising set-up time, activated by the rising edge of ED0 20ns — ED0 pulse width 20ns 50µs ED0 rising set-up time, activated by the rising edge of ED1 20ns — ED1 pulse width (serial input) 20ns — Symbol ts2 th2 ts1 tw0 ts0 tw1 – 13 – CXD2424R 3-3. Shutter speed calculation formula High-speed shutter T = [31210 – (1FF16 – L16)] × 64 + 35.6 (µs) (∗L16 = Load value) Load value Shutter speed Calculated value 0C816 1/10000 1/10040 0CA16 1/4000 1/4394 0CE16 1/2000 1/2068 0D616 1/1000 1/1004 0E616 1/500 1/495 10516 1/250 1/250 14316 1/125 1/125 14916 1/120 1/120 Low-speed shutter N = 2 × (1FF16 – L16) FLD However, “FF” cannot be used as the load value. Load value Shutter speed (FLD) 1FE16 2 1FD16 4 : : 10116 508 10016 510 Note) In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it. – 14 – CXD2424R 4. Random Trigger Shutter The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter. In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock (XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated. XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external trigger is detected and the signal is read out. When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point, exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in 1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the signal start, it can be used as the sync signal for writing image data into the frame memory. In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result, sync signals VD and FLD are also halted. TRIG HD reset HD XSG XSUB reset XSUB Shutter speed XV1 XV2 XV3 WEN – 15 – CXD2424R 5. External Synchronization - Reset HD and VD are reset to synchronize with the external sync signal. Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The CXD2424R has two reset modes: normal reset and direct reset. Details of the reset modes are described in the following pages. In the 1/25s non-interlaced readout mode, the normal reset mode is not supported, and although the direct reset mode is supported, the field is not identified. – 16 – CXD2424R 5-1. Normal reset In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from that time. Only the mode which resets both HD and VD (HV reset) is supported, and the mode which does not accept the HD reset (V reset) is not supported. When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (136ns) on the internal clock. In other words, the HRI input jitter is absorbed when it is up to 136 ns. The HRI minimum reset pulse width is 0.3µs. In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 312.5 – 3 = 309.5H. The VRI minimum reset pulse width is 2H. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics. FIELD.E FIELD.O HRI HDO VRI 7.5H VDO 309.5H FIELD.O FIELD.E HRI HDO VRI 7.5H VDO 309.5H H reset 57.6 to 57.7µs (850 to 851bit) HRI HD OUT Reset 6.3 to 6.37µs – 17 – CXD2424R 5-2. Direct reset In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no continuous output. There are two direct reset modes: one to direct reset VD only, and one to reset both HD and VD. (However, note that even for V reset, the HD signal is acceptable and the reset timing is the same as in normal reset mode.) In both modes, the VD reset timing is the same. When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V is reset to cause VDO to fall simultaneously in the middle of HD, and if EVEN, V is reset to cause VDO to fall simultaneously with HD fall. VRI requires a minimum pulse width of 2H. H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge. The minimum HRI reset pulse width is 0.3µs. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics. 5-2-1. V reset FIELD.E FIELD.O HRI HDO VRI 7.5H VDO FIELD.O FIELD.E HRI HDO VRI 7.5H VDO – 18 – CXD2424R 5-2-2. HV reset (1/50s interlaced readout mode) FIELD.E FIELD.O HDO HRI 7.5H VDO VRI XSG ID FIELD.O FIELD.E HDO HRI 7.5H VDO VRI XSG ID CL HRI HDO – 19 – CXD2424R 5-2-3. HV reset (1/25s non-interlaced readout mode) HDO HRI 7.5H VDO VRI XSG ID HDO HRI 7.5H VDO VRI XSG ID CL HRI HDO – 20 – XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 21 – 1 3 5 7 1 3 5 7 9 11 13 15 582 2 4 6 8 2 4 6 8 10 12 14 16 581 1 3 5 7 1 3 5 7 9 11 13 15 582 OUT2 2 4 6 8 2 4 6 8 10 12 14 16 OUT1 581 335 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CXD2424R Timing Chart (1) <Vertical direction> 1/50s interlaced readout (RM = High) FLD VDO BLK HDO XV1 XV2 XV3 CXD2424R Timing Chart (2) <Vertical direction> 1/25s non-interlaced readout (RM = Low) FLD VDO BLK 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 HDO XV1 XV2 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 22 – 1 2 3 4 5 6 7 8 1 2 3 581 582 1 2 3 4 5 6 7 8 1 2 3 4 OUT1 581 582 XV3 20 39 44 – 23 – WEN ID XCPDM XCPOB PBLK XSUB XSHD XSHP RG XH2 XH1 XHHG2 17 52 50 46 44 44 40 XHHG1B 30 44 OPB (38 bits) 10 XHHG1A XVOG XVHOLD XV3 XV2 XV1 CL BLK/HD 0 60 68 66 60 60 60 70 71 76 84 80 82 76 80 Timing Chart (3) <Horizontal direction> 1/50s interlaced readout (RM = High) 90 84 90 93 96 100 98 92 102 108 102 100 100 100 116 108 116 110 122 122 124 124 120 124 124 132 132 130 130 144 140 1 160 154 155 Dummy (19 bits) 150 177 180 19 OPB (3 bits) 170 CXD2424R – 24 – WEN ID XCPDM XCPOB PBLK XSUB XSHD XSHP RG XH2 XH1 XHHG2 XHHG1B XHHG1A XVOG XVHOLD XV3 XV2 XV1 CL BLK/HD 0 10 30 17 OPB (38 bits) 20 39 40 44 44 44 44 44 50 60 60 70 76 76 84 84 80 90 Timing Chart (4) <Horizontal direction> 1/25s non-interlaced readout (RM = Low) 93 102 100 100 116 116 110 122 122 124 124 120 130 130 132 144 140 160 1 154 155 19 Dummy (19 bits) 150 177 OPB (3 bits) 170 180 CXD2424R CXD2424R Timing Chart (5) <V2/V3 simultaneous readout timing> 1/50s interlaced (RM = High) HD 2.58µs (38 bits) 2.58µs (38 bits) 43.25µs (638 bits) ODD Field 15.59µs (230 bits) 3.25µs (48 bits) XV1 XV2 XV3 XSG EVEN Field XV1 XV2 XV3 XSG Timing Chart (6) <V2/V3 simultaneous readout timing> 1/25s non-interlaced (RM = Low) HD ODD Field 2.58µs (38 bits) 43.25µs (638 bits) 2.58µs (38 bits) 15.59µs (230 bits) XV1 XV2 XV3 XSG – 25 – 3.25µs (48 bits) CXD2424R Timing Chart (7) <High-speed phase> HD CKI CL XH1 XH2 RG XSHP XSHD XRS CLD – 26 – CXD2424R Timing Chart (8) <SG vertical direction> O: ODD E: EVEN Field E Field O HDO 7.5H VDO SYNC 25H BLK FLD Field O Field E HDO 7.5H VDO SYNC BLK 25H FLD – 27 – CXD2424R Timing Chart (9) <SG horizontal direction> HDO 6.92µs (102 bits) 12.0µs (177 bits) BLK HSYNC 1.48µs (22 bits) 4.93µs (73 bits) EQ 2.47µs (36 bits) 27.07µs (399 bits) VSYNC 4.93µs (73 bits) VDO FLD O2FH ODD 9.87µs (145 bits) EVEN 11.91µs (176 bits) 10.22µs (151 bits) 64.0µs (944 bits) 1/2H 32.0µs (472 bits) FH 9.87µs (146 bits) 22.13µs (326 bits) – 28 – CXD2424R Setting Up during Power ON During power on, after setting random trigger shutter mode once, switch to normal operation mode, and then use it. To be concrete, control supply voltage of two pins as shown below. The period to set random trigger shutter mode must be 1 clock (68ns) or more. Pin No. Symbol during power on Supply voltage of pin 7 SMD1 (with pull-up resistor) Low → High 41 RDM (with pull-down resistor) High (random trigger shutter) → Low (normal operation) <Timing Example> +5V power supply (TG power supply) SMD1 pin voltage Low RDM pin voltage High 68ns or more – 29 – 0.3VDD High 0.7VDD Low – 30 – 3 4 5 6 Input only for random trigger shutter mode. Refer to setting up during power on. 12p 20p 17 64 10/10V 0.01 CXD1250M ICX075AL CXD1268M 13 VSUB ADJ. CCD OUT2 CCD OUT1 21 22 14 24 15 13 21 22 14 CXA1690Q CXA1690Q DIGITAL OUT2 (10 bit) CXD2311AR 22 22 DIGITAL OUT1 (10 bit) CXD2311AR Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 74HC04 9 10 11 12 13 14 15 16 18 N.C. 63 8 20 N.C. 19 61 2.2K N.C. 62 7 21 N.C. 60 2.2K 22 47p 23 58 59 2.2K 24 57 47p To MEMORY CONTROLLER 2 25 56 1 26 55 CXD2424R 27 54 2.2K 28 53 47p 29 31 N.C. 30 47p 47p 47p N.C. 2.2K N.C. 52 2.2K +5V 10/10V 0.01 47p 2.2K 24 47p 2.2K 50 47p 2.2K 15 47p 2.2K 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 N.C. N.C. Refer to setting up during power on. N.C. N.C. 51 1000p ANALOG OUT1 ANALOG OUT2 Application Circuit (1/60s interlaced, internal synchronization, normal continuous operation) CXD2424R CXD2424R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 31 –