SONY CXD2720Q-2

CXD2720Q-2
Single-Chip Digital Signal Processor for Karaoke
Description
The CXD2720Q-2 is a digital signal processor LSI
for Karaoke, suitable for use in LD/CD/CD-G/video
CD and the like.
A large capacity DRAM and AD/DA converters are
built in, and Karaoke functions such as key control
and microphone echo are contained on a single
chip.
Features
• 3-channel 1-bit AD converter and decimation filter
S/N ratio: 88 dB
THD + N: 0.016%
Filter pass band ripple:
less than ±0.008dB
Filter stop band attenuation: less than –62dB
(all characteristics are typical values)
• 2-channel 1-bit DA converter and oversampling
filter
S/N ratio: 98dB
THD + N: 0.006%
Filter pass band ripple:
less than ±0.2dB
Filter stop band attenuation: less than –41dB
(all characteristics are typical values)
• In addition to analog input/output, 2-channel input/
2-channel output of digital input/output are provided.
The interface also supports a variety of formats.
• 128K-bit DRAM for key control and microphone
echo processing
Functions
• Key controller pitch setting can be varied to a
maximum of ±1 octave with a precision of 14 bits
• Two key controllers are provided.
For their pitches, either of common or independent
setting is possible
• Key controller can be used for voice
• Microphone echo delay time can be varied to a
maximum of 185ms (when fs = 44.1kHz)
• Voice parametric equalizer
• Mixing function to support sound multiplexing
software
• Digital de-emphasis function
• Soft mute function
100 pin QFP (Plastic)
Structure
Silicon gate CMOS
Applications
Equipment having Karaoke function, such as
LD/CD, compact music center, video games, etc.
Absolute Maximum Ratings
•
•
•
•
•
(Ta = 25°C, VSS = 0V)
Supply voltage
VDD VSS – 0.5 to +7.0
V
Input voltage
VI VSS – 0.5 to VDD + 0.5 V
Output voltage
VO VSS – 0.5 to VDD + 0.5 V
Operating temperature
Topr
–20 to +75
°C
Storage temperature Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.5 to 5.5 (5.0 typ.) V
• Operating temperature
Ta
–20 to +75
°C
Input/Output Capacitance
9 (max.)
pF
• Input capacitance
CIN
• Output capacitance
COUT 11 (max.)
pF
• Input/output capacitance CI/O 11 (max.)
pF
∗ Measurement conditions: VDD = VI = 0V, F = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97315-PS
CXD2720Q-2
Block Diagram
128K bit DELAY RAM
RVDT 3
SCK
4
XLAT
5
MICRO
COMPUTER
I/F
REDY 6
TRDT
25 AO1P
DAC1
7
26 AO1N
DAC2
39 AO2N
40 AO2P
ADC1
29 AIN1
ADC2
36 AIN2
ADC3
22 AIN3
DSP
LRCK 88
BCK 87
SERIAL
DATA
I/F
SI 86
SO 12
XWO
8
CLOCK GENERATOR
/TIMING CIRCUIT
33
82
32
XTLI XTLO BFOT
NC
NC
VSS4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD2
VSS5
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS6
Pin Configuration
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X768 81
50 NC
BFOT 82
49 NC
INVI 83
48
NC
NC 84
47
NC
NC 85
46 NC
SI 86
45
NC
BCK 87
44
NC
LRCK 88
43 VDD1
XMST 89
42 VSS3
VSS7 90
41
AVS5
NC 91
40 AO2P
NC 92
39 AO2N
NC 93
38 AVD5
NC 94
37 AVD2
NC 95
36 AIN2
NC 96
35 AVS2
NC 97
34 XVSS
NC 98
33
XTLI
–2–
AVD1
AIN1
AVS1
AVS4
AO1P
AO1N
AVD4
AIN3
AVD3
AVS3
VSS2
TST5
TRDT
TST3
REDY
TST4
XLAT
TST2
SCK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TST1
RVDT
8
TST0
7
XS24
6
SO
5
VDD0
4
VSS1
3
XWO
2
XRST
1
VSS0
32 XTLO
31 XVDD
AVS0
VDD3 99
AVD0 100
CXD2720Q-2
Pin Description
Pin
No.
Symbol
I/O
Description
1
AVS0
—
DRAM digital GND.
2
VSS0
—
Digital GND.
3
RVDT
I
Data input for microcomputer interface.
4
SCK
I
Shift clock input for microcomputer interface.
5
XLAT
I
Latch input for microcomputer interface.
6
REDY
O
Transmission enabling signal output for microcomputer interface. Transmission
prohibited when Low.
7
TRDT
O
Serial data output for microcomputer interface.
8
XWO
I
Window open input for synchronization. Normally High.
9
XRST
I
System reset input. Resets when Low.
10
VSS1
—
Digital GND.
11
VDD0
—
Digital power supply.
12
SO
O
1-sampling 2-channel serial data output.
13
XS24
I
Serial data 24-/32-bit slot selection. 24-bit slot when Low. (valid for slave mode)
14
TST0
I
Test pin. Normally set Low.
15
TST1
I
Test pin. Normally set Low.
16
TST2
I
Test pin. Normally set Low.
17
TST3
I
Test pin. Normally set Low.
18
TST4
I
Test pin. Normally set Low.
19
TST5
I
Test pin. Normally set Low.
20
VSS2
—
Digital GND.
21
AVS3
—
CH3 AD converter GND.
22
AIN3
I
23
AVD3
—
CH3 AD converter power supply.
24
AVD4
—
CH1 DA converter power supply.
25
AO1P
O
CH1 DA converter analog positive phase output.
26
AO1N
O
CH1 DA converter analog reversed phase output.
27
AVS4
—
CH1 DA converter GND.
28
AVS1
—
CH1 AD converter GND.
29
AIN1
I
CH1 AD converter analog input.
30
AVD1
—
CH1 AD converter power supply.
31
XVDD
—
Digital power supply for master clock.
32
XTLO
O
Crystal oscillator circuit output.
33
XTLI
I
Crystal oscillator circuit input.
34
XVSS
—
Digital GND for master clock.
35
AVS2
—
CH2 AD converter GND.
CH3 AD converter analog input (for microphone input).
–3–
CXD2720Q-2
Pin
No.
Symbol
I/O
Description
36
AIN2
I
CH2 AD converter analog input.
37
AVD2
—
CH2 AD converter power supply.
38
AVD5
—
CH2 DA converter power supply.
39
AO2N
O
CH2 DA converter analog reversed phase output.
40
AO2P
O
CH2 DA converter analog positive phase output.
41
AVS5
—
CH2 DA converter GND.
42
VSS3
—
Digital GND.
43
VDD1
—
Digital power supply.
44 to 52 NC
53
VSS4
Normally open.
—
54 to 68 NC
Digital GND.
Normally open.
69
VSS5
—
Digital GND.
70
VDD2
—
Digital power supply.
71 to 79 NC
Normally open.
80
VSS6
—
81
X768
I
Test input pin. Normally set Low.
82
BFOT
O
Clock, frequency-divider output (384fs).
83
INVI
I
Test pin. Normally set Low.
84
NC
Normally open.
85
NC
Normally open.
86
SI
87
BCK
I/O
Serial bit transmission clock for serial input/output data SI and SO.
88
LRCK
I/O
Sampling frequency clock for serial input/output data SI and SO.
89
XMST
I
90
VSS7
I
—
91 to 98 NC
Digital GND.
1-sampling 2-channel serial data input.
BCK, LRCK master/slave mode switching input. Master mode when Low.
Digital GND.
Normally open.
99
VDD3
—
Digital power supply.
100
AVD0
—
Digital power supply for DRAM.
–4–
CXD2720Q-2
DC Characteristics
(AVD0 to 5 = XVDD = VDD0 to 3 = 5V ± 10%, AVS0 to 5 = XVSS = VSS0 to 7 = 0V, Ta = –20 to +75°C)
Item
Input voltage (1)
Symbol
Conditions
Min.
Typ.
0.7VDD
High level VIH
Low level VIL
Input voltage (2)
∗1, ∗4, ∗5
V
∗3
0.2VDD
V
∗3
VDD
V
∗2
V
∗6, ∗7, ∗8
V
∗6, ∗7, ∗8, ∗9
V
∗10
V
∗10
V
∗11
VDD/2
V
∗11
0.8VDD
Low level VIL
Unit Applicable pins
∗1, ∗4, ∗5
V
V
0.3VDD
High level VIH
Input voltage (3)
Max.
Analog input
VSS
Output voltage High level VOH
(1)
Low level VOL
IOH = –2.0mA
VDD – 0.8
Output voltage High level VOH
(2)
Low level VOL
IOH = –6.0mA
Output voltage High level VOH
(3)
Low level VOL
IOH = –12.0mA
Input leak current (1)
II
VIH = VDD, VSS
–10
10
µA
∗1, ∗3, ∗5
Input leak current (2)
II
VIH = VDD, VSS
–40
40
µA
∗4
Output leak current
IOZ
VIH = VDD, VSS
–40
40
µA
∗8, ∗9
Feedback resistance
RFB
1M
2.5M
Ω
Resistance
between ∗5
and ∗11.
Current consumption
IDD
79
90
mA
VIN
IOL = 4.0mA
0.4
VDD – 0.8
IOL = 4.0mA
0.4
VDD/2
IOL = 12.0mA
250k
fs = 44.1kHz
∗1 RVDT, SCK, XLAT, XWO, XRST, XS24, TST0 to TST5, X768, SI, XMST
∗2 AIN1, AIN2, AIN3
∗3 INVI
∗4 During input to bidirectional pins BCK, LRCK
∗5 XTLI
∗6 During output from bidirectional pins BCK, LRCK
∗7 SO, BFOT
∗8 TRDT
∗9 REDY
∗10 AO1P, AO1N, AO2N, AO2P
∗11 XTLO
–5–
CXD2720Q-2
AC Characteristics
(AVD0 to 5 = XVDD = VDD0 to 3 = 5V±10%, AVS0 to 5 = XVSS = VSS0 to 7 = 0V, Ta = –20 to +75°C)
Serial Audio Interface Timing
[Slave mode]
0.7VDD
0.3VDD
BCK
tSSI
tHSI
0.7VDD
0.3VDD
SI
tDSSO
SO
tHLR
tSLR
0.7VDD
0.3VDD
LRCK
[Master mode]
BCK
tDLR
LRCK
tDMSO
SO
Item
SI setup time
SI hold time
SO delay time
LRCK setup time
LRCK hold time
LRCK delay time
SO delay time
Symbol
tSSI
tHSI
tDSSO
tSLR
tHLR
tDLR
tDMSO
Conditions
Min.
Max.
Unit
Slave mode
20
ns
Slave mode
40
ns
Slave mode, CL = 60pF
50
ns
Slave mode
20
ns
Slave mode
40
ns
Master mode, CL = 120pF
50
ns
Master mode, CL = 60pF
100
ns
–6–
CXD2720Q-2
Microcomputer Interface Timing
[Write]
• Transmission timing for address section, transmission mode section, data section LSB
RVDT
Address LSB
tSWL tSWH
0.7VDD
0.3VDD
Mode MSB
tDS
tDH
Data LSB
Data MSB
0.7VDD
0.3VDD
SCK
tSLP
tLSD
0.7VDD
0.3VDD
XLAT
tLWL
tLWH
REDY
• Transmission timing from data section MSB to address section and transmission mode section
RVDT
Data MSB
Address LSB
Mode MSB
0.7VDD
0.3VDD
tSS
0.7VDD
0.3VDD
SCK
tSLD
0.7VDD
0.3VDD
XLAT
tSBD
tLDR
tRLP
tBSP
REDY
[Read]
• Transmission timing for address section and transmission mode section is the same as for write.
RVDT
Address LSB
Mode MSB
tSS
0.7VDD
0.3VDD
SCK
tSLP
tRSDP
0.7VDD
0.3VDD
XLAT
tLWL
tLBD
0.7VDD
0.3VDD
REDY
tLDN
tSDD
Data LSB
TRDT
–7–
Data MSB
CXD2720Q-2
Item
Symbol
tDS
tDH
tSWL
tSWH
tLWL
tLWH
tSLP
tLSD
tLBD
tSBD
tBSP
tRLP
tRSDP
RVDT setup time relative to SCK rise
RVDT data hold time from SCK rise
SCK Low level width
SCK High level width
XLAT Low level width
XLAT High level width
SCK rise preceding time relative to XLAT rise
SCK rise wait time relative to XLAT rise
Delay time to REDY fall relative to XLAT rise.
Delay time to REDY fall relative to SCK rise
REDY fall preceding time relative to SCK rise
REDY rise preceding time relative to XLAT rise
REDY rise preceding time relative to SCK fall
XLAT fall wait time relative to SCK rise
XLAT fall delay time relative to REDY fall
Delay time from XLAT rise until TRDT data becomes active
Delay time from SCK rise until TRDT data becomes high-impedance
Delay time from SCK fall until TRDT data is verified
SCK rise wait time for next transmission
tSLD
tLDR
tLDN
tSDF
tSDD
tSS
Note 1) t is the cycle of 1/2 the clock frequency applied to the XTLI pin. (384fs)
Note 2) REDY and TRDT pins are the values for CL = 60pF.
–8–
Min.
Max.
Unit
20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
20
ns
3t + 20
ns
3t + 50
ns
4t + 50
ns
20
ns
20
ns
20
ns
3t + 20
ns
20
ns
2t + 40
3t + 80
ns
3t + 80
ns
2t + 70
ns
ns
CXD2720Q-2
Analog Characteristics (AVD0 to 5 = VDD0 to 3 = XVDD = 5.0V, AVS0 to 5 = VSS0 to 7 = XVSS = 0.0V, Ta = 25°C,
DSP: each function = OFF, gain = 1)
[1] ADC + DAC connection total characteristics
The measurement circuit in Figure 1-1 is used. Unless otherwise indicated, the measurement conditions are as
given below.
• Input signal ...1.0Vrms, 1kHz
• fs....................44.1kHz
• Rin .................0Ω
Item
S/N ratio
THD + N
Measurement conditions
Min.
Typ.
1.0Vrms, EIAJ (with “A” weighting filter)
80
88
1.0Vrms, EIAJ
0.016
0.5Vrms, EIAJ
0.012
Max.
Unit
dB
0.03
%
Dynamic range
EIAJ
92
dB
Channel separation
Only ADC characteristics using DAC1,
EIAJ
108
dB
Level difference between
channels
Only ADC characteristics using DAC1
0.05
dB
Rin = 0Ω
1.26
Rin = 22kΩ
2.06
Analog full-scale input level∗1
ADC input impedance
Analog current consumption
Vrms
34.6
kΩ
21
mA
∗1 Analog input level which outputs digital full scale.
An optional analog input signal level Vin (Vrms) of 1.26Vrms or more can be set in digital full scale by the
measurement circuit external resistor Rin.
The calculation formula for external resistor Rin is:
Rin = 27.5 × Vin – 34.6 [kΩ]......(1)
However, THD + N characteristics deteriorate for full-scale output as shown in Graph 1, so use of up to 80%
(when Rin = 0Ω, 0.8 × 1.26 (Vrms) = 1.0 (Vrms) → “analog full scale”) of the analog signal level is recommended
for digital full-scale output.
In this case, the Rin calculation formula is the same as formula (1), except that Vin becomes 1.25 × Vin.
Note that this change causes the output level after ADC + DAC to change.
Most of the above specifications are measurement values for analog full scale.
–9–
CXD2720Q-2
[2] DAC unit characteristics
Use the measurement circuit in Figure 1-2. Unless otherwise specified, the measurement conditions are as
follows.
• Input signal ....0dB, 1kHz, 16 bits
• fs....................44.1kHz
Item
Measurement conditions
S/N ratio
Min.
EIAJ (with “A” weighting filter)
Typ.
98
Max.
Unit
dB
EIAJ (0dB)
0.006
EIAJ (–1dB)
0.004
Dynamic range
EIAJ (–60dB)
98
dB
Channel separation
EIAJ
120
dB
Level difference between
channels
EIAJ
0.05
dB
Output level
EIAJ (Measure at OUT in Figure 1-2.)
2.0
Vrms
THD + N
THD + N [%]
1.00
0.10
(Rin = 0Ω)
Digital full scale
Analog full scale
0.01
–60
–50
–40
–30
–20
–10
Analog input level [dBV]
Graph 1.
– 10 –
0
10
(1Vrms)
%
CXD2720Q-2
CXD2720Q-2
(Master mode)
150p
10µ Rin
12k
22k
39k
AINx AOxN
Vin
2.2k
8200p
2.2k
OUT
330p
1M
AOxP
820p
12k
22k
39k
150p
Figure 1-1. ADC + DAC Measurement Circuit Diagram
CXD2720Q-2
(Slave mode)
768fs
48fs
fs
DATA
(fs = 44.1kHz)
150p
XTLI
BCK
12k
22k
39k
LRCK AOxN
2.2k
8200p
2.2k
330p
SI
AOxP
820p
12k
22k
39k
150p
Figure 1-2. DAC Measurement Circuit Diagram
– 11 –
OUT
CXD2720Q-2
Description of Functions
1. Master/Slave Modes
[Relevant pins] XMST, LRCK, BCK
When connecting multiple CXD2720Q-2s, or when using as a pair with a D/A converter such as the
CXD2558M, one of the CXD2720Q-2 should be in master mode to supply LRCK and BCK.
The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock
of the XTLI and XTLO pins or the external clock input from the XTLI pin
XMST
Mode
LRCK, BCK I/O
H
Slave mode
Input
L
Master mode
Output
Table 1-1. LRCK, BCK Mode Setting
2. Master Clock System
[Relevant pins] XTLI, XTLO, BFOT
768fs (fs = 44.1kHz) is assumed for the master clock system, and the connection is as shown below. (Please
inquire with regard to use at other than fs = 44.1kHz.)
(1) Master
O 384fs
BFOT
Frequency divider
I
XTLI
768fs
O
768fs
XTLO
(2) Slave
I
768fs
XTLI
768fs
O OPEN
XTLO
– 12 –
CXD2720Q-2
3. Input/Output Synchronization Circuit
[Relevant pins] LRCK, XWO
During normal operation, synchronization is performed automatically to input LRCK (in slave mode), and phase
is matched with serial input data, but if there is a lot of jitter on LRCK, or during power input, synchronization
may be impossible. In this case, forced synchronization can be done by making the XWO pin Low for 2/Fs or
more. Forced synchronization operation is done by the timing of the second LRCK rising edge after the XWO
pin is made Low. When synchronization is completed, return the XWO pin to High.
4. Reset Circuit
[Relevant pins] XRST, XTLI, XTLO
This LSI must be reset after power is turned ON.
Reset is done by making the XRST pin Low for 1/Fs or more after supply voltage satisfies the recommended
operating condition, and the crystal oscillator clock of the XTLI, XTLO pins or the external clock input from the
XTLI pin is correctly applied.
5. Serial Audio Interface (SIF)
[Relevant pins] SI, SO, BCK, LRCK, XS24, XMST
Serial data is used for the external communication of the digital audio data.
The CXD2720Q-2 has one system each for input and output, and each one inputs/outputs 2 channels of data
at 1 sampling cycles. Either the 32-bit clock mode or 24-bit clock mode can be selected. In master mode, the
32-bit clock mode is fixed.
(1) Pin Configuration
The pins shown in the table below are assigned to SIF.
Pin
name
I/O
SI
I
Serial input; taken synchronized to BCK.
SO
O
Serial output; output synchronized to BCK.
BCK
I/O
BCK input/output; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output
supports 32-bit clock mode only.
LRCK
I/O
LRCK input/output (1fs).
XS24
I
SI0 slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot. Valid only in slave
mode. Set High in master mode.
XMST
I
BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode.
Function
Table 5-1. Pin Configuration
– 13 –
CXD2720Q-2
(2) Operation Modes
The LRCK/BCK mode and SI/SO system settings can be selected by the setup register settings as follows.
LRCK/BCK Mode Setting
Setup register
Function
SQ11
SQ10
SQ09
LRCK format
LRCK polarity selection
BCK polarity selection relative to LRCK edge
Contents
“0” : normal,
“0” : Lch High,
“0” : edge↓,
“1” : IIS
“1” : Lch Low
“1” : edge↑
Table 5-2. LRCK/BCK Mode Setting
SI/O System Register Setting
SI system
Setup register
Function
SQ08
SQ07
SI data list
SI frontward/rearward truncation
SQ06
SQ05
SI data word length
SI data word length
Contents
“0” : MSB first,
“1” : LSB first
“0” : Forward truncation,
“1” : Rearward truncation
SQ06 SQ05
0
0
: 16 bits
1
1
: 24 bits
Table 5-3. SI System Register Setting
SO system
Setup register
Function
SQ04
SQ03
SO data list
SO forward/rearward truncation
SQ02
SQ01
SO data word length
Contents
“0” : MSB first,
“1” : LSB first
“0” : Forward truncation,
“1” : Rearward truncation
SQ02 SQ01
0
0
: 16 bits
0
1
: 18 bits
1
0
: 20 bits
1
1
: 24 bits
Table 5-4. SO System Register Setting
– 14 –
CXD2720Q-2
(3) SIF Format
Serial I/F have one input/output system each, and except for slot number, the following formats can be set
independently for input and output, by setting the setup register. It can also be made to support IIS format, to
enable connection to Philips and other devices. The timing charts for each data format are given on the
following pages.
32-bit slot (XS24 = High)
Setup register SQ05 SQ06 SQ07 SQ08
SI format
MSB first 24 bits Forward truncation
MSB first 16 bits Rearward truncation
LSB first 24 bits Rearward truncation
1
0
1
1
0
1
0
1
1
0
0
1
Supplement
Supports 20, 16 bits
Supports 20, 16 bits
Table 5-5. 32-bit Slot Serial IN
Setup register SQ01 SQ02 SQ03 SQ04
SO format
MSB first
MSB first
MSB first
MSB first
MSB first
LSB first
16 bits
18 bits
20 bits
24 bits
24 bits
24 bits
Rearward truncation
Rearward truncation
Rearward truncation
Rearward truncation
Forward truncation
Rearward truncation
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
Table 5-6. 32-bit Slot Serial OUT
24-bit slot (XS24 = Low)
Setup register SQ05 SQ06 SQ07 SQ08
SI format
MSB first 16 bits Rearward truncation
MSB first 24 bits
0
1
0
1
∗
0
0
LSB first
1
1
∗
1
24 bits
1
Supplement
Supports 20, 16 bits for forward
truncation
Supports 20, 16 bits for rearward
truncation
Table 5-7. 24-bit Slot Serial IN
Setup register SQ01 SQ02 SQ03 SQ04
SO format
MSB first
MSB first
MSB first
MSB first
LSB first
16 bits Rearward truncation
18 bits Rearward truncation
20 bits Rearward truncation
24 bits
24 bits
0
1
0
1
1
0
0
1
1
1
1
1
1
∗
∗
0
0
0
0
1
Table 5-8. 24-bit Slot Serial OUT
Note 1) When performing 20-bit and 16-bit data input in serial IN 24-bit data format, fill the lower 4 and 8 bits
with “0”, respectively.
Note 2) ∗ means “don't care”.
– 15 –
– 16 –
SI
23
22
21
20
LSB
00
01
02
03
MSB
• LSB first 24 bits
04
19
Invalid
• MSB first 24 bits
05
18
Invalid
MSB
LSB
06
17
07
16
15
14
08
15
09
14
MSB
10
13
13
11
12
12
Lch
12
11
11
13
10
10
14
09
09
15
08
08
16
07
07
17
06
06
18
05
05
19
04
04
20
03
03
00
00
LSB
23
22
23
00
01
MSB LSB
22
LSB MSB
01
01
Figure 5-1.
21
02
02
MSB
Rch
02
21
03
20
04
19
Invalid
Invalid
05
18
MSB
LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Invalid
06
17
LSB
07
16
15
14
08
15
09
14
MSB
10
13
13
11
12
12
12
11
11
Rch
13
10
10
14
09
09
15
08
08
16
07
07
17
06
06
18
05
05
19
04
04
20
03
03
21
02
02
00
23
LSB
00
LSB
MSB
22
01
01
MSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Invalid
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
• MSB first 16 bits rearward truncation
BCK
LRCK
Invalid
• LSB first 24 bits rearward truncation
Invalid
MSB
• MSB first 16 bits rearward truncation
24-bit slot
SI
Lch
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
• MSB first 24 bits forward truncation
BCK
LRCK
32-bit slot
Digital Audio Data Input Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
CXD2720Q-2
– 17 –
SO
14
16
15
14
22
21
20
LSB
00
01
02
03
MSB
• LSB first 24 bits
23
04
19
MSB
• MSB first 24 bits
19
05
18
18
06
17
17
07
16
16
08
15
15
09
14
14
MSB
• MSB first 20 bits rearward truncation
17
MSB
• MSB first 18 bits rearward truncation
15
LSB
LSB
" 0 " truncation
10
13
13
13
13
11
12
12
12
12
12
11
11
11
11
Lch
13
10
10
10
10
14
09
09
09
09
15
08
08
08
08
16
07
07
07
07
17
06
06
06
06
18
05
05
05
05
19
04
04
04
04
20
03
03
03
03
00
00
LSB
00
LSB
00
LSB
23
22
23
00
01
MSB LSB
22
02
21
19
MSB
03
20
04
19
05
18
LSB
LSB
" 0 " truncation
LSB
06
17
17
07
16
16
16
08
15
15
15
MSB
09
14
14
14
14
10
13
13
13
13
11
12
12
12
12
12
11
11
11
11
13
10
10
10
10
Rch
14
09
09
09
09
15
08
08
08
08
16
07
07
07
07
17
06
06
06
06
18
05
05
05
05
19
04
04
04
04
20
03
03
03
03
21
02
02
02
02
00
23
LSB
00
LSB
00
LSB
00
LSB
MSB
22
01
01
01
01
MSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MSB
18
LSB
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
MSB
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
LSB
MSB
17
15
" 0 " truncation
LSB MSB
01
01
01
01
MSB
Figure 5-2.
21
02
02
02
02
MSB
23
19
17
15
Rch
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
LSB
• MSB first 16 bits rearward truncation
BCK
24-bit slot
LRCK
LSB
18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
• LSB first 24 bits rearward truncation
" 0 " truncation
LSB
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
Lch
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
• MSB first 24 bits forward truncation
23
MSB
SO • MSB first 24 bits rearward truncation
19
• MSB first 20 bits rearward truncationMSB
17
• MSB first 18 bits rearward truncation
15
• MSB first 16 bits rearward truncation
BCK
LRCK
32-bit slot
Digital Audio Data Output Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
CXD2720Q-2
CXD2720Q-2
6. Microcomputer Interface
[Relevant pins] RVDT, TRDT, SCK, XLAT, REDY
The CXD2720Q-2 performs serial audio interface format setting, volume, coefficient settings of microphone
echo delay amount and others by serial data from the microcomputer.
Further, bidirectional communication such as internal data read from the CXD2720Q-2 to the microcomputer
can be done at the rate of once in 1 LRCK.
(1) Pin Structure
The five external pins indicated in the table below are allocated for microcomputer interface.
Microcomputer interface begins operation when XLAT is received, so RVDT, TRDT, SCK and REDY are
connected in common, and by controlling (wiring) only XLAT separately, multiple CXD2720Q-2s can be used.
Pin
name
I/O
RVDT
I
Serial data input from microcomputer.
TRDT
O
Serial data output to microcomputer. High impedance state unless this pin is set to internal
data read state by the microcomputer. Therefore, it is preferable to perform pull-up or pulldown so that potential is not unstable when this pin is not active.
SCK
I
Shift clock for serial data. Input data from RVDT is taken according to SCK rise, and output
data from TRDT is sent out according to SCK fall.
XLAT
I
Interprets the 8 bits of RVDT before this signal rises as transmission mode data, and the
bits before that as address data.
REDY
O
Transmission prohibited while at Low level. Transmission enabled at High. This pin is an
open drain, and must be pulled up externally.
Function
Table 6-1. Microcomputer Interface External Pins
– 18 –
CXD2720Q-2
(2) Description of Communication Formats
The data transmission timing between the microcomputer interface and coefficient RAM and setup register is
called the SV cycle, and is generated once in 1LRCK.
The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect
on signal processing, and there is no risk of the sound being cut.
In read/write modes,
Address section + Mode section + Data section
act as one package of data to perform data transmission between the microcomputer and the CXD2720Q-2.
[Write] • For coefficient RAM
Address section (8 bits)
RVDT
A0
A7
Mode section (8 bits)
M0
M7
Data section (16 bits)
D0
D15
SCK
XLAT
REDY
TRDT
[Read] • For coefficient RAM
Address section (8 bits) Mode section (8 bits)
RVDT
A0
A7
M0
M7
SCK
XLAT
REDY
Data section (16 bits)
TRDT
D0
Note) For both read and write, the data section is 24 bits for the setup register.
Figure 6-1. Examples of Communication
– 19 –
D15
CXD2720Q-2
(3) Data Structure
Data structure is classified in three types, as shown in the table below. All data communication is done with
LSB first.
Name
Bit length
Contents
Remarks
A0 to A7
8
Address section
M0 to M7
8
Transmission
mode section
D0 to D15/SQ00 to SQ23
16/24
Data section
Coefficient RAM is 16 bits; setup register is
24 bits
Table 6-2. Data Structure
(3)-1. Transmission Mode Section
The transmission mode section is 8 bits and has the following functions.
Bit
Name
M7
XVMT
Function
M6
Reserve
M5
M4
0: ON (No sound)
1: OFF
SO Mute
VS1
Data type
M3
VS0
M2
VS0
0
0
Setup register
Coefficient RAM (K-RAM)
Reserve
M1
M0
VS1
0
1
VRD
Send/Receive
0: Receive
1: Send
Note) Polarity as seen from the CXD2720Q-2
Table 6-3. Transmission Mode Section
(3)-2. Address Section
The coefficient RAM has a 192-word structure, so the address section is 8 bits. The setup register has a 1word structure, so the address section data may be optional.
(3)-3. Data Section
Sixteen SCK are required, as the coefficient RAM has a 16-bit structure (D0 to D15). The setup register has a
24-bit structure (SQ00 to SQ23), so twenty-four SCK are required.
– 20 –
CXD2720Q-2
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Write
First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to
the RVDT pin.
The address section data is 8 bits both for the coefficient RAM and setup register, and the setup register
transmits optional data for 1 word length. Address section data is sent with LSB first.
Mode section data is fixed at 8 bits regardless of content.
The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions:
• RV data must be verified before SCK rise (tDS ≥ 20ns).
• RV data must be held for 1t + 20ns or more after SCK rise (tDH).
SCK itself has the following restrictions:
• SCK Low level must be 1t+ 20ns or more (tSWL).
• SCK High level must also be 1t + 20ns or more (tSWH).
After raising SCK which corresponds to mode section final data, XLAT is raised (tSLP ≥ 20ns). XLAT Low level
width must be maintained at 1t + 20ns or more (tLWL). Further, fall timing restrictions are:
• for the preceding transmission, if REDY falls due to SCK, as for write, 3t + 20ns or more is required. (tSLD)
• for the preceding transmission, if REDY falls due to XLAT, as for read, 20ns or more is required. (tLDR)
Further, if preceding transmissions have been performed and REDY = Low, it is necessary to wait for REDY =
High to raise XLAT.
The procedure until this point is the same for write and read.
RVDT
A0
A7
M0
tDS
tDH
tSWL
tSWH
M7
D0/SQ00
D15/SQ23
SQ00
SQ23
A0
M7
tSS
SCK
tSLP
tLSD
tBSP
tSLP
XLAT
tSLD or tLWH
tLWL
tSLD
tLDR
tRLP
tSBD
REDY
TRDT
High-Z
Figure 6-2. Write Timing
– 21 –
tLDR
tRLP
CXD2720Q-2
Data section write begins after XLAT rise, and here also transmission must be with LSB first, with tDS and tDH
restrictions. In addition, after raising XLAT at the starting point for sending to the data section, wait for 3t +
20ns or more for the first SCK rise. (tLSD)
When 16 bits (coefficient RAM) or 24 bits (setup register) of this write is repeated, REDY = Low within 4t + 50ns,
and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle
by microcomputer interface. (tSBD)
When REDY goes High again, the corresponding data is written.
The next communication restarts by using the REDY signal as follows.
• When REDY = Low, the SCK for the next transmission can rise (tBSP ≥ 20ns ).
• In the same way, when REDY = Low, the XLAT for the next transmission can fall (tLDR ≥ 20ns).
REDY will fall due to this transmission, but it is prohibited for XLAT to rise for the next transmission before the
REDY rises. Be sure to raise the next XLAT after REDY rises (tRLP ≥ 20ns ).
In order to restart the next transmission without using the REDY signal, the following conditions must be observed:
• There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for
the next transmission (tSS).
• In the same way, the XLAT for the next transmission can fall after waiting 3t + 20ns or more after the final
data section SCK rise (tSLD).
The tss and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so the restriction conditions are not much strict.
However, even in this case the rise of XLAT for the next transmission must come after REDY rise (tRLP ≥
20ns).
Further, the restriction for XLAT fall at the starting point of this write from tSLD can be:
• tSLD ≥ 3t + 20ns if the preceding transmission was “write”.
– 22 –
CXD2720Q-2
(4)-2. Read
First, address section and mode section data are transmitted synchronized to SCK, and XLAT is raised
matched with this; the procedure until this point is the same as for write, so the description is omitted here.
Read differs from write in that after XLAT rise, REDY falls within 3t + 50ns (tLBD), and the microcomputer is
informed of SV cycle waiting.
At this time, the TRDT pin changes from high-impedance state to active state (tLDN ≤ 3t + 80ns) simultaneously
with REDY fall. When the read data is ready, the REDY pin changes from Low to High. When the data read out
from the TRDT pin is made TR, and SCK falls (tRSDP ≥ 20ns) when the REDY pin goes High, the first TR data
is defined within 2t + 70ns (tSDD). The microcomputer reads this data at SCK rise. The TR data is read in order
from the LSB with 16 bits for the coefficient RAM and 24 bits for the setup register by adding SCK, the
corresponding data is all read, and then read is completed.
Next, the method for restarting transmission after read is completed is described.
As in Case 1, there is a method for sending address section and mode section data consecutively after reading
all of the 16- or 24-bit data. There should be 2t + 40ns or more left between the SCK rise for the final data read
and the next SCK rise (tss), and this is established by the conditions tSWL ≥ 1t + 20ns and tSWH ≥ 1t + 20ns.
Further, at this read REDY changes from High to Low, but it is prohibited for the XLAT for the next
transmission to fall before this. If REDY = Low has been verified, XLAT can fall (tLDR ≥ 20 ns).
Also, while 16- or 24-bit data is being read from the TRDT pin, address and mode section data writing to the
RVDT pin for the next transmission can be started.
In Case 3, the final section of read data and the final data in the mode section overlap, and this allows shifting
to the next transmission processing in the shortest possible time after data read.
It is also possible to have data read and address and mode section write overlap partially, as shown in Case 2.
– 23 –
CXD2720Q-2
RVDT
A0
tDS
A7
M0
M7
A0
A1
M7
tDH
SCK
tSWL
tSWH
XLAT
tSLP
tLWL
tRSDP
tSLP
tLBD
tSLD or tLWH
REDY
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
A0
tDS
A7
M0
tSDD
SQ00
D0/SQ00
Case 1
RVDT
tSS
tSDD
SQ22
tSDF
SQ23
D14/SQ22 D15/SQ23
M7
A5
A6
M7
tDH
SCK
tSWL
tSWH
XLAT
tSLP
tLWL
tRSDP
tLBD
tSLD or tLWH
REDY
tSLP
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
A0
tDS
A7
M0
tSDD
SQ00
D0/SQ00
Case 2
RVDT
tSS
tSDD
SQ22
tSDF
SQ23
D14/SQ22 D15/SQ23
M7
M7
tDH
SCK
tSWL
XLAT
tSWH
tSLP
tLWL
tRSDP
tLBD
tSLD or tLWH
REDY
tSLP
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
tSDD
SQ00
D0/SQ00
Case 3
Figure 6-3. Read Timing
– 24 –
tSDD
SQ22
SQ23
D14/SQ22 D15/SQ23
CXD2720Q-2
7. Setup Register
When the setup register is selected for microcomputer interface transmission mode, the following settings are
possible for serial audio interface and DAC.
Data
section bit
Control
SQ23 to 12 Reserve bit
When system reset is Low
Must be Low for setup register setting
change
All Low
SQ11
LRCK format
0: normal
1: IIS
Normal
SQ10
LRCK polarity selection
0: Lch High
1: Lch Low
Lch High
SQ09
BCK polarity selection
relative to LRCK edge
0: Falling edge
1: Rising edge
Falling edge
SQ08
SI data list
0: MSB first
1: LSB first
(24-bit rearward truncation)
MSB first
SQ07
SI frontward/rearward
truncation
0: Frontward truncation
(valid only for MSB first/24 bits/32 slots) Frontward truncation
1: Rearward truncation
SQ06, 05
SI data word length
SQ06
0
1
SQ04
SO data list
0: MSB first
1: LSB first
LSB first
SQ03
SO frontward/rearward
truncation
0: Frontward truncation
1: Rearward truncation
Frontward truncation
SQ02, 01
SO data word length
SQ02
0
0
1
1
16 bits
SQ00
DAC forced mute
0: ON
1: OFF
SQ05
0
1
SQ01
0
1
0
1
: 16 bits
: 24 bits
: 16 bits
: 18 bits
: 20 bits
: 24 bits
16 bits
ON
Table 7-1.
– 25 –
CXD2720Q-2
8. Coefficient RAM Setting
When the coefficient RAM is selected in microcomputer interface transmission mode, the coefficient
parameters such as each section's volumes and microphone echo delay amount can be set. Data settings
other than those given following in Tables 8-1 and 8-2 are “don't care”.
(1) Fixed Values for System Initialization
When the system is initialized, the coefficient RAM must be set at the fixed values, shown below, for internal
operation.
Address
Fixed value
Address
Fixed value
fs = 44.1kHz
fs = 48kHz
fs = 32kHz
01H
68A9H
6A30H
623EH
36H
0000H
02H
5121H
5460H
447CH
3BH
0008H
fs = 44.1kHz
fs = 48kHz
03H
0000H
43H
0000H
19H
0000H
46H
0000H
1AH
0000H
48H
0001H
1BH
4000H
50H
0008H
1CH
4000H
72H
0092H
20H
0010H
73H
0209H
21H
4000H
74H
02CDH
23H
4000H
75H
0109H
24H
1600H
76H
FDA0H
25H
2A00H
77H
FD19H
26H
3FF8H
78H
0189H
27H
8000H
79H
058AH
28H
0000H
7AH
016DH
2DH
0008H
7BH
F7BEH
31H
4000H
7CH
F72AH
32H
1600H
7DH
0A4EH
33H
2A00H
7EH
2706H
34H
3FF8H
7FH
34EEH
35H
8000H
Table 8-1.
– 26 –
fs = 32kHz
CXD2720Q-2
(2) Setting Data
The relationships between the coefficient RAM and each function during DSP operation are as follows.
Address
Name
Function
Setting value
00H
Ki
SI data input level control
Refer to Table 12-1
04H
Ke
De-emphasis ON/OFF
Refer to Table 9
05H
DC1a1
DC cut1 coefficient for accompaniment
Refer to Table 14-1
06H
DC1a0
DC cut1 coefficient for accompaniment
Refer to Table 14-1
07H
DC1b
DC cut1 coefficient for accompaniment
Refer to Table 14-1
08H
DC2a1
DC cut2 coefficient for voice
Refer to Table 14-1
09H
DC2a0
DC cut2 coefficient for voice
Refer to Table 14-1
0AH
DC2b
DC cut2 coefficient for voice
Refer to Table 14-1
0BH
PEQa
PEQ coefficient for voice
Refer to Table 14-3
0CH
PEQb1
PEQ coefficient for voice
Refer to Table 14-3
0DH
PEQb2
PEQ coefficient for voice
Refer to Table 14-3
0EH
PEQg
PEQ coefficient for voice
Refer to Table 14-4
0FH
KisLm
SI CH1 data → Lch mix
Refer to Table 12-1
10H
KisRc
SI CH2 data → Lch mix
Refer to Table 12-1
11H
KiaLm
ADC CH1 data → Lch mix
Refer to Table 12-1
12H
KiaRc
ADC CH2 data → Lch mix
Refer to Table 12-1
13H
KisRm
SI CH2 data → Rch mix
Refer to Table 12-1
14H
KisLc
SI CH1 data → Rch mix
Refer to Table 12-1
15H
KiaRm
ADC CH2 data → Rch mix
Refer to Table 12-1
16H
KiaLc
ADC CH1 data → Rch mix
Refer to Table 12-1
17H
KiaML
ADC CH3 (Mic) data → Lch mix
Refer to Table 12-1
18H
KiaMR
ADC CH3 (Mic) data → Rch mix
Refer to Table 12-1
1DH
nRpR
Pitch ratio for Lch
Refer to Table 10-1
1EH
nRpR_R Pitch ratio for Rch
Refer to Table 10-1
1FH
Kp
Pitch ratio switching for LR independent/LR common
Common/8000H; independent/0000H
2EH
Ks
Key control ON/OFF
ON/8000H; OFF/0000H
3CH
KLf
Lch IIR4 output mix
Refer to Table 12-1
3DH
KRf
Rch IIR4 output mix
Refer to Table 12-1
3EH
KLpc
Lch pitch control output mix
Refer to Table 12-1
3FH
KRpc
Rch pitch control output mix
Refer to Table 12-1
40H
KLpt
Lch data → Echo mix
Refer to Table 12-1
41H
KRpt
Lch data → Echo mix
Refer to Table 12-1
42H
KdryE
Microphone PEQ output → Echo mix
Refer to Table 12-1
Table 8-2 (1). Coefficient RAM Setting Data (1/2)
– 27 –
CXD2720Q-2
Address
Name
Function
Setting value
44H
Tdo
Microphone echo delay amount
Refer to Table 12-1
45H
Kre
Microphone echo read tap volume
Refer to Table 12-2
47H
Tre
Microphone echo read tap address
Refer to Table 11-1
49H
Krd
Microphone echo input sound mix
Refer to Table 12-1
4AH
Kfb
Microphone echo reverberation sound mix
Refer to Table 12-1
4BH
HCa1
Microphone echo high cut
Refer to Table 14-2
4CH
HCa0
Microphone echo high cut
Refer to Table 14-2
4DH
HCb
Microphone echo high cut
Refer to Table 14-2
51H
KdryL
Microphone input direct sound Lch mix
Refer to Table 12-1
52H
KdryR
Microphone input direct sound Rch mix
Refer to Table 12-1
53H
Keff
Microphone input echo mix
Refer to Table 12-1
54H
KLm
Key control Lch data → Lch mix
Refer to Table 12-1
55H
KRm
Key control Rch data → Rch mix
Refer to Table 12-1
56H
KLmc
Key control Rch data → Lch mix
Refer to Table 12-1
57H
KRmc
Key control Lch data → Rch mix
Refer to Table 12-1
58H
KLo
System volume Lch
Refer to Table 12-1
59H
KRo
System volume Rch
Refer to Table 12-1
5AH
Kmut
Fade in/out Lch and Rch
Refer to Table 12-1
60H
IIR1a1
Pitch control input IIR_1 coefficient
Refer to Table 14-5
61H
IIR1a0
Pitch control input IIR_1 coefficient
Refer to Table 14-5
62H
IIR1b
Pitch control input IIR_1 coefficient
Refer to Table 14-5
63H
IIR2a1
Pitch control input IIR_2 coefficient
Refer to Table 14-5
64H
IIR2a0
Pitch control input IIR_2 coefficient
Refer to Table 14-5
65H
IIR2b
Pitch control input IIR_2 coefficient
Refer to Table 14-5
66H
IIR3a1
IIR_3 coefficient
Refer to Table 14-5
67H
IIR3a0
IIR_3 coefficient
Refer to Table 14-5
68H
IIR3b
IIR_3 coefficient
Refer to Table 14-5
69H
IIR4a1
IIR_4 coefficient
Refer to Table 14-5
6AH
IIR4a0
IIR_4 coefficient
Refer to Table 14-5
6BH
IIR4b
IIR_4 coefficient
Refer to Table 14-5
Table 8-2. Coefficient RAM Setting Data (2/2)
∗ Refer to 13. DSP Signal Flow regarding the names.
– 28 –
CXD2720Q-2
9. De-emphasis Settings
[Relevant coefficients] Ke (address = 04H)
Ke
OFF
ON
0000H
fs = 44.1kHz
AC19H
fs = 48kHz
AB50H
fs = 32kHz
B01DH
Table 9. Settings for De-emphasis ON/OFF Coefficients
– 29 –
CXD2720Q-2
10. Key Controller Setting
[Relevant coefficients] nRpR (address = 1DH), nRpR_R (addresas = 1EH), Kp (address = 1FH),
Ks (address = 2EH)
(1) Key Controller Pitch Ratio
nRpR (D15,.....,D2) is a 2’s complement format with a decimal point between D14 and D13, and sets the
desired pitch ratio directly. (VnRpR has the same type of setting as nRpR.)
15
nRpR = ∑Dn × 2n–14
n=2
The expression range for the pitch ratio is: –2.0 ≤ nRpR ≤ 2.0 – 2–12
but for practical use it is: –0.5 ≤ nRpR ≤ 1.0
or ±1 octave.
Use within a range of ± half an octave is recommended for quality of sound, although it depends on the aim
and the source.
Also, the algorithm is such that allophones will not be generated even when nRpR setting value is changed.
This applies to nRpR_R (Rch pitch ratio).
(2) L/R Common Setting and L/R Independent Setting of Pitch Ratio
The pitch ratio value can be set commonly or independently for Lch and Rch. It is recommended that the
common value be set when the key controller is used as the music key controller, and the independent values
be set when it is used as the voice effect.
Kp (address = 1FH) is used to switch the settings of the common value and independent values.
The common value is set when Kp is 8000H. nRpR (address = 1DH) is valid, and nRpR_R (address = 1EH)
setting value is invalid for both Lch and Rch in the pitch ratio.
The independent values are set when Kp is 0000H. nRPR is valid for Lch, and nRpR_R is valid for Rch in the
pitch ratio.
(3) Notes on Key Controller OFF
The pitch does not change when nRpR and nRpR_R are set to 0000H (OFF) when the key controller is OFF,
but depending on the internal state during OFF, there is no guarantee that the input value will be output as is.
During OFF, after setting nRpR and nRpR_R to 0000H (OFF), set the pitch control section to through state.
– 30 –
CXD2720Q-2
(4) Examples of Key Controller Setting
Examples of pitch ratio setting are illustrated below.
nRpR setting values are hexadecimal notation with D15 as MSB and D2 as LSB for a total of 14 bits.
(D1 and D0 can be optional data.)
CENT
nPpR, nRpR_R
CENT
nPpR, nRpR_R
0
0000H
0
0000H
+50
01E0H
–50
FE2EH
+100
03CEH
–100
FC69H
+150
05CAH
–150
FAB1H
+200
07D6H
–200
F905H
+250
09F1H
–250
F765H
+300
0C1BH
–300
F5D2H
+350
0E56H
–350
F44AH
+400
10A2H
–400
F2CCH
+450
12FFH
–450
F15AH
+500
156EH
–500
EFF3H
+550
17EEH
–550
EE95H
+600
1A82H
–600
ED42H
+650
1D29H
–650
EBF8H
+700
1FE4H
–700
EAB8H
+750
22B3H
–750
E980H
+800
2597H
–800
E852H
+850
2892H
–850
E72CH
+900
2BA2H
–900
E60EH
+950
2EC9H
–950
E4F9H
+1000
3208H
–1000
E3ECH
+1050
3560H
–1050
E2E6H
+1100
38D0H
–1100
E1E8H
+1150
3C5BH
–1150
E0F1H
+1200
4000H
–1200
E000H
Table 10-1. Pitch Ratio Setting Examples
The numeric representation format for pitch ratio here is:
15
nRpR = ∑Dn × 2n–14
n=2
The numeric representation range is: –2.0 ≤ nRpR ≤ 2.0 – 2–12
Also, the relationship formula with music word cent value C is:
C
nRpR = 2 1200 – 1, C = 1200 log2 [nRpR + 1] [cent]
The semitone at average ratio is 100 [cent].
– 31 –
CXD2720Q-2
11. Microphone Echo Delay Amount Setting
[Relevant coefficients] Tdo (address = 44H), Tre (address = 47H)
Microphone echo delay amount can be varied by setting coefficient Tdo (12 bits from D14 to D3) values. The
relationships between the coefficient and the delay amount differ depending on fs used as shown in Table 11-1.
Coefficient Tre (12 bits from D14 to D3) is microphone input echo initial delay time.
Set in the range of 0008H to Tdo.
Setting value Tdo
0008H
0010H
0018H
·
·
4096 step
·
·
7ff0H
7ff8H
0000H
Delay
fs = 44.1kHz
fs = 48kHz
fs = 32kHz
0.045ms
·
·
·
· 0.045ms/step
· setting possible
·
·
·
185.760ms
0.042ms
·
·
·
· 0.042ms/step
· setting possible
·
·
·
170.667ms
0.063ms
·
·
·
· 0.063ms/step
· setting possible
·
·
·
256.000ms
Table 11-1. Microphone Echo Delay Amount Setting
– 32 –
CXD2720Q-2
12. Input/Output Level Settings
[Relevant coefficients] Ki (address = 00H), KisLm (address = 0FH), KisRc (address = 10H),
KiaLm (address = 11H), KiaRc (address = 12H), KisRm (address = 13H),
KisLc (address = 14H), KiaRm (address = 15H), KiaLc (address = 16H),
Kre (address = 45H), Krd (address = 49H), Kfb (address = 4AH),
KLf (address = 3CH), KRf (address = 3DH), KLpc (address = 3EH),
KRpc (address = 3FH), KLpt (address = 40H), KRpt (address = 41H),
KdryE (address = 42H), KdryL (address = 51H), KdryR (address = 52H),
Keff (address = 53H), KLm (address = 54H), KRm (address = 55H),
KLmc (address = 56H), KRmc (address = 57H), KLo (address = 58H),
KRo (address = 59H), Kmut (address = 5AH)
The input/output levels and volumes are 2's complement format with a decimal point between D15 and D14,
and hexadecimal notation with D15 as MSB and D0 as LSB.
The coefficient and level relationships are as follows.
D15 to D0
Level
D15 to D0
Level
8000H
↓
FFFFH
0000H
0dB
↓
–90.31dB
–∞
8000H
↓
FFFFH
0000H
+12.04dB
↓
–78.27dB
–∞
Table 12-1. Input/Output Level Settings
(other than Kre)
Table 12-2. Input/Output Level Settings
(Kre)
The input/output levels for 8001H to FFFEH are determined by the following formulas.
14
(Coefficient value) = [ (–1) × D15 + ∑Dn × 2n–15] × (–1)
for other than Kre
n=0
14
(Coefficient value) = [ (–1) × D15 + ∑Dn × 2n–15] × (–4)
for Kre
n=0
Input/output level = 20log [coefficient value] dB
∗ D15 to D0 are negative values, but the calculation is (–1) × (D15 to D0).
∗ Kmut is the coefficient of the soft mute.
This approaches the specified value approximately every 45µs.
For example, when the output with its level of 0dB (8000H) is set to OFF (0000H), it takes approximately
1.49s to change from 8000H to 0000H.
– 33 –
– 34 –
SI2
SI1
AD2
AD1
00H
–Ki
04H
DeEmphasis
Decimation∗
ADC
–Ki
DeEmphasis
DC_Cut1
DC_Cut1
05 to 07H
PEQ
0B to 0EH
DC_Cut2
08 to 0AH
Decimation∗
∗75th FIR
Decimation∗
ADC
ADC
42H –KdryE
41H –KRpt
40H –KLpt
13H –KisRm
14H –KisLc
15H –KiaRm
16H –KiaLc
18H –KiaMr
10H –KisRc
0FH –KisLm
12H –KiaRc
11H –KiaLm
17H –KiaMl
∗ Refer to the coefficient RAM setting for information on each coefficient.
MIC
13. DSP Signal Flow
–Krd
Down
Sampling
49H
IIR_3
IIR_4
IIR_2
63 to 65H
60 to 62H
IIR_1
IIR_2
IIR_4
69 to 6BH
IIR_1
IIR_3
66 to 68H
4B to 4DH
High_Cut
–Kfb
4AH
Pitch
Control_R
1EH (1DH)
1FH, 2EH
1DH
Pitch
Control_L
Tdi
–KRf
45H
Tdo
44H
53H
–Keff
57H –KRmc
55H –KRm
52H –KdryR
56H –KLmc
54H –KLm
51H –KdryL
Over
Sampling
–Kre
Tre
47H
Delay Line
3FH
3EH
–KRpc
–KLpc
3CH
3EH
–KLf
5AH
Over
Sampling
Over
Sampling
–Kmut: Soft mute
59H
–KRo –Kmut
58H
–KLo –Kmut
DAC
DAC
DA2
SO2
DA1
SO1
CXD2720Q-2
CXD2720Q-2
14. Filter Coefficient Table
[Relevant coefficients] DC1a1 (address = 05H), DC1a0 (address = 06H), DC1b (address = 07H),
DC2a1 (address = 08H), DC2a0 (address = 09H), DC2b (address = 0AH),
PEQa (address = 0BH), PEQb1 (address = 0CH), PEQb2 (address = 0DH),
PEQg (address = 0EH), HCa1 (address = 4BH), HCa0 (address = 4CH),
HCb (address = 4DH), IIR∗b (address = 62, 65, 68, 6BH),
IIR∗a1 (address = 60, 63, 66, 69H), IIR∗a0 (address = 61, 64, 67, 6AH)
The cut-off frequencies and PEQ gain, Q, and center frequency settings for each signal flow filter are shown in
Tables 14-1 (1) to 14-5 (3).
Note) • If the above setting values are changed during DSP operation, the output level becomes unstable for
several 1/fs.
• The coefficients differ depending on fs used. Please inquire with regard to use at fs other than this
value.
(1) DC Cut1 for Accompaniment/ DC Cut2 for Voice
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
7FD1
7FBA
7FA2
7F8B
7F74
7F5D
7F46
7F2F
7F18
7F01
7EEA
7ED3
7EBC
7EA5
7E8E
7E77
7E61
7E4A
7E33
7E1C
7E06
7DEF
7DD9
7DC2
7DAC
802F
8046
805E
8075
808C
80A3
80BA
80D1
80E8
80FF
8116
812D
8144
815B
8172
8189
819F
81B6
81CD
81E4
81FA
8211
8227
823E
8254
7FA2
7F74
7F45
7F17
7EE9
7EBA
7E8C
7E5E
7E30
7E02
7DD4
7DA6
7D78
7D4B
7D1D
7CEF
7CC2
7C94
7C67
7C39
7C0C
7BDF
7BB2
7B85
7B58
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
OFF
7D95
7D7F
7D68
7D52
7D3B
7D25
7D0F
7CF8
7CE2
7CCC
7CB6
7CA0
7C8A
7C73
7C5D
7C47
7C31
7C1B
7C05
7BEF
7BDA
7BC4
7BAE
7B98
0000
826B
8281
8298
82AE
82C5
82DB
82F1
8308
831E
8334
834A
8360
8376
838D
83A3
83B9
83CF
83E5
83FB
8411
8426
843C
8452
8468
8000
7B2B
7AFE
7AD1
7AA4
7A77
7A4B
7A1E
79F1
79C5
7998
796C
7940
7914
78E7
78BB
788F
7863
7837
780B
77DF
77B4
7788
775C
7731
0000
Table 14-1 (1). Coefficients of DC Cut1 for Accompaniment / DC Cut2 for Voice (fs = 44.1kHz)
– 35 –
CXD2720Q-2
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
7FD5
7FBF
7FAA
7F95
7F7F
7F6A
7F55
7F40
7F2A
7F15
7F00
7EEB
7ED6
7EC1
7EAC
7E97
7E82
7E6D
7E58
7E43
7E2E
7E1A
7E05
7DF0
7DDB
802B
8041
8056
806B
8081
8096
80AB
80C0
80D6
80EB
8100
8115
812A
813F
8154
8169
817E
8193
81A8
81BD
81D2
81E6
81FB
8210
8225
7FAA
7F7F
7F54
7F2A
7EFF
7ED5
7EAA
7E80
7E55
7E2B
7E01
7DD7
7DAC
7D82
7D58
7D2E
7D04
7CDA
7CB1
7C87
7C5D
7C34
7C0A
7BE0
7BB7
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
OFF
7DC6
7DB2
7D9D
7D88
7D74
7D5F
7D4B
7D36
7D22
7D0D
7CF9
7CE4
7CD0
7CBB
7CA7
7C93
7C7E
7C6A
7C56
7C42
7C2D
7C19
7C05
7BF1
0000
823A
824E
8263
8278
828C
82A1
82B5
82CA
82DE
82F3
8307
831C
8330
8345
8359
836D
8382
8396
83AA
83BE
83D3
83E7
83FB
840F
8000
7B8D
7B64
7B3B
7B11
7AE8
7ABF
7A96
7A6D
7A44
7A1B
79F2
79C9
79A0
7977
794E
7926
78FD
78D5
78AC
7884
785B
7833
780A
77E2
0000
Table 14-1 (2). Coefficients of DC Cut1 for Accompaniment / DC Cut2 for Voice (fs = 48kHz)
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
Cut-off
frequency (Hz)
DC1a1
DC2a1
DC1a0
DC2a0
DC1b
DC2b
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
7FBF
7F9F
7F7F
7F5F
7F40
7F20
7F00
7EE0
7EC1
7EA1
7E82
7E63
7E43
7E24
7E05
7DE6
7DC6
7DA7
7D88
7D69
7D4B
7D2C
7D0D
7CEE
7CD0
8041
8061
8081
80A1
80C0
80E0
8100
8120
813F
815F
817E
819D
81BD
81DC
81FB
821A
823A
8259
8278
8297
82B5
82D4
82F3
8312
8330
7F7F
7F3F
7EFF
7EBF
7E80
7E40
7E01
7DC1
7D82
7D43
7D04
7CC6
7C87
7C48
7C0A
7BCC
7B8D
7B4F
7B11
7AD3
7A96
7A58
7A1B
79DD
79A0
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
OFF
7CB1
7C93
7C74
7C56
7C37
7C19
7BFB
7BDD
7BBF
7BA0
7B82
7B64
7B47
7B29
7B0B
7AED
7ACF
7AB2
7A94
7A77
7A59
7A3C
7A1E
7A01
0000
834F
836D
838C
83AA
83C9
83E7
8405
8423
8441
8460
847E
849C
84B9
84D7
84F5
8513
8531
854E
856C
8589
85A7
85C4
85E2
85FF
8000
7963
7926
78E9
78AC
786F
7833
77F6
77BA
777E
7741
7705
76C9
768E
7652
7616
75DB
759F
7564
7529
74EE
74B3
7478
743D
7403
0000
Table 14-1 (3). Coefficients of DC Cut1 for Accompaniment / DC Cut2 for Voice (fs = 32kHz)
– 36 –
CXD2720Q-2
(2) Microphone Echo High Cut
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
100E
1177
12D8
1432
1586
16D3
181A
195B
1A97
1BCE
1CFF
1E2C
1F55
2079
2199
22B5
23CE
24E3
25F4
2703
280E
2917
2A1D
2B21
2C22
2D21
2E1D
2F18
3011
3108
31FD
32F1
33E3
34D5
35C5
36B3
37A1
388E
397B
3A66
3B51
3C3B
3D26
3E0F
3EF9
3FE2
EFF2
EE89
ED28
EBCE
EA7A
E92D
E7E6
E6A5
E569
E432
E301
E1D4
E0AB
DF87
DE67
DD4B
DC32
DB1D
DA0C
D8FD
D7F2
D6E9
D5E3
D4DF
D3DE
D2DF
D1E3
D0E8
CFEF
CEF8
CE03
CD0F
CC1D
CB2B
CA3B
C94D
C85F
C772
C685
C59A
C4AF
C3C5
C2DA
C1F1
C107
C01E
5FE2
SD11
SA4E
579A
54F3
5259
4FCB
4D48
4AD0
4863
4600
43A6
4155
3F0D
3CCD
3A94
3863
3639
3416
31F9
2FE2
2DD0
2BC4
29BD
27BB
25BD
23C4
21CF
1FDD
1DEF
1C04
1A1C
1838
1655
1475
1298
10BC
0EE2
0D09
0B32
095C
0788
05B3
03E0
020D
003A
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
OFF
40CC
41B5
429F
4389
4173
455E
464A
4136
4822
4910
49FF
4AEE
4BDF
4CD1
4DC5
4EBA
4FB0
50A9
51A3
529F
539D
549E
55A1
56A6
57AE
58B9
59C7
5AD8
5BEC
5D03
5E1F
5F3E
6061
6188
62B4
63E4
651A
6654
6794
68DA
6A25
6B77
6CD0
6E2F
6F96
0000
BF34
BE4B
BD61
BC77
BB8D
BAA2
B9B6
B8CA
B7DE
B6F0
B601
B512
B421
B32F
B23B
B146
B050
AF57
AE5D
AD61
AC63
AB62
AA5F
A95A
A852
A747
A639
A528
A414
A2FD
A1E1
A0C2
9F9F
9E78
9D4C
9C1C
9AE6
99AC
986C
9726
95DB
9489
9330
91D1
906A
8000
FE68
FC95
FAC2
F8EE
F719
F543
F36C
F194
EFBB
EDE0
EC02
EA23
E841
E65D
E476
E28C
E09F
DEAE
DCBA
DAC1
D8C5
D6C4
D4BE
D2B3
D0A3
CE8E
CC72
CA50
C828
C5F9
C3C2
C184
BF3E
BCEF
BA98
B837
B5CC
B357
B0D7
AE4C
ABB5
A911
A660
A3A1
A0D4
0000
Table 14-2 (1). Coefficients of Microphone Echo High Cut (fs = 44.1kHz)
– 37 –
CXD2720Q-2
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
0EE4
1035
1180
12C4
1403
153C
1670
179E
18C7
19EC
1B0C
1C28
1D40
1E53
1F63
2070
2179
227E
2381
2480
257D
2677
276E
2863
2956
2A46
2B34
2C20
2D0A
2DF3
2ED9
2FBE
30A2
3184
3265
3345
3423
3500
35DD
36B8
3793
386C
3945
3A1E
3AF6
3BCE
F11C
EFCB
EE80
ED3C
EBFD
EAC4
E990
E862
E739
E614
E4F4
E3D8
E2C0
EIAD
E09D
DF90
DE87
DD82
DC7F
DB80
DA83
D989
D892
D79D
D6AA
D5BA
D4CC
D3E0
D2F6
D20D
D127
D042
CF5E
CE7C
CD9B
CCBB
CBDD
CB00
CA23
C948
C86D
C794
C6BB
C5E2
C50A
C432
6237
5F95
5CFF
5A76
57F8
5586
531F
50C3
4E70
4C26
49E6
47AE
457F
4358
4138
3F1F
3D0D
3B02
38FD
36FE
3504
3311
3122
2F38
2D53
2B73
2996
27BE
25EA
2419
224C
2082
1EBA
1CF6
1B35
1975
17B9
15FE
1445
128F
10D9
0F26
0D74
0BC2
0A12
0863
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
OFF
3CA5
3D7C
3E52
3F29
4000
40D6
41AD
4283
435A
4431
4509
45E1
46BA
4793
486C
4947
4A22
4AFF
4BDC
4CBA
4D9A
4E7B
4F5D
5041
5126
520C
52F5
53DF
54CB
SSB9
56A9
579C
5891
5988
5A82
5B7F
5C7E
5D81
5E86
5F8F
609C
61AC
62BF
63D7
64F3
0000
C35B
C284
C1AE
C0D7
C000
BF2A
BE53
BD7D
BCA6
BBCF
BAF7
BA1F
B946
B86D
B794
B6B9
B5DE
B501
B424
B346
B266
B185
B0A3
AFBF
AEDA
ADF4
AD0B
AC21
AB35
AA47
A957
A864
A76F
A678
A57E
A481
A382
A27F
A17A
A071
9F64
9E54
9D41
9C29
9B0D
8000
06B5
0507
035A
01AC
0000
FE54
FCA6
FAF9
F94B
F79D
F5EE
F43E
F28C
F0DA
EF27
ED71
EBBB
EA02
E847
E68B
E4CB
E30A
E146
DF7E
DDB4
DBE7
DA16
D842
D66A
D18D
D2AD
D0C8
CEDE
CCEF
CAFC
C902
C703
C4FE
C2F3
C0E1
BEC8
BCA8
BA81
B852
B61A
0000
Table 14-2 (2). Coefficients of Microphone Echo High Cut (fs = 48kHz)
– 38 –
CXD2720Q-2
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
Cut-off
frequency (Hz)
HCa1
HCa0
HCb
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
153C
1707
18C7
1A7D
1C28
1DCA
1F63
20F5
227E
2401
257D
26F3
2863
29CE
2B34
2C95
2DF3
2F4C
30A2
31F5
3345
3492
35DD
3725
386C
39B2
3AF6
3C39
3D7C
3EBE
4000
4141
4283
43C6
4509
464D
4793
48DA
4A22
4B6D
4CBA
4E0A
4F5D
50B3
520C
536A
EAC4
E8F9
E739
E583
E3D8
E236
E09D
DF0B
DD82
DBFF
DA83
D90D
D79D
D632
D4CC
D36B
D20D
D0B4
CF5E
CE0B
CCBB
CB6E
CA23
C8DB
C794
C64E
C50A
C3C7
C284
C142
C000
BEBF
BD7D
BC3A
BAF7
B9B3
B86D
B726
B5DE
B493
B346
B1F6
B0A3
AF4D
ADF4
AC96
5586
51F0
4E70
4B05
47AE
446A
4138
3E15
3B02
37FD
3504
3219
2F38
2C62
2996
26D4
2419
2166
1EBA
1C15
1975
16DB
1445
11B4
0F26
0C9B
0A12
078C
0507
0283
0000
FD7D
FAF9
F874
F5EE
F365
F0DA
EE4C
EBBB
E925
E68B
E3EB
E146
DE9A
DBE7
D92C
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
OFF
54CB
5631
579C
590C
5A82
5BFE
5D81
5F0A
609C
6235
63D7
6582
6738
68F8
6AC3
6C9B
6E7F
7072
7274
7486
76A9
78DF
7B29
7D88
7FFF
8290
853C
8805
8AEF
8DFB
912F
948B
9816
9BD3
9FC8
A3FA
A870
AD31
B247
B7BC
BD9B
C3F3
CAD3
D250
DA82
0000
AB35
A9CF
A864
A6F4
A57E
A402
A27F
A0F6
9F64
9DCB
9C29
9A7E
98C8
9708
953D
9365
9181
8F8E
8D8C
8B7A
8957
8721
84D7
8278
8001
7D70
7AC4
77FB
7511
7205
6ED1
6B75
67EA
642D
6038
5C06
5790
52CF
4DB9
4844
4265
3C0D
352D
2DB0
257E
8000
D66A
D39E
D0C8
CDE7
CAFC
C803
C4FE
C1EB
BEC8
BB96
B852
B4FB
B190
AE10
AA7A
A6CA
A301
9F1C
9B18
96F4
92AE
8E42
89AE
84EF
8001
7AE0
7588
6FF5
6A22
6409
5DA2
56E9
4FD3
4859
4070
380C
2F20
259D
1B71
1088
04CA
F81A
EA59
DB5F
CAFC
0000
Table 14-2 (3). Coefficients of Microphone Echo High Cut (fs = 32kHz)
– 39 –
CXD2720Q-2
(3) PEQ for Voice
Center
frequency (Hz)
PEQa
PEQb1
PEQb2
250.0
280.6
315.0
353.6
396.9
445.4
500.0
561.2
630.0
707.1
793.7
890.9
1000.0
1122.5
1259.9
1414.2
1587.4
1781.8
2000.0
2244.9
2519.8
2828.4
3174.8
3563.6
4000.0
4489.8
5039.7
5656.9
6349.6
7127.2
8000.0
023D
0282
02CF
0325
0385
03F0
0467
04EC
0580
0624
06DB
07A6
0886
097E
0A91
0BC0
0D0D
0E7C
100E
11C7
13A8
15B5
17F1
1A5E
1CFF
1FD8
22ED
2642
29DB
2DC1
31FD
7DAE
7D64
7D10
7CB2
7C47
7BCF
7B48
7AAE
7A01
793D
785E
7762
7643
74FD
738B
71E5
7004
6DE0
6B6D
68A1
656E
61C6
5D97
58CF
535A
4D24
4617
3E23
353B
2B5C
2097
847B
8505
859F
864B
870B
87E1
88CF
89D9
8B01
8C4A
8DB7
8F4D
910E
92FE
9524
9781
9A1C
9CFA
A01E
A38F
A752
AB6C
AFE4
B4BE
BA00
BFB2
C5DC
CC85
D3B8
DB84
E3FC
Gain
(dB)
PEQg
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
0000
01E5
03E7
0608
0849
0AAC
0D33
0FE1
12B7
15B8
18E7
1C46
1FD9
23A1
27A3
2BE2
3061
3524
3A30
3F88
4531
4B30
518A
5844
5F64
Table 14-4.
Table 14-3 (1). Coefficients of PEQ for Voice (fs = 44.1kHz)
– 40 –
CXD2720Q-2
Center
frequency (Hz)
PEQa
PEQb1
PEQb2
Center
frequency (Hz)
PEQa
PEQb1
PEQb2
250.0
280.6
315.0
353.6
396.9
445.4
500.0
561.2
630.0
707.1
793.7
890.9
1000.0
1122.5
1259.9
1414.2
1587.4
1781.8
2000.0
2244.9
2519.8
2828.4
3174.8
3563.6
4000.0
4489.8
5039.7
5656.9
6349.6
7127.2
8000.0
020F
024F
0295
02E5
033D
03A0
040E
0489
0512
05AA
0653
070F
07DF
08C6
09C5
0ADF
0C16
0D6C
0EE4
1080
1243
1430
1649
1892
1B0C
1DBC
20A5
23CA
2730
2ADE
2ED9
7DDF
7D9B
7D4E
7CF8
7C97
7C29
7BAD
7B21
7A82
79CF
7904
781E
7719
75F0
749F
7320
716B
6F79
6D41
6AB8
67D2
6181
60B6
5C61
576C
51C6
4B58
4410
3BDC
32B1
2893
8420
849F
852C
85CB
867C
8742
881E
8914
8A25
8B55
8CA8
8E1F
8FC0
918D
938B
95BF
982D
9AD9
9DC9
A101
A488
A861
AC94
B125
B61A
BB7A
C14B
C795
CE62
D5BD
DDB4
250.0
280.6
315.0
353.6
396.9
445.4
500.0
561.2
630.0
707.1
793.7
890.9
1000.0
1122.5
1259.9
1414.2
1587.4
1781.8
2000.0
2244.9
2519.8
2828.4
3174.8
3563.6
4000.0
4489.8
5039.7
5656.9
6349.6
7127.2
8000.0
0311
036E
03D7
074B
04CD
055D
05FE
06B0
0776
0852
0945
0A51
0B79
0CC0
0E27
0FB1
1161
1339
153C
176D
19CF
1C64
1F30
2237
257D
2907
2CDB
3103
3589
3A80
3FFF
7CC8
7C60
7BEC
7B68
7AD2
7A2A
796B
7892
779D
7686
754A
73E2
7248
7075
6E61
6C01
694A
662F
62A2
5E93
59EF
54A3
4E99
47BF
4000
374E
2DA6
2312
17B5
0BDA
0000
8623
86DE
87AF
8898
899B
8ABC
8BFD
8D62
8EEE
90A5
928B
94A4
96F4
9981
9C4F
9F64
A2C3
A673
AA7A
AEDC
B39F
B8C9
BE62
C470
CAFC
D20F
D9B8
E207
EB14
F502
0000
Table 14-3 (2). Coefficients of PEQ for Voice
(fs = 48kHz)
Table 14-3 (3). Coefficients of PEQ for Voice
(fs = 32kHz)
– 41 –
CXD2720Q-2
(4) First-Stage IIR Filter
Used as LPF
Cut-off
frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
16D3
1777
181A
18BB
195B
19FA
1A97
1B33
1BCE
1C67
1CFF
1D96
1E2C
1EC1
1F55
1FE7
2079
2109
2199
2228
22B5
2342
23CE
2459
24E3
256C
25F4
267C
2703
2789
280E
2893
2917
299A
2A1D
2A9F
2B21
2BA1
2C22
2CA1
2D21
E92D
E889
E7E6
E745
E6A5
E606
E569
E4CD
E432
E399
E301
E26A
E1D4
E13F
E0AB
E019
DF87
DEF7
DE67
DDD8
DD4B
DCBE
DC32
DBA7
DB1D
DA94
DA0C
D984
D8FD
D877
D7F2
D76D
D6E9
D666
D5E3
D561
D4DF
D45F
D3DE
D35F
D2DF
5259
5110
4FCB
4E88
4D48
4C0B
4AD0
4998
4863
4730
4600
44D2
43A6
427C
4155
4030
3F0D
3DEC
3CCD
3BAF
3A94
397B
3863
374D
3639
3527
3416
3306
31F9
30EC
2FE2
2ED8
2DD0
2CCA
2BC4
2AC0
29BD
28BC
27BB
26BC
25BD
Used as HPF
IIR∗a1 IIR∗a0
96D4
9778
981B
98BC
995C
99FB
9A98
9B34
9BCF
9C68
9D00
9D97
9E2D
9EC2
9F56
9EF8
A07A
A10A
A19A
A229
A2B6
A343
A3CF
A45A
A4E4
A56D
A5F5
A67D
A704
A78A
A80F
A894
A918
A99B
AA1E
AAA0
AB22
ABA2
AC23
ACA2
AD22
96D4
9778
981B
98BC
995C
99FB
9A98
9B34
9BCF
9C68
9D00
9D97
9E2D
9EC2
9F56
9FE8
A07A
A10A
A19A
A229
A2B6
A343
A3CF
A45A
A4E4
A56D
A5F5
A67D
A704
A78A
A80F
A894
A918
A99B
AA1E
AAA0
AB22
ABA2
AC23
ACA2
AD22
Used as LPF
Cut-off
IIR∗b frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
5259
5110
4FCB
4E88
4D48
4C0B
4AD0
4998
4863
4730
4600
44D2
43A6
427C
4155
4030
3F0D
3DEC
3CCD
3BAF
3A94
397B
3863
374D
3639
3527
3416
3306
31F9
30EC
2FE2
2ED8
2DD0
2CCA
2BC4
2AC0
29BD
28BC
27BB
26BC
25BD
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
10100
10200
10300
10400
10500
10600
10700
10800
10900
11000
OFF
2D9F
2E1D
2E9B
2F18
2F95
3011
308C
3108
3183
31FD
3277
32F1
336A
33E3
345C
34D5
354D
35C5
363C
36B3
372B
37A1
3818
388E
3905
397B
39F0
3A66
3ADC
3B51
3BC6
3C3B
3CB1
3D26
3D9A
3E0F
3E84
3EF9
3F6E
3FE2
0000
D261
D1E3
D165
D0E8
D06B
CFEF
CF74
CEF8
CE7D
CE03
CD89
CD0F
CC96
CC1D
CBA4
CB2B
CAB3
CA3B
C9C4
C94D
C8D5
C85F
C7E8
C772
C6FB
C685
C610
C59A
C524
C4AF
C43A
C3C5
C34F
C2DA
C266
C1F1
C17C
C107
C092
C01E
8000
24C0
23C4
22C9
21CF
20D5
1FDD
1EE6
1DEF
1CF9
1C04
1B10
1A1C
192A
1838
1746
1655
1565
1475
1386
1298
11A9
10BC
0FCF
0EE2
0DF5
0D09
0C1E
0B32
0A47
095C
0872
0788
069D
05B3
04CA
03E0
02F6
020D
0123
003A
0000
Table 14-5 (1). Coefficients of First-Stage IIR Filter (fs = 44.1kHz)
– 42 –
Used as HPF
IIR∗a1 IIR∗a0
ADA0
AE1E
AE9C
AF19
AF96
B012
B08D
B109
B184
B1FE
B278
B2F2
B36B
B3E4
B45D
B4D6
B54E
B5C6
B63D
B6B4
B72C
B7A2
B819
B88F
B906
B97C
B9F1
BA67
BADD
BB52
BBC7
BC3C
BCB2
BD27
BD9B
BE10
BE85
BEFA
BF6F
BFE3
0000
ADA0
AE1E
AE9C
AF19
AF96
B012
B08D
B109
B184
B1FE
B278
B2F2
B36B
B3E4
B45D
B4D6
B54E
B5C6
B63D
B6B4
B72C
B7A2
B819
B88F
B906
B97C
B9F1
BA67
BADD
BB52
BBC7
BC3C
BCB2
BD27
BD9B
BE10
BE85
BEFA
BF6F
BFE3
8000
IIR∗b
24C0
23C4
22C9
21CF
20D5
1FDD
1EE6
1DEF
1CF9
1C04
1B10
1A1C
192A
1838
1746
1655
1565
1475
1386
1298
11A9
10BC
0FCF
0EE2
0DF5
0D09
0C1E
0B32
0A47
095C
0872
0788
069D
05B3
04CA
03E0
02F6
020D
0123
003A
0000
CXD2720Q-2
Used as LPF
Cut-off
frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
153C
15D6
1670
1707
179E
1833
18C7
195A
19EC
1A7D
1B0C
1B9B
1C28
1CB4
1D40
1DCA
1E53
1EDC
1F63
1FEA
2070
20F5
2179
21FC
227E
2300
2381
2401
2480
24FF
257D
25FA
2677
26F3
276E
27E9
2863
28DD
2956
29CE
2A46
EAC4
EA2A
E990
E8F9
E862
E7CD
E739
E6A6
E614
E583
E4F4
E465
E3D8
E34C
E2C0
E236
E1AD
E124
E09D
E016
DF90
DF0B
DE87
DE04
DD82
DD00
DC7F
DBFF
DB80
DB01
DA83
DA06
D989
D90D
D892
D817
D79D
D723
D6AA
D632
D5BA
5586
5452
531F
51F0
50C3
4F98
4E70
4D4A
4C26
4B05
49E6
48C9
47AE
4696
457F
446A
4358
4247
4138
402A
3F1F
3E15
3D0D
3C07
3B02
39FE
38FD
37FD
36FE
3600
3504
340A
3311
3219
3122
302D
2F38
2E45
2D53
2C62
2B73
Used as HPF
IIR∗a1 IIR∗a0
IIR∗b
953D
95D7
9671
9708
979F
9834
98C8
995B
99ED
9A7E
9B0D
9B9C
9C29
9CB5
9D41
9DCB
9E54
9EDD
9F64
9FEB
A071
A0F6
A17A
A1FD
A27F
A301
A382
A402
A481
A500
A57E
A5FB
A678
A6F4
A76F
A7EA
A864
A8DE
A957
A9CF
AA47
5586
5452
531F
51F0
50C3
4F98
4E70
4D4A
4C26
4B05
49E6
48C9
47AE
4696
457F
446A
4358
4247
4138
402A
3F1F
3E15
3D0D
3C07
3B02
39FE
38FD
37FD
36FE
3600
3504
340A
3311
3219
3122
302D
2F38
2E45
2D53
2C62
2B73
953D
95D7
9671
9708
979F
9834
98C8
995B
99ED
9A7E
9B0D
9B9C
9C29
9CB5
9D41
9DCB
9E54
9EDD
9F64
9FEB
A071
A0F6
A17A
A1FD
A27F
A301
A382
A402
A481
A500
A57E
A5FB
A678
A6F4
A76F
A7EA
A864
A8DE
A957
A9CF
AA47
Used as LPF
Cut-off
frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
10100
10200
10300
10400
10500
10600
10700
10800
10900
11000
OFF
2ABD
2B34
2BAA
2C20
2C95
2D0A
2D7F
2DF3
2E66
2ED9
2F4C
2FBE
3030
30A2
3113
3184
31F5
3265
32D5
3345
33B4
3423
3492
3500
356E
35DD
364A
36B8
3725
3793
3800
386C
38D9
3945
39B2
3A1E
3A8A
3AF6
3B62
3BCE
0000
D543
D4CC
D456
D3E0
D36B
D2F6
D281
D20D
D19A
D127
D0B4
D042
CFD0
CF5E
CEED
CE7C
CE0B
CD9B
CD2B
CCBB
CC4C
CBDD
CB6E
CB00
CA92
CA23
C9B6
C948
C8DB
C86D
C800
C794
C727
C6BB
C64E
C5E2
C576
C50A
C49E
C432
8000
2A84
2996
28AA
27BE
26D4
25EA
2501
2419
2332
224C
2166
2082
1F9E
1EBA
1DD8
1CF6
1C15
1B35
1A55
1975
1897
17B9
16DB
15FE
1522
1445
136A
128F
11B4
10D9
0FFF
0F26
0E4D
0D74
0C9B
0BC2
0AEA
0A12
093B
0863
0000
Table 14-5 (2). Coefficients of First-Stage IIR Filter (fs = 48kHz)
– 43 –
Used as HPF
IIR∗a1 IIR∗a0
AABE
AB35
ABAB
AC21
AC96
AD0B
AD80
ADF4
AE67
AEDA
AF4D
AFBF
B031
B0A3
B114
B185
B1F6
B266
B2D6
B346
B3B5
B424
B493
B501
B56F
B5DE
B64B
B6B9
B726
B794
B801
B86D
B8DA
B946
B9B3
BA1F
BA8B
BAF7
BB63
BBCF
0000
AABE
AB35
ABAB
AC21
AC96
AD0B
AD80
ADF4
AE67
AEDA
AF4D
AFBF
B031
B0A3
B114
B185
B1F6
B266
B2D6
B346
B3B5
B424
B493
B501
B56F
B5DE
B64B
B6B9
B726
B794
B801
B86D
B8DA
B946
B9B3
BA1F
BA8B
BAF7
BB63
BBCF
8000
IIR∗b
2A84
2996
28AA
27BE
26D4
25EA
2501
2419
2332
224C
2166
2082
1F9E
1EBA
1DD8
1CF6
1C15
1B35
1A55
1975
1897
17B9
16DB
15FE
1522
1445
136A
128F
11B4
10D9
0FFF
0F26
0E4D
0D74
0C9B
0BC2
0AEA
0A12
093B
0863
0000
CXD2720Q-2
Used as LPF
Cut-off
frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
1DCA
1E98
1F63
202D
20F5
21BA
227E
2341
2401
24C0
257D
2639
26F3
27AC
2863
2919
29CE
2A82
2B34
2BE5
2C95
2D45
2DF3
2EA0
2F4C
2FF8
30A2
314C
31F5
329D
3345
33EB
3492
3537
35DD
3681
3725
37C9
386C
390F
39B2
E236
E168
E09D
DFD3
DF0B
DE46
DD82
DCBF
DBFF
DB40
DA83
D9C7
D90D
D854
D79D
D6E7
D632
D57E
D4CC
D41B
D36B
D2BB
D20D
D160
D0B4
D008
CF5E
CEB4
CE0B
CD63
CCBB
CC15
CB6E
CAC9
CA23
C97F
C8DB
C837
C794
C6F1
C64E
446A
42CF
4138
3FA4
3E15
3C8A
3B02
397D
37FD
367F
3504
338D
3219
30A7
2F38
2DCC
2C62
2AFB
2996
2834
26D4
2575
2419
22BF
2166
200F
1EBA
1D67
1C15
1AC5
1975
1828
16DB
1590
1445
12FC
11B4
106C
0F26
0DE0
0C9B
Used as HPF
IIR∗a1 IIR∗a0
IIR∗b
9DCB
9E99
9F64
A02E
A0F6
A1BB
A27F
A342
A402
A4C1
A57E
A63A
A6F4
A7AD
A864
A91A
A9CF
AA83
AB35
ABE6
AC96
AD46
ADF4
AEA1
AF4D
AFF9
B0A3
B14D
B1F6
B29E
B346
B3EC
B493
B538
B5DE
B682
B726
B7CA
B86D
B910
B9B3
446A
42CF
4138
3FA4
3E15
3C8A
3B02
397D
37FD
367F
3504
338D
3219
30A7
2F38
2DCC
2C62
2AFB
2996
2834
26D4
2575
2419
22BF
2166
200F
1EBA
1D67
1C15
1AC5
1975
1828
16DB
1590
1445
12FC
11B4
106C
0F26
0DE0
1C9B
9DCB
9E99
9F64
A02E
A0F6
A1BB
A27F
A342
A402
A4C1
A57E
A63A
A6F4
A7AD
A864
A91A
A9CF
AA83
AB35
ABE6
AC96
AD46
ADF4
AEA1
AF4D
AFF9
B0A3
B14D
B1F6
B29E
B346
B3EC
B493
B538
B5DE
B682
B726
B7CA
B86D
B910
B9B3
Used as LPF
Cut-off
frequency (Hz) IIR∗a1 IIR∗a0 IIR∗b
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
10100
10200
10300
10400
10500
10600
10700
10800
10900
11000
OFF
3A54
3AF6
3B98
3C39
3CDB
3D7C
3E1D
3EBE
3F5F
4000
40A0
4141
41E2
4283
4324
43C6
4467
4509
45AB
464D
46F0
4793
4836
48DA
497E
4A22
4AC8
4B6D
4C14
4CBA
4D62
4E0A
4EB3
4F5D
5007
50B3
515F
520C
52BA
536A
0000
C5AC
C50A
C468
C3C7
C325
C284
C1E3
C142
C0A1
C000
BF60
BEBF
BE1E
BD7D
BCDC
BC3A
BB99
BAF7
BA55
B9B3
B910
B86D
B7CA
B726
B682
B5DE
B538
B493
B3EC
B346
B29E
B1F6
B14D
B0A3
AFF9
AF4D
AEA1
ADF4
AD46
AC96
8000
0B56
0A12
08CF
078C
0649
0507
03C5
0283
0141
0000
FEBF
FD7D
FC3B
FAF9
F9B7
F874
F731
F5EE
F4AA
F365
F220
F0DA
EF94
EE4C
ED04
EBBB
EA70
E925
E7D8
E68B
E53B
E3EB
E299
E146
DFF1
DE9A
DD41
DBE7
DA8B
D92C
0000
Table 14-5 (3). Coefficients of First-Stage IIR Filter (fs = 32kHz)
– 44 –
Used as HPF
IIR∗a1 IIR∗a0
IIR∗b
BA55 BA55
BAF7 BAF7
BB99 BB99
BC3A BC3A
BCDC BCDC
BD7D BD7D
BE1E BE1E
BEBF BEBF
BF60 BF60
C000 C000
C0A1 C0A1
C142 C142
C1E3 C1E3
C284 C284
C325 C325
C3C7 C3C7
C468 C468
C50A C50A
C5AC C5AC
C64E C64E
C6F1 C6F1
C794 C794
C837 C837
C8DB C8DB
C97F C97F
CA23 CA23
CAC9 CAC9
CB6E CB6E
CC15 CC15
CCBB CCBB
CD63 CD63
CE0B CE0B
CEB4 CEB4
CF5E CF5E
D008 D008
D0B4 D0B4
D160 D160
D20D D20D
D2BB D2BB
D36B D36B
0000 8000
0B56
0A12
08CF
078C
0649
0507
03C5
0283
0141
0000
FEBF
FD7D
FC3B
FAF9
F9B7
F874
F731
F5EE
F4AA
F365
F220
F0DA
EF94
EE4C
ED04
EBBB
EA70
E925
E7D8
E68B
E53B
E3EB
E299
E146
DFF1
DE9A
DD41
DBE7
DA8B
D92C
0000
CXD2720Q-2
Filter Characteristics
ADC Filter Characteristics (75th + 15th FIR)
Stop band
Pass band
50.00
0.00
40.00
–10.00
–20.00
–30.00
20.00
–40.00
10.00
Response [dB]
Response [dB × 10–3]
30.00
0.00
–10.00
–20.00
–30.00
–50.00
–60.00
–70.00
–80.00
–90.00
–40.00
–100.00
–50.00
–110.00
–60.00
–120.00
–130.00
–70.00
0
5
10
15
Frequency [kHz]
1fs
20 22.05
(1/2fs)
2fs
Frequency [kHz]
DAC Filter Characteristics (43rd + 7th FIR)
Stop band
Pass band
0.00
500.00
400.00
–10.00
300.00
–20.00
–30.00
100.00
Response [dB]
Response [dB × 10–3]
200.00
0.00
–100.00
–200.00
–300.00
–40.00
–50.00
–60.00
–70.00
–400.00
–500.00
–80.00
–600.00
–90.00
–700.00
–800.00
–100.00
0
5
10
15
1fs
20
Frequency [kHz]
Frequency [kHz]
– 45 –
2fs
: DA operational amplifier +12V power supply
: AD operational amplifier –12V power supply
: DA operational amplifier –12V power supply
2
3
4
XTAI
SIN
DA16
BCK
DA15
LRCK
LRCK
CXD2500Q
DGND
DGND
0.01
NC
NC
NC
NC
CXD2720Q-2
DGND
DGND
83
81 82
80 VSS6
79 NC
78 NC
77 NC
76 NC
75 NC
74 NC
73 NC
72 NC
71 NC
70 VDD2
69 VSS5
68 NC
67 NC
66 NC
65 NC
64 NC
63 NC
62 NC
88
94
91 92 93
DGND
0.01
DGND
89 90
97
95 96
B
AGND
E
AGND
D
AGND
3
2
SCK
RVDT
VSS0
DGND DGND
0.01
AVS0
1
5
4
XLAT
7
6
TRDT
Microcomputer
XWO
8
REDY
XRST
9
XWO
DGND
DGND
0.01
DGND
DGND
DGND
0.01
AGND
0.01
AGND
0.01
XRST
VSS1 10
VDD0 11
SO 12
XS24 13
TST0 14
TST1 15
TST2 16
TST3 17
TST4 18
TST5 19
99 100
0.01
98
60 NC
86 87
AIN3 22
AVS3 21
59 NC
84 85
AVD3 23
58 NC
VSS2 20
AVD4 24
61 NC
AO1P 25
56 NC
AO1N 26
55 NC
57 NC
AVS4 27
54 NC
X768
INVI
BFOT
DGND
NC
AVS1 28
BCK
53 VSS4
XMST
DGND
SI
AIN1 29
AVD1 30
31
32
34 33
36 35
38 37
39
42 41 40
43
44
46 45
49 48 47
VSS3
52 NC
51 NC
C
0.01 0.01
F
50
DGND AGND
NC
5532 operational amplifier used
0.01
AVS5
VSS7
: AO2 +5V power supply
20p AGND
768fs
A
0.01
AGND AGND
NC
20p
AGND
NC
AVD5
NC
: Digital power supply +5V
AGND AGND
NC
NC
NC
NC
F
DGND
VDD1
NC
E : AO1 +5V power supply
AO2P
AIN2
NC
D : AIN3 +5V power supply
AO2N
NC
B : AIN1 +5V power supply
AVD2
XVSS
NC
– 46 –
AVD0
C : AIN2 +5V power supply
AVS2
A : Crystal oscillator circuit +5V power supply
: AD operational amplifier +12V power supply
1
XTLI
LRCK
XVDD
XTLO
VDD3
Application Circuit
22k
22k
22k
22k
12k
12k
100p
6 39k
AGND
5
100k
6
5
100p
AGND
5
100k
6
7
7
7
7
7
1.8k
10k
1.8k
1.8k
10k
3
2
3
2
3
2
3
2
3
2
AGND
1200p
2200p
1.8k
AGND
220p
1000p
10k
AGND
1200p
2200p
1.8k
AGND
1200p
2200p
1.8k
AGND
220p
1000p
10k
3
1
4
2
3
1
3
1
4
2
4
8
4
8
4
8
4
8
4
8
0.01
AGND
AGND
1
10µ
1M
CH1 OUT
AGND
1M
AGND
330k
AGND
1M
AGND
AGND
10µ 4.7k
0.01
0.01
AGND
AGND
1
10µ 4.7k
0.01
0.01
AGND
AGND
1
CH2 OUT
AGND
330k
AGND
10µ 4.7k
0.01
0.01
AGND
AGND
1
0.01
0.01
10µ
0.01
AGND
AGND
1
Application circuits shown are typical examples illustrating the operation of
the devices. Sony cannot assume responsibility for any problems arising out
of the use of these circuits or for any infringement of third party patent and
other right due to same.
AGND
CH3 IN
6
5
100k
AGND
AGND AGND
39k
AGND
CH1 IN
AGND
CH2 IN
6 39k
5
100p
AGND AGND
39k
220p
12k
12k
220p
100p
CXD2720Q-2
CXD2720Q-2
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
(16.3)
0.15
0° to 15°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
SONY CODE
QFP-100P-L01
EIAJ CODE
∗QFP100-P-1420-A
JEDEC CODE
– 47 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
Sony Corporation