SONY CXD3152AR

CXD3152AR
Signal Processor LSI for Single-chip CCD B/W Camera
Description
The CXD3152AR is a digital signal processor LSI
for CCD black-and-white cameras. In addition to the
CDS and AGC circuits of conventional analog signal
processor LSI, this chip also features the ease of use
and functions of digital signal processing.
Features
• Supports 510H/760H system CCD image sensors
• Supports EIA/CCIR modes
• Built-in CDS and AGC circuits
• Built-in 10-bit A/D converter
• Built-in 9-bit D/A converter
• Analog and digital signal output
• Right/left inverted (mirror image) output function
• Horizontal and vertical aperture correction function
• Gamma correction curve variable function
• Serial communication function (I2C bus)
• Supports external sync functions
(when using the CXD2463R)
— Line lock/Vreset HPLL
• Supports backlight compensation functions
(when using the CXD2463R)
• Character input pin
• Blemish detection and compensation function
64 pin LQFP (Plastic)
Applications
Various CCD black-and-white cameras
Applicable CCD Image Sensors∗
510H system CCDs (Type 1/3, 1/4 EIA/CCIR)
760H system CCDs (Type 1/2, 1/3, 1/4 EIA/CCIR)
Supported Related LSIs
TG
: CXD2463R
EEPROM : S-24C01B
(Seiko Instruments Co., Ltd.)
or equivalent product
∗
Applicable CCD Image Sensors are applicable products as of
preparing this data sheet. They may be changed according to
the version up and production stop of CCD image sensor.
Absolute Maximum Ratings
• Supply voltage VDD (3.3V) VSS – 0.3 to +4.6
V
VDD (5.0V) VSS – 0.3 to +6.0
V
• Input voltage VI (3.3V) VSS – 0.3 to VDD3 + 0.3 V
VI (5.0V) VSS – 0.3 to VDD5 + 0.3 V
• Output voltage VO (3.3V) VSS – 0.3 to VDD3 + 0.3 V
VO (5.0V) VSS – 0.3 to VDD5 + 0.3 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +125
°C
Recommended Operating Conditions
• Supply voltage VDD (3.3V)
3.0 to 3.6
VDD (5.0V)
4.75 to 5.25
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E03551B46
5
6
7
8
YOUT
YIN
CAPB2
GOUT 64
IRISOUT
CLP
AGC
DAC
AMP
CDS
54
Gamma
27
AMP
SW
15, 16
3H Memory
Blemish
Correction
HV
AP. Con
13, 14
CLP
Blemish
Detector
GAIN
Y. Gain
PED
BLK
WC
CSYNC
Over
Sampling
9bit DAC
Register
37, 33, 34
44 to 48, 50 to 52
41, 42, 40
10
V. follower
10bit ADC
AGC Controller
Timing
Generator
SHP
SHD
MONITOR
3, 4
Sync
Separator
59
CSYNC_IN
REFHIN,
REFLIN
CAP1,
CAPA2
BLCW1, 2
AGC,
DGC
60, 61, 25, 26
SDA,
SCL,
REGRES
REFH,
REFL
2
58, 57
2MCKI
55
Y0 to Y7
GAIN
MIRROR
–2–
CHARA
CCDIN
CCD,
EIA
63, 62
PREF,
CVREF,
COMP
Block Diagram
39, 38
ANA,
ANAB
CXD3152AR
CXD3152AR
Description of Functions by Block
CDS & AGC
• CDS
VDD1 = 5.0V
SHD/SHP external input: <SHD/SHP>
Brightness signal output for iris detection: <IRISOUT>
• AGC
VDD2 = 5.0V
AGC gain variable range: 6 to 19dB (typ.)
The gain is controlled by the 8-bit DAC for DC voltage generation.
Manual setting possible by the register
A/D Converter
• ADC
10 bits
VDD3 = 3.3V
The input block clamp circuit pulse is generated internally, and external input is impossible.
Built-in voltage follower for the reference voltage
Digital Signal Processing
• DGC
DGC (digital gain control) operates at the maximum AGC (analog gain control) gain.
The gain can be controlled from 0 to approximately 8 times.
The aperture signal coring level is automatically controlled in conjunction with the gain.
• MIRROR
Right/left inverted output possible <MIRROR>
• APCON
Horizontal and vertical aperture correction circuit
The circuit can be turned on and off by the setting pin. <APCON>
Fine adjustment possible by the register
The position at which the aperture correction signal is added can be switched to before or after gamma.
• Gamma correction
4 patterns can be selected by the setting pins. <GAMMA1, GAMMA2>
7-line approximation
Adjustable by the register
• Oversampling
Sampling frequency selectable from 2MCKI or (2MCKI/2)
• PED
Standard setting: 7.5 IRE
Adjustable by the register
• Character input
A 1-bit signal from an external pin can be added to the luminance signal. <CHARA>
The gain can be set by the register.
• Blemish detection and compensation function
Up to a total of 10 white point blemishes can be detected and compensated during dark signal.
Blemish addresses can be read out by serial communication.
• Digital output
8-bit digital signal output
–3–
CXD3152AR
D/A Converter
• DAC
9 bits
VDD6 = 3.3V
Supports –40 to +130 IRE output
Timing Generation
• Timing
Generation of various DSP internal signal processing pulses
Input clock frequencies:
EIA (510 × 492)
: 19.06993MHz
CCIR (500 × 582) : 18.9375MHz
EIA (768 × 494)
: 28.63636MHz
CCIR (752 × 582) : 28.375MHz
Slave operation according to the sync signal <CSYNC_IN> from an external TG: Composite sync input
Gain Control
Built-in auto gain control circuit
The maximum AGC (analog gain control) and DGC (digital gain control) gains can be set individually by the
registers.
AGC and DGC can be turned on and off individually by external pins. <AGC, DGC>
The gain control time constants can be set by the registers.
Supports backlight compensation
Registers
• I2C bus
Various register settings: <SCL, SDA, REGRES>
Slave address: [A6:A0] = 0011111 (b)
Related pins: <SCL, SDA, REGRES>
• External EEPROM
An EEPROM which supports the I2C bus can be connected.
Register values can be automatically read out during power-on.
–4–
CXD3152AR
Y4
Y3
Y2
Y1
Y0
OEB
SCL
SDA
REGRES
ANA
ANAB
RREF
VDD6 (3.3V)
VSS6
COMP
CVREF
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS7 49
32 VSS5
Y5 50
31 MCKPHS
Y6 51
30 GAMMA2
Y7 52
29 GAMMA1
MCKO 53
28 APCON
CHARA 54
27 MIRROR
2MCKI 55
26 DGC
VDD7 (3.3V) 56
25 AGC
EIA 57
24 VDD5 (3.3V)
CCD 58
23 DEFECT
CSYNC_IN 59
22 TEST
BLCW1 60
21 VSS4
BLCW2 61
20 VDD4 (3.3V)
SHD 62
19 REFBIAS
SHP 63
18 VDD3 (3.3V)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CCDIN
CAP1
CAPA2
IRISOUT
YOUT
YIN
CAPB2
VSS1
MONITOR
VSS2
VDD2 (5V)
REFHIN
REFLIN
REFH
REFL
17 VSS3
VDD1 (5V)
GOUT 64
–5–
CXD3152AR
Pin Description
Pin
No.
Symbol
Description
I/O
1
VDD1
P
Analog power supply (5.0V)
2
CCDIN
I
Image signal input from CCD
3
CAP1
O(A)
CDS DC bias output
Connect to GND via an approximately 0.1µF capacitor.
4
CAPA2
O(A)
Gain control amplifier DC bias output
Connect to GND via an approximately 0.1µF capacitor.
5
IRISOUT
O(A) Image signal output for iris detection
6
YOUT
O(A) AGC image signal output
7
YIN
I(A)
Image signal input to ADC
Normally input YOUT via an approximately 0.1µF capacitor.
8
CAPB2
I(A)
ADC input clamp level (DC) input
High reference (REFHIN) reference level
9
VSS1
10
MONITOR
11
VSS2
P
Analog GND
12
VDD2
P
Analog power supply (5.0V)
13
REFHIN
I(A)
ADC high reference input
14
REFLIN
I(A)
ADC low reference input
15
REFH
O(A)
ADC high reference output
Connect to GND via an approximately 0.1µF capacitor.
16
REFL
O(A)
ADC low reference output
Connect to GND via an approximately 0.1µF capacitor.
17
VSS3
P
Analog GND
18
VDD3
P
Analog power supply (3.3V)
19
REFBIAS
20
VDD4
P
Digital power supply (3.3V)
21
VSS4
P
Digital GND
22
TEST
I
Test pin. Normally fix high.
23
DEFECT
I
Blemish compensation function switching 0: Off, 1: On
24
VDD5
P
Digital power supply (3.3V)
25
AGC
I
Analog gain switching 0: Fixed, 1: Auto
26
DGC
I
Digital gain switching 0: Fixed, 1: Auto
27
MIRROR
I
Mirror inversion switching 0: Standard, 1: Mirror
28
APCON
I
Aperture correction switching 0: Off, 1: On
29
GAMMA1
I
30
GAMMA2
I
Gamma correction characteristics switching
00: 0.45, 01: 0.6 (register setting), 10: 1.0, 11: S curve
P
Analog GND
O(A) Output for monitoring the signal input to ADC
O(A)
ADC DC bias output
Connect to GND via an approximately 0.1µF capacitor.
–6–
CXD3152AR
Pin
No.
Symbol
31
MCKPHS
I
2MCKI input polarity switching
0: Through, 1: Inverted
32
VSS5
P
Digital GND
33
CVREF
O(A)
34
COMP
O(A) DAC phase compensation. Connect to GND via 0.1µF.
35
VSS6
P
Digital GND
36
VDD6 (3.3V)
P
Digital power supply (3.3V)
37
RREF
O(A)
38
ANAB
O(A) DAC negative output. Normally connect to GND via 200Ω.
39
ANA
40
REGRES
41
SDA
O(A) DAC positive output. Normally connect to GND via 200Ω.
I∗
Register reset. All registers reset to the default when low.
∗
I/O
I2C bus data line
42
SCL
I/O∗
43
OEB
I
Digital output (Y0 to Y7) control.
0: Output, 1: Hi-Z
44
Y0
O
Digital signal output (LSB)
45
Y1
O
Digital signal output
46
Y2
O
Digital signal output
47
Y3
O
Digital signal output
48
Y4
O
Digital signal output
49
VSS7
P
Digital GND
50
Y5
O
Digital signal output
51
Y6
O
Digital signal output
52
Y7
O
Digital signal output (MSB)
53
MCKO
Y0 to Y7 latch clock output
54
CHARA
O
I∗
55
2MCKI
I∗
56
VDD7
57
Description
I/O
DAC reference voltage output
Connect to GND via 0.1µF.
DAC reference voltage generation
Normally connect to GND via 3.3kΩ.
I2C bus clock line
Character signal input
Reference clock input
Digital power supply (3.3V)
EIA
P
I∗
58
CCD
I∗
CCD number of horizontal pixels switching
0: 510H system, 1: 760H system
59
CSYNC_IN
I∗
Composite sync input
60
BLCW1
I∗
61
BLCW2
I∗
Backlight compensation window switching
00: Full-screen photometry, 01: Bottom photometry
10: Center photometry, 11: Bottom + center photometry
62
SHD
I∗
Data block sampling pulse input
TV mode switching 0: EIA, 1: CCIR
–7–
CXD3152AR
Pin
No.
Symbol
63
SHP
64
GOUT
Description
I/O
I∗
O(A)
Precharge block sampling pulse input
AGC gain control voltage output (DAC output)
Connect to GND via an approximately 0.1µF capacitor.
Note 1) Asterisks (∗) indicate that either 3.3V or 5.0V input is possible.
Note 2) The I/O column symbol meanings are as follows.
I
: Digital input
O
: Digital output
I/O
: Digital input/output
I(A) : Analog input
O(A) : Analog output
P
: Power supply/GND
–8–
CXD3152AR
Logic Block Electrical Characteristics
DC Characteristics
3.3V Block
(VDD = 3.0 to 3.6V, VSS = 0V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
0.7VDD
—
—
V
—
—
0.2VDD
V
0.75VDD
—
—
V
—
—
0.15VDD
V
—
—
0.4
V
VDD – 0.8
—
—
V
—
—
0.4
V
Applicable
pins
Input high level voltage
VIH
Input low level voltage
VIL
Input high level voltage
VIH
Input low level voltage
VIL
Output low level voltage
VOL
IOL = 4mA
Output high level voltage
VOH
IOH = –4mA
Output low level voltage
VOL
IOL = 4mA
Input leak current
IIL
VI = VDD, VSS
–10
—
+10
µA
∗1, ∗2, ∗4
Output leak current
IOZ
At high impedance output
–10
—
+10
µA
∗3, ∗4
CMOS supported
CMOS Schmitt supported
∗1
∗2, ∗4
∗4
∗3
Note 1) The applicable pins correspond to the following symbols.
∗1 AGC, APCON, BLCW1, BLCW2, CCD, CHARA, MCKPHS, CSYNC_IN, DEFECT, DGC, EIA, GAMMA1,
GAMMA2, 2MCKI, MIRROR, TEST, OEB (input)
∗2 REGRES
∗3 MCKO, Y0 to Y7 (output)
∗4 SCL, SDA (I/O)
Note 2) The ANA, ANAB, COMP, CVREF, REFBIAS, REFH, REFL and RREF pins are not included in the DC
characteristics.
5.0V Block
(VDD = 4.75 to 5.25V, VSS = 0V)
Item
Symbol
Input high level voltage
VIH
Input low level voltage
VIL
Input leak current
IIL
Min.
Typ.
Max.
Unit
0.7VDD
—
—
V
—
—
0.3VDD
V
–10
—
+10
µA
Conditions
CMOS supported
VI = VDD, VSS
Applicable
pins
∗5
∗5
Note 1) The applicable pins correspond to the following symbols.
∗5 SHD, SHP (input)
Note 2) The CAP1, CAPA2, CAPB2, CCDIN, REFHIN, REFLIN, YIN, GOUT, IRISOUT, MONITOR and YOUT
pins are not included in the DC characteristics.
–9–
CXD3152AR
AC Characteristics
(Output load: CL = 50pF)
Item
Symbol
Min.
Typ.
Max.
Unit
CSYNC_IN fall setup time, activated by the falling edge of 2MCKI
10
—
—
ns
10
—
—
ns
—
—
20
ns
10
—
—
ns
10
—
—
ns
—
—
20
ns
0
—
—
ns
20
—
—
ns
—
—
15
ns
1
—
—
µs
Reset pulse width
tsu1
thd1
tdly1
tsu2
thd2
tdly2
tsu3
thd3
tdly3
tpor
trst
1
—
—
µs
SCL clock frequency
fscl
—
—
500
kHz
SCL clock high level width
thigh
tlow
tsu4
thd4
tdly4
tdly5
tdly6
tdly7
700
—
—
ns
700
—
—
ns
30
—
—
ns
0
—
—
ns
—
—
20
ns
—
—
15
ns
—
—
—
ns
0
—
30
ns
CSYNC_IN fall hold time, activated by the falling edge of 2MCKI
Delay time from the falling edge of 2MCKI to MCKO output
CSYNC_IN fall setup time, activated by the rising edge of 2MCKI
CSYNC_IN fall hold time, activated by the rising edge of 2MCKI
Delay time from the rising edge of 2MCKI to MCKO output
CHARA setup time, activated by the falling edge of MCKO
CHARA hold time, activated by the falling edge of MCKO
Delay time from the falling edge of MCKO to Y0 to Y7 output
Power-on reset time
SCL clock low level width
SDA setup time, activated by the rising edge of SCL
SDA hold time, activated by the falling edge of SCL
Delay time from the falling edge of SCL to SDA low level output
Delay time from the falling edge of SCL to SDA output floating
SHP rise time, activated by the falling edge of 2MCKI
SHD rise time, activated by the falling edge of 2MCKI
– 10 –
CXD3152AR
Master Clock Generation Timing
(1) MCKPHS = Low
2MCKI
thd1
tsu1
CSYNC_IN
tdly1
tdly1
tdly1
MCKO
(2) MCKPHS = High
2MCKI
thd2
tsu2
CSYNC_IN
tdly2
tdly2
tdly2
MCKO
Video Signal Related Input/Output Timing
MCKO
tsu3
CHARA
thd3
tdly3
Y0 to Y7
– 11 –
CXD3152AR
Reset Timing
3V
VDD
tpor
trst
VIH
REGRES
I2C bus Timing
SCL
thigh
tlow
SDA (input)
tsu4
thd4
Hi-Z
SDA (output)
tdly4
Analog Signal Processing Sampling Pulse Timing
2MCKI
SHP
tdly6
tdly7
SHD
ADCLK
tdly8
tdly8
Note 1) When MCKPHS = Low
– 12 –
tdly5
CXD3152AR
Analog Block Electrical Characteristics
10-bit A/D Converter Electrical Characteristics
Item
Symbol
(VDD3 = 3.3V, VSS = 0V, Ta = 25°C)
Min.
Typ.
Max.
Unit
Test conditions
Resolution
RES
—
—
10
Bits
Conversion frequency
Fs
—
15
20
MSPS
Nonlinearity error
I.L.
—
—
±2.0
LSB
DC accuracy
Differential nonlinearity error
D.L.
—
—
±1.0
LSB
DC accuracy
∗ For the power supply names, refer to the symbols in the Pin Description.
9-bit D/A Converter Electrical Characteristics
Item
Symbol
(VDD6 = 3.3V, VSS = 0V, Ta = 25°C)
Min.
Typ.
Max.
Unit
Test conditions
Resolution
RES
—
—
10
Bits
Conversion frequency
Fs
—
—
20.0
MSPS
Zero scale output voltage
VZERO
–15
0
15
mW
Full scale output voltage
VFULL
1.21
1.30
1.43
V
Full scale output current
IFULL
0
6.6
16.5
mA
Nonlinearity error
I.L.
—
—
±2.0
LSB
DC accuracy
Differential nonlinearity error
D.L.
—
—
±1.0
LSB
DC accuracy
∗ For the power supply names, refer to the symbols in the Pin Description.
– 13 –
CXD3152AR
CDS-AGC Electrical Characteristics
Item
Symbol
(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25°C)
Min.
Typ.
Max.
Unit
Test conditions
CAP1 DC level
CAP1
1.5
1.6
1.7
V
CAP1 output DC level
CCDIN = 1.6V (DC)
GOUT = 1.5V
CAPA2 DC level
CAPA2
2.5
3.0
3.5
V
CAPA2 output DC level
CCDIN = 1.6V (DC)
GOUT = 1.5V
CDS DC level
CDSDC
2.9
3.4
3.9
V
YOUT output DC level
CCDIN = 1.6V (DC)
GOUT = 2.5V
AGC DC offset 1
GCOF1
–0.2
0
0.2
mV
GCOF1 = V4 – CDSDC
V4 = YOUT output DC level
CCDIN = 1.6V (DC)
GOUT = 1.5V
AGC DC offset 2
GCOF2
–0.4
0
0.4
mV
GCOF2 = V5 – CDSDC
V5 = YOUT output DC level
CCDIN = 1.6V (DC)
GOUT = 0.5V
AGC minimum
gain characteristics (Note 1)
AGCG1
3.3
6.4
8.7
dB
YOUT output gain
CCDIN = S1 (Note 2)
GOUT = 3.3V
AGC maximum
gain characteristics (Note 1)
AGCG2
15.7
18.8
21.1
dB
YOUT output gain
CCDIN = S1 (Note 2)
GOUT = 0V
AGC D range 1
AGCD1
1.9
2.2
2.7
V
YOUT output AC level
CCDIN = S1 (Note 3)
GOUT = 0.5V
AGC D range 2
AGCD2
1.6
2.0
2.7
V
YOUT output AC level
CCDIN = S1 (Note 3)
GOUT = 2.5V
IRIS DC level
IRISDC
1.6
2.2
2.6
V
IRISOUT DC level
CCDIN = 1.6V (DC)
GOUT = 3.3V
IRIS gain
IRISG
8.3
9.5
10.7
dB
IRISOUT gain
CCDIN = S2 (Note 4)
GOUT = 3.3V
IRIS D range
IRISDR
1.6
2.1
2.7
V
IRISOUT AC level
CCDIN = S2 (Note 5)
GOUT = 3.3V
∗ For the power supply names, refer to the symbols in the Pin Description.
Note 1) Refer to the AGC Gain Characteristics.
Note 2) S1: Va = 100 to 400mV, Vb = 1.6V (Va = peak to peak, Vb = peak to GND)
Note 3) S1: Va = 1000mV, Vb = 1.6V
Note 4) S2: Va = 400mV, Vb = 1.6V
Note 5) S2: Va = 1000mV, Vb = 1.6V
– 14 –
CXD3152AR
CLP Electrical Characteristics
(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Test conditions
CAPB2 DC level
CAPB2
2.6
2.7
2.8
V
CAPB2 output DC level
SW1 = A, SW2 = A
CLP DC level
CLPDC1
2.6
2.7
2.8
V
MONITOR output DC level
CLP = "H"
SW1 = A, SW2 = A
CLP gain
CLPG
0
0.6
1.2
dB
MONITOR output gain
SW1 = B, SW2 = B
YIN = S4 (Note 1)
CLP D range
CLPD
2.0
2.4
2.7
V
MONITOR output AC level
SW1 = B, SW2 = A
YIN = S3 (Note 2)
∗ For the power supply names, refer to the symbols in the Pin Description.
Note 1) S4: Va = 1000mV, Vb = 2.75V (Va = peak to peak, Vb = peak to GND)
Note 2) S3: Va = 2000mV, Vb = 3.6V
OPAMP Electrical Characteristics
Item
(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25°C)
Symbol
Min.
Typ.
Max.
Unit
Test conditions
OPAMP DC H
OPH
2.8
2.9
3.0
V
REFH output DC level
SW1 = A, SW2 = A
OPAMP DC L
OPL
0.8
0.9
1.0
V
REFL output DC level
SW1 = A, SW2 = A
∗ For the power supply names, refer to the symbols in the Pin Description.
AGC Gain Characteristics (VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25°C)
25
AGC gain [dB]
20
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.3
GOUT voltage [V]
AGC Gain Characteristics
– 15 –
CXD3152AR
Analog Input/Output Pin Equivalent Circuits
Pin
No.
5
Symbol
IRISOUT
Equivalent circuit
I/O
Description
O
VDD1, 2
Video signal output pin of gain control
amplifier (AGC)
Maximum output amplitude = 2.25Vp-p
(typ.)
Black level = 3.40V DC (typ.)
5
6
YOUT
O
6
10
10
MONITOR
Video signal output of analog clamp circuit
Monitor pin for input signal to ADC
Black level = 2.75V DC (typ.)
O
VDD1, 2
2
CCDIN
I
2
13
13
REFHIN
I
14
REFLIN
I
Video signal output pin for iris detection
Maximum output amplitude = 2.10Vp-p
(typ.)
Maximum input amplitude = 3.40Vp-p
(Maximum video signal amplitude from
precharge level = 2.00Vp-p)
DC input bias = 1.80 ± 0.1V
High reference input pin for ADC
2.92V DC input (typ.)
14
Low reference input pin for ADC
0.82V DC input (typ.)
VDD1, 2
Input pin for video signal to undergo
A/D conversion
Maximum input amplitude = 2.30Vp-p
(typ.)
Black level = 2.73V DC (typ.)
7
7
YIN
I
VDD1, 2
4
CAPA2
O
1k
10k
3
CAP1
DC bias output pin of the gain control
amplifier
3.00V DC output (typ.)
4
10k
VDD1, 2
O
DC bias output pin of the CDS circuit
1.58V DC output (typ.)
3
8
8
CAPB2
Clamp level (DC) input pin of the
clamp circuit for A/D conversion
2.73V DC input (typ.)
I
– 16 –
CXD3152AR
Pin
No.
Symbol
I/O
Equivalent circuit
VDD7
Description
VDD1, 2
1.5k
64
GOUT
64
Gain control signal (8-bit DAC for gain
control) output pin for AGC
O
VDD7
15
REFH
O
High reference output pin for ADC
Voltage follower output
2.90V DC output (typ.)
15
VDD3
16
REFL
O
Low reference output pin for ADC
Voltage follower output
0.80V DC output (typ.)
16
VDD3
19
REFBIAS
O
DC bias output pin for ADC
1.55V DC output (typ.)
19
VDD6
38
ANAB
O
39
ANA
O
D/A converter negative output
0 to 1.24V output
38
39
– 17 –
D/A converter positive output
0 to 1.24V output
CXD3152AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
VDD6
37
RREF
DAC reference voltage generation pin
1.32V DC output (typ.)
O
37
VDD6
33
CVREF
O
DAC reference voltage output pin
1.32V DC output (typ.)
33
VDD6
34
COMP
DAC phase compensation pin
2.18V DC output (typ.)
O
34
Note) For the power supply names in the equivalent circuits, refer to the symbols in the Pin Description.
– 18 –
CXD3152AR
Timing Chart
Horizontal Direction Timing
2MCK:
MCK:
MCKO:
CCDIN:
SHP:
SHD:
cblk:
CSYNC:
A_CLP:
D_CLP:
DOUT[7:0]:
ANA:
Master clock input for the CXD3152AR
Internal reference clock produced by dividing the input reference clock (2MCK) in half.
Latch clock for digital output signal (Inverted MCK signal)
Imaging signal from CCD
Precharge level sampling pulse input
Video level sampling pulse input
Internal composite blanking pulse (for VIDEO output signal)
Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal)
Internal pulse for analog clamp
Internal pulse for digital clamp
8-bit digital output signal
Analog output signal
Vertical Direction Timing
HD:
cblk:
CSYNC:
A_CLP:
D_CLP:
CCDIN:
DOUT[7:0]:
Internal horizontal sync signal
Internal composite blanking pulse (for VIDEO output signal)
Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal)
Internal pulse for analog clamp
Internal pulse for digital clamp
Video signal from the CCD
8-bit digital output signal
– 19 –
– 20 –
ANA
DOUT[7:0]
cblk
D_CLP
A_CLP
CSYNC
SHD
SHP
CCDIN
MCKO
MCK
2MCK
0
506
507
508
509
510
499
505
499
500
501
502
503
504
505
8
10
14
14
16
20
24
EIA 510H System
30
59
60
80
90
100
110
120
Count CLK = 606fH = 19.0699/2MHz
17.5 clocks
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
6
11
16
19
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Horizontal Direction Timing Chart
CXD3152AR
– 21 –
ANA
DOUT[7:0]
cblk
D_CLP
A_CLP
CSYNC
SHD
SHP
CCDIN
MCKO
MCK
2MCK
0
496
497
498
499
500
489
495
489
490
491
492
493
494
495
8
10
14
14
16
20
24
CCIR 510H System
30
59
60
90
100
110
120
130
Count CLK = 606fH = 18.9375/2MHz
17.5 clocks
114
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
6
11
16
19
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Horizontal Direction Timing Chart
CXD3152AR
– 22 –
ANA
DOUT[7:0]
cblk
D_CLP
A_CLP
CSYNC
SHD
SHP
CCDIN
MCKO
MCK
2MCK
0
764
765
766
767
768
758
764
758
759
760
761
762
763
764
10
12
20
22
EIA 760H System
30
40
90
140
150
160
170
Count CLK = 910fH = 28.63636/2MHz
15.5 clocks
154
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
7
11
16
21
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Horizontal Direction Timing Chart
CXD3152AR
– 23 –
ANA
DOUT[7:0]
cblk
D_CLP
A_CLP
CSYNC
SHD
SHP
CCDIN
MCKO
MCK
2MCK
0
748
749
750
751
752
743
749
743
744
745
746
747
748
749
10
12
20
22
CCIR 760H System
30
40
90
150
160
170
180
Count CLK = 908fH = 28.375/2MHz
13.5 clocks
169
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9
13
18
21
9
10
11
12
13
14
15
16
17
18
19
20
21
Horizontal Direction Timing Chart
CXD3152AR
DOUT[7:0]
CCDIN
D_CLP
A_CLP
CSYNC
cblk
HD
258 260 262
(520) (522) (524) 0
2
4
479
481
483
485
487
489
491
493
OB
480
482
484
486
488
490
492
494
OB
Odd field
OB
OB
OB
OB
OB
OB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
OB
OB
OB
OB
OB
OB
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Even field
475
477
479
481
483
485
476
478
480
482
484
486
6
8
EIA 510H/760H System
10
20
25
30
258
0
4
8
2
10
6
260 (262) (264) (266) (268) (270) (272)
15
(277)
2H
20
(282)
25
(287)
30
(292)
478
480
482
484
486
488
490
492
494
OB
479
481
483
485
487
489
491
493
OB
15
OB
OB
OB
OB
OB
OB
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
OB
OB
OB
OB
OB
OB
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Odd field Even field
475 474
477 476
479 478
481 480
483 482
485 484
487 486
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
4
6
8
10
12
14
16
18
20
22
24
26
28
Vertical Direction Timing Chart
2
4
6
8
10
12
14
16
18
20
22
24
3
5
7
9
11
13
15
17
19
21
23
25
– 24 –
CXD3152AR
DOUT[7:0]
CCDIN
D_CLP
A_CLP
CSYNC
cblk
HD
308 310 312
(620) (622) (624)0
2
4
567
569
571
573
575
577
579
581
OB
568
570
572
574
576
578
580
582
OB
Odd field
563
565
567
569
571
573
575
564
566
568
570
572
574
576
OB
OB
OB
OB
OB
OB
2
4
6
8
10
12
14
16
OB
OB
OB
OB
OB
OB
1
3
5
7
9
11
13
15
17
Even field
OB
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
6
8
10
CCIR 510H/760H System
15
20
25
30
308
310
10
6
8
2
4
0
(313) (315) (317) (319) (321) (323)
Even field
15
(328)
568
570
572
574
576
578
580
582
OB
569
571
573
575
577
579
581
OB
Odd field
OB
OB
OB
OB
OB
OB
1
3
5
7
9
11
13
15
17
19
21
OB
OB
OB
OB
OB
OB
2
4
6
8
10
12
14
16
18
20
22
Vertical Direction Timing Chart
564
566
568
570
572
574
565
567
569
571
573
575
– 25 –
2H
25
(338)
30
(343)
1
3
5
7
9
11
13
15
17
20
(333)
2
4
6
8
10
12
14
16
18
CXD3152AR
CXD3152AR
I2C Serial Communication
1. Description of communication
The CXD3152AR performs serial communication between a PC or an external EEPROM via the I2C bus. In
communication with a PC, the PC is the master device and the CXD3152AR is the slave device. On the other
hand, in communication with an EEPROM, the CXD3152AR is the master device and the EEPROM is the
slave device. Communication is performed using two signal lines: SDA and SCL. SDA is a bidirectional serial
data transfer line, and is used to transfer addresses from master to slave and to transfer data between master
and slave. SDA is normally pulled up to VDD by external resistance of several kΩ. (Therefore, SDA is high at high
impedance.) SCL is a bidirectional serial clock transfer line, and is used as the data transfer synchronization
clock. SCL is driven by the master device, and like SDA is pulled up to VDD by external resistance of several
kΩ.
2. Slave address
The CXD3152AR I2C slave address is as follows.
[A6:A0] = 0011111 (b)
3. I2C protocol
Communication conforms to the I2C bus protocol. Data transfer is started when the bus is not in the busy
status. During the data transfer period, the data line must be kept stable while the clock line is high. Otherwise,
data line changes while the clock line is high are interpreted as START or STOP conditions.
• START condition
The START condition occurs before all commands to the device, and is defined as SDA changing from high
to low when SCL is high.
• STOP condition
The STOP condition is defined as SDA changing from low to high when SCL is high. All operations must end
in the stop condition.
BUS ACTIVITY
STOP
BYTE
ADDRESS
DATA
P
– 26 –
ACK
S
SLAVE
ADDRESS
ACK
SDA LINE
BUS ACTIVITY
ACK
MASTER
START
4. Communication timing
During read, the SDA data is taken in sync with the falling edge of SCL. During write, the data is output to SDA
after a certain delay time from the falling edge of SCL. The communication data is MSB first. An overview of
the byte-write and byte-read timings are described below.
• Byte-write timing
In the byte-write mode, the master device transmits the START condition and the slave address information
(the R/W bit is set to 0) to the slave device. After the slave returns an acknowledgement, the master transmits
the byte address to be written in the slave address pointer. After receiving the next acknowledgement from
the slave, the master transfers the data to be written to the preceding address. The slave device returns an
acknowledgement again, and the master generates the STOP condition.
CXD3152AR
STOP
SLAVE
ADDRESS
DATA
P
NO ACK
S
ACK
BUS ACTIVITY
START
S
BYTE
ADDRESS
SLAVE
ADDRESS
ACK
SDA LINE
BUS ACTIVITY
ACK
MASTER
START
• Byte-read timing
In the byte-read mode, the master device first transmits the START condition, the slave address, and the
byte address of the position to be read to the slave device as a write operation. After the slave returns an
acknowledgement, the master transmits the START condition and slave address (at this time the R/W bit is
set to 1) again. After that, the slave issues an acknowledgement and transfers the read data. The master
generates the STOP condition without transmitting an acknowledgement.
Note 1) The upper 7 bits of the slave address indicate the device address, while the lowermost bit indicates
the R/W mode. (Read mode when this bit is high, and write mode when it is low.)
Note 2) The CXD3152AR slave address is [A6:A0] = 0011111 (b).
Note 3) ACK is the response acknowledgement signal, and the slave device goes to low.
Note 4) NO ACK means that a response acknowledgement signal is not returned.
Note 5) S: START condition, P: STOP condition
– 27 –
CXD3152AR
Description of Registers
Address
Symbol
Part symbol
bit
REGRES
0
Description
Register reset
0: Reset, 1: Normal
(The REGRES pin (Pin 40) has precedence.)
Default R/W
—
1
2
00 (h)
REGRES
W
3
dummy
4
5
6
7
0
1
2
3
0F (h)
WSTART
WSTART
4
5
6
Horizontal timing for write start to line memory
Set in MCKI clock units
0x00 : Earliest (advanced) position
0xFE : Latest (delayed) position
0xFF : Internal fixed value
EIA510 system = 67 (h)
CCIR510 system = 71 (h)
EIA760 system = 95 (h)
CCIR760 system = A3 (h)
FF (h)
W
Horizontal timing for read start from line memory
Set in MCKI clock units
0x00 : Earliest (advanced) position
0xFE : Latest (delayed) position
0xFF : Internal fixed value
EIA510 system = 5C (h)
CCIR510 system = 66 (h)
EIA760 system = 89 (h)
CCIR760 system = 96 (h)
FF (h)
W
Gamma correction curve adjustment-1
Sets the intersection between the 1st
approximation line (slope = 1) and the 2nd
approximation line (slope = 3).
Setting range: 00 (h) to 1F (h)
00 (h)
7
0
1
2
3
10 (h)
RSTART
RSTART
4
5
6
7
0
1
YGAM1
2
3
14 (h)
YGAM1
4
5
dummy
6
7
– 28 –
W
CXD3152AR
Address
Symbol
Part symbol
Description
bit
Default R/W
0
1
2
YGAM2
15 (h)
YGAM2
3
4
Gamma correction curve adjustment-2
Sets the intersection between the 2nd
approximation line (slope = 3) and the 3rd
approximation line (slope = 3/2).
Setting range: 00 (h) to 3F (h)
0A (h)
Gamma correction curve adjustment-3
Sets the intersection between the 3rd
approximation line (slope = 3/2) and the 4th
approximation line (slope = 1).
Setting range: 00 (h) to 7F (h)
20 (h)
Gamma correction curve adjustment-4
Sets the intersection between the 4th
approximation line (slope = 1) and the 5th
approximation line (slope = 3/4).
Setting range: 00 (h) to 7F (h)
2E (h)
Gamma correction curve adjustment-5
Sets the intersection between the 5th
approximation line (slope = 3/4) and the 6th
approximation line (slope = 1/2).
Setting range: 00 (h) to 7F (h)
36 (h)
W
5
6
dummy
7
0
1
2
16 (h)
YGAM3
YGAM3
3
4
W
5
6
dummy
7
0
1
2
17 (h)
YGAM4
YGAM4
3
4
W
5
6
dummy
7
0
1
2
18 (h)
YGAM5
YGAM5
3
4
5
6
dummy
7
– 29 –
W
CXD3152AR
Address
Symbol
Part symbol
bit
Description
Default R/W
0
1
2
19 (h)
YGAM6
YGAM6
3
4
5
Gamma correction curve adjustment-6
Sets the intersection between the 6th
approximation line (slope = 1/2) and the 7th
approximation line (slope = 1/8).
Setting range: 00 (h) to 7F (h)
The 7th approximation line is used for knee
processing.
41 (h)
Horizontal aperture correction signal gain setting
The gain changes linearly from 0 (h) to 7 (h).
0 (h): ×0
F (h): Maximum gain
09 (h)
W
6
dummy
7
0
1
HAPGAIN
2
3
1A (h)
HAPGAIN
W
4
5
dummy
6
7
0
1
2
HAPCORE1
3
4
1B (h)
HAPCORE
Horizontal aperture correction signal noise
suppression (coring) characteristics setting
OUTPUT = INPUT – HAPCORE1
If (OUTPUT < 0), OUTPUT = 0
00 (h): Noise suppression off
3F (h): Maximum noise suppression level
W
5
6
HAPCORE2
7
0
1
VAPGAIN
2
Horizontal aperture correction signal noise
suppression (coring) characteristics setting
OUTPUT = INPUT
If (OUTPUT ≤ HAPCORE2), OUTPUT = 0
00 (h): Noise suppression off
03 (h): Maximum noise suppression level
00 (h)
Vertical aperture correction signal gain setting
The gain changes linearly from 0 (h) to F (h).
0 (h): ×0
F (h): Maximum gain
04 (h)
3
1C (h)
02 (h)
VAPGAIN
W
4
5
dummy
6
7
– 30 –
CXD3152AR
Address
Symbol
Part symbol
Description
bit
Default R/W
0
1
2
VAPCORE1
3
4
1D (h)
VAPCORE
02 (h)
W
5
6
VAPCORE2
7
0
1
LCLIP
1E (h)
Vertical aperture correction signal noise
suppression (coring) characteristics setting
OUTPUT = INPUT – VAPCORE1
If (OUTPUT < 0), OUTPUT = 0
00 (h): Noise suppression off
3F (h): Maximum noise suppression level
2
3
APCLIP
4
5
HCLIP
6
7
Vertical aperture correction signal noise
suppression (coring) characteristics setting
OUTPUT = INPUT
If (OUTPUT ≤ VAPCORE2), OUTPUT = 0
00 (h): Noise suppression off
03 (h): Maximum noise suppression level
00 (h)
Aperture correction signal minus side clip level setting
OUTPUT = INPUT
If (INPUT ≤ LCLIP), OUTPUT = LCLIP
0 (h): Maximum clip level
F (h): Minimum clip level
04 (h)
W
Aperture correction signal plus side clip level setting
OUTPUT = INPUT
If (INPUT ≥ HCLIP), OUTPUT = HCLIP
0 (h): Maximum clip level
F (h): Minimum clip level
06 (h)
Aperture correction signal coring level DGC link
setting
0x0: Coring off
0x1F: Maximum coring level
1F (h)
0
1
AT_APCORE
1F (h)
2
3
AT_APCORE
W
4
5
dummy
6
7
0
1
2
YGAIN1
20 (h)
YGAIN1
3
Signal gain setting when GAMMA1 and GAMMA2
are set to 00 (gamma = 0.45)
W
4
5
6
dummy
3C (h)
7
– 31 –
CXD3152AR
Address
Symbol
Part symbol
Description
bit
Default R/W
0
1
2
YGAIN2
21 (h)
YGAIN2
3
Signal gain setting when GAMMA1 and GAMMA2
are set to 10 (gamma = 0.6)
1F (h)
W
4
5
6
dummy
7
0
1
2
YGAIN3
22 (h)
YGAIN3
3
Signal gain setting when GAMMA1 and GAMMA2
are set to 01 (gamma = 1.0)
18 (h)
W
4
5
6
dummy
7
0
1
2
YGAIN4
23 (h)
YGAIN4
3
Signal gain setting when GAMMA1 and GAMMA2
are set to 11 (gamma = S)
3A (h)
W
4
5
6
dummy
7
0
1
2
24 (h)
PED
PED
3
4
5
Pedestal level setting
The pedestal level changes linearly from
0 (h) to F (h).
00 (h): Low
17 (h): 7.5 IRE
3F (h): High
6
dummy
7
– 32 –
17 (h)
W
CXD3152AR
Address
Symbol
Part symbol
bit
LCLIP
0
Description
Clip level setting for the black level and lower
0: –20 IRE, 1: Pedestal level
Default R/W
00 (h)
1
2
25 (h)
3
LOWCLIP
dummy
W
4
5
6
7
0
1
2
CHARA_G
27 (h)
CHARA_G
3
Externally input 1-bit character signal gain setting
00 (h): –85 IRE
20 (h): ±0
3F (h): +85 IRE
32 (h)
White clip level setting
C4 (h)
W
1D (h)
W
W
4
5
6
dummy
7
0
1
2
28 (h)
3
WT_CLIP
WT_CLIP
4
5
6
7
0
1
2
BK_CLIP
29 (h)
BK_CLIP
Video signal minus component clip level setting
3
4
5
6
dummy
7
– 33 –
CXD3152AR
Address
Symbol
Part symbol
Description
bit
Default R/W
0
1
2
APGAM1
2A (h)
APGAM1
3
4
Aperture signal gamma correction characteristics
setting
Sets the intersection of the 1st approximation line
(slope = 2) which passes through the origin and
the 2nd approximation line (slope = 1).
Setting range: 00 (h) to 3F (h)
3F (h)
W
5
6
dummy
7
0
1
2
2B (h)
APGAM2
APGAM2
3
4
5
Aperture signal gamma correction characteristics
setting
Sets the intersection of the 2nd approximation line
(slope = 1) and the 3rd approximation line (slope = 7F (h)
1/2).
Setting range: 00 (h) to 7F (h)
W
6
dummy
7
APSW
0
Aperture correction signal added position setting
01 (h)
0: After gamma correction, 1: Before gamma correction
1
2
2C (h)
3
APSW
dummy
W
4
5
6
7
0
1
2
32 (h)
AGC_REF
AGC_REF
3
Reference level setting for auto gain control
integral value
4
5
6
dummy
7
– 34 –
18 (h)
W
CXD3152AR
Address
Symbol
Part symbol
Description
bit
Default R/W
0
1
2
33 (h)
3
DGCMIN
DGCMIN
4
5
6
Digital gain control (DGC) minimum gain limiter
setting
Valid when DGC = 1
When DGC = 0, this is the digital gain manual
20 (h)
setting register.
20 (h) : ×1.0 times
(1F (h) and lower settings are prohibited)
FF (h) : ×8.0 times
W
Digital gain control (DGC) maximum gain limiter
setting
Valid when DGC = 1
20 (h) : ×1.0 times
A0 (h)
(1F (h) and lower settings are prohibited)
0xA0 : ×5.0 times
0xFF : ×8.0 times
W
7
0
1
2
34 (h)
3
DGCMAX
DGCMAX
4
5
6
7
0
1
2
35 (h)
AGCMIN
AGCMIN
3
4
5
Analog gain control (AGC) minimum gain limiter
setting (Sets the upper 7 bits for gain signal
generating 8-bit DAC. The lowest digit is "0".)
Valid when AGC = 1
When AGC = 0, this is the analog gain manual
setting register.
00 (h) : Min.
7F (h) : Max.
00 (h)
Analog gain control (AGC) maximum gain limiter
setting (Sets the upper 7 bits for gain signal
generating 8-bit DAC. The lowest digit is "0".)
Valid when AGC = 1
00 (h) : Min.
7F (h) : Max.
59 (h)
W
6
dummy
7
0
1
2
36 (h)
AGCMAX
AGCMAX
3
4
5
6
dummy
7
– 35 –
W
CXD3152AR
Address
Symbol
Part symbol
bit
0
1
AGCWAIT
2
3
37 (h)
AGCWAIT
4
SW
5
Description
Default R/W
Auto gain control time constant setting
Hold time (Hold_time) or feedback time (FB_time)
can be selected by the SW setting.
Hold_time = (AGCWAIT × 2 + 2) × Vt
Vt: 1/60 (EIA), 1/50 (CCIR)
(FB_time also uses the above formula.)
1D (h)
Hold time/feedback time selection
0: Hold_time, 1: FB_time
00 (h)
Auto gain control feedback time setting
0: Low speed, 1: High speed
00 (h)
W
6
dummy
AGCTM
7
0
1
2
38 (h)
AGCTM
W
3
dummy
4
5
6
7
AGCHD
0
Auto gain control hold setting
0: Normal operation, 1: Hold
00 (h)
1
2
39 (h)
3
AGCHD
dummy
W
4
5
6
7
0
Time constant setting
(00: Short, 11: Long)
3 (h)
2
Insensitive range setting
(0: Narrow, 1: Wide)
0
3
Digital clamp operation mode setting
(011: V period, 100: H period) 6 bit∗ is also used.
1
Digital clamp function ON/OFF (= 1)
0
Digital clamp operation mode setting
0
1
3A (h)
DCLP
DCLP
4
5
6∗
dummy
7
– 36 –
1
W
CXD3152AR
Address
Symbol
Part symbol
bit
NEWCLPH
0
Description
Clamp system changing (1 = New system)
Default R/W
1
1
2
3
3B (h)
NEWCLPH
dummy
W
4
5
6
7
0
1
1
2
CLPCYCL
3C (h)
CLPCYCL
3
1
Period setting (effective more than 000111) of
digital clamp data renewal (setting value + one
field)
0
0
4
1
5
0
W
6
dummy
7
0
HLDAREA
1
0
Digital clamp insensitive range setting
1
0
2
3
3D (h)
HLDAREA
W
4
dummy
5
6
7
0
1
MAX_N_DEF
2
Maximum number of registered blemishes setting
Maximum 10 points
3
4C (h)
MAX_N_DEF
W
4
5
dummy
0A (h)
6
7
– 37 –
CXD3152AR
Address
Symbol
Part symbol
bit
DEFRES
0
Description
Blemish detection operation reset
0: Reset, 1: Normal
Default R/W
01 (h)
1
2
5A (h)
3
DEFRES
dummy
W
4
5
6
7
0
1
2
64 (h)
3
DEF01
X[0:7]
Lower 8 bits of blemish pixel X address
00 (h) R/W
Upper 2 bits of blemish pixel X address
00 (h)
4
5
6
7
0
X[8:9]
1
2
65 (h)
3
DEF02
4
Y[0:5]
R/W
Lower 6 bits of blemish pixel Y address
00 (h)
Upper 3 bits of blemish pixel Y address
00 (h)
5
6
7
0
Y[6:8]
1
2
66 (h)
DEF03
D[0:4]
3
D0: EVEN Y address offset data relative to ODD
0: Offset value 0, 1: Offset value 1
4
Fixed to 1
5
D2: Valid data/invalid data
0: Invalid data, 1: Valid data
6
D3: Internal data/external data
0: External, 1: Internal
7
dummy
– 38 –
R/W
00 (h)
CXD3152AR
Address
Symbol
Part symbol
bit
67 (h)
DEF11
Omitted: Same as DEF01
68 (h)
DEF12
Omitted: Same as DEF02
69 (h)
DEF13
Omitted: Same as DEF03
6A (h)
DEF21
Omitted: Same as DEF01
6B (h)
DEF22
Omitted: Same as DEF02
6C (h)
DEF23
Omitted: Same as DEF03
6D (h)
DEF31
Omitted: Same as DEF01
6E (h)
DEF32
Omitted: Same as DEF02
6F (h)
DEF33
Omitted: Same as DEF03
70 (h)
DEF41
Omitted: Same as DEF01
71 (h)
DEF42
Omitted: Same as DEF02
72 (h)
DEF43
Omitted: Same as DEF03
73 (h)
DEF51
Omitted: Same as DEF01
74 (h)
DEF52
Omitted: Same as DEF02
75 (h)
DEF53
Omitted: Same as DEF03
76 (h)
DEF61
Omitted: Same as DEF01
77 (h)
DEF62
Omitted: Same as DEF02
78 (h)
DEF63
Omitted: Same as DEF03
79 (h)
DEF71
Omitted: Same as DEF01
7A (h)
DEF72
Omitted: Same as DEF02
7B (h)
DEF73
Omitted: Same as DEF03
7C (h)
DEF81
Omitted: Same as DEF01
7D (h)
DEF82
Omitted: Same as DEF02
7E (h)
DEF83
Omitted: Same as DEF03
7F (h)
DEF91
Omitted: Same as DEF01
80 (h)
DEF92
Omitted: Same as DEF02
81 (h)
DEF93
Omitted: Same as DEF03
Description
– 39 –
Default R/W
CXD3152AR
Address
Symbol
Part symbol
ADGC
Default R/W
0
Digital gain switching
(Same function as DGC pin)
0: Fixed, 1: Auto
00 (h)
AGC
1
Analog gain switching
(Same function as AGC pin)
0: Fixed, 1: Auto
00 (h)
SW
2
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
Gamma correction characteristics switching
(Same function as GAMMA1 and GAMMA2 pins)
00: 0.45, 01: 0.6, 10: 1, 11: S curve
00 (h)
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
DGC
96 (h)
Description
bit
W
3
4
dummy
5
6
7
GAM1
97 (h)
0
GAM2
1
SW
2
GAMMA
W
3
4
dummy
5
6
7
98 (h)
BLCW1
0
BLCW2
1
SW
2
BLCW
Backlight compensation window switching
(Same function as BLCW1 and BLCW2 pins)
00 (h)
00: Full-screen photometry, 01: Lower photometry
10: Center photometry, 11: Lower + center photometry
Register setting/pin setting selection
0: Pin setting, 1: Register setting
W
3
4
dummy
00 (h)
5
6
7
– 40 –
CXD3152AR
Address
99 (h)
Symbol
Description
Default R/W
Part symbol
bit
EIA
0
TV mode switching
(Same function as EIA pin)
0: EIA, 1: CCIR
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
EIA
W
3
4
dummy
5
6
7
9A (h)
CCD
0
CCD number of horizontal pixels switching
(Same function as CCD pin)
0: 510H system, 1: 760H system
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
CCD
W
3
4
dummy
5
6
7
9B (h)
MIR
0
Mirror inversion switching
(Same function as MIRROR pin)
0: Standard, 1: Mirror
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
MIRROR
W
3
4
dummy
5
6
7
– 41 –
CXD3152AR
Address
9C (h)
Symbol
Part symbol
bit
Description
Default R/W
APCON
0
Aperture correction switching
(Same function as APCON pin)
0: Off, 1: On
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
APCON
W
3
dummy
4
5
6
7
DACSW
0
DA conversion frequency setting
0: 2MCKI/2, 1: 2MCKI
01 (h)
1
2
9D (h)
OVSA
3
dummy
W
4
5
6
7
9E (h)
DEFECT
0
Blemish compensation function switching
(Same function as DEFECT pin)
0: Off, 1: On
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
DEFECT
W
3
dummy
4
5
6
7
DSCSW
0
Video output DAC on/off
0: On, 1: Off
00 (h)
1
2
9F (h)
3
DACSW
dummy
W
4
5
6
7
– 42 –
CXD3152AR
Address
A0 (h)
Symbol
Part symbol
bit
Description
Default R/W
OEB
0
Digital output (Y0 to Y7) switching
(Same function as OEB pin)
0: Output, 1: Hi-Z
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
OEB
W
3
dummy
4
5
6
7
CHARA
0
1-bit character signal input switching
(Same function as CHARA pin)
00 (h)
SW
1
Register setting/pin setting selection
0: Pin setting, 1: Register setting
00 (h)
2
A1 (h)
CHARA
W
3
dummy
4
5
6
7
– 43 –
CXD3152AR
Using the EEPROM
The CXD3152AR can connect an external EEPROM which supports the I2C bus. Normally, read and write to
and from the EEPROM are performed from the PC master via the I2C bus to the slave EEPROM. Also, this IC
can automatically read the user-set register values during power-on by writing the addresses and setting
values for up to 64 registers in the EEPROM. (At this time this IC is the master device and the EEPROM is the
slave device.)
The serial EEPROM S-24C01B made by Seiko Instruments Co., Ltd. or equivalent product can be used as the
external EEPROM.
The external EEPROM load timing during power-on or register reset is shown below for when an EEPROM is
mounted and not mounted. The I2C bus is occupied by the EEPROM load at this period, so when using the I2C
bus, other communication by the master device is prohibited for the following times from the rising edge of
REGRESS.
When an EEPROM is mounted
REGRES
SCL/SDA
Max. 135ms active (read from the EEPROM)
When an EEPROM is not mounted
REGRES
SCL/SDA
Max. 2ms active (checking for EEPROM presence)
– 44 –
CXD3152AR
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
0.15 ± 0.05
48
0.1
33
49
32
A
64
17
1
1.25
16
+ 0.08
0.18 – 0.03
0.5
1.7 MAX
0.1
M
0° to 10°
0.5 ± 0.2
(0.5)
0.1 ± 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L061
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP064-P-1010-AY
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
42 ALLOY
SOLDER COMPOSITION
Sn-Bi
PLATING THICKNESS
5-18µm
– 45 –
Sony Corporation