CXD3504R Selective Delay Line for LCD Description The CXD3504R is a selective delay line IC for performing signal processing during dot and line inverted drive of liquid crystal panels for Sony projectors. This chip has three built-in 10-bit × 1200-word 1H delay lines, and data path with or without a 1H delay can be selected by the control pins. Features • Supports dot and line inverted drive of liquid crystal panels for Sony projectors • Three built-in 10-bit × 1200-word 1H delay lines • Data path with or without a 1H delay can be selected by the control pins. Applications LCD projectors, etc. 176 pin LQFP (Plastic) Absolute Maximum Ratings (Vss = 0V) • Supply voltage VDD –0.3 to +4.6 V • Input voltage VI –0.3 to VDD + 0.3 V • Output voltage VO –0.3 to VDD + 0.3 V • Operating temperature Topr –30 to +75 °C • Storage temperature Tstg –55 to +125 °C • Allowable power dissipation PDmax 850mW (Ta ≤ 75°C) Recommended Operating Conditions • Supply voltage VDD 3.0 to 3.6 • Operating temperature Topr –30 to +75 • Input voltage VIN 0 to VDD Structure Silicon gate CMOS IC V °C V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99815-PS CXD3504R VSS R2OUT5 R2OUT6 R2OUT7 R2OUT8 R2OUT9 TEST3 VDD VSS R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 VDD VSS R1OUT5 R1OUT6 R1OUT7 R1OUT8 R1OUT9 VDD VSS R1IN9 R1IN8 R1IN7 R1IN6 R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN9 R2IN8 R2IN7 R2IN6 R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 VDD Block Diagram 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 VDD VSS 133 87 R2OUT4 G1IN9 134 86 R2OUT3 G1IN8 135 G1IN7 136 85 R2OUT2 R CH FIFO G1IN6 137 84 R2OUT1 G1IN5 138 83 R2OUT0 G1IN4 139 82 VSS G1IN3 140 81 VDD G1IN2 141 80 TEST2 G1IN1 142 79 G1OUT9 G1IN0 143 78 G1OUT8 G2IN9 144 77 G1OUT7 G2IN8 145 76 G1OUT6 75 G1OUT5 G2IN7 146 INPUT LATCH & SELECT G2IN6 147 G2IN5 148 G2IN4 149 OUTPUT SELECT & LATCH G CH FIFO 74 VSS 73 VDD 72 G1OUT4 G2IN3 150 71 G1OUT3 G2IN2 151 70 G1OUT2 G2IN1 152 69 G1OUT1 G2IN0 153 68 G1OUT0 VDD 154 67 VSS VSS 155 66 VDD 65 G2OUT9 B1IN9 156 64 G2OUT8 B1IN8 157 B1IN7 158 63 G2OUT7 B CH FIFO B1IN6 159 62 G2OUT6 B1IN5 160 61 G2OUT5 B1IN4 161 60 VSS B1IN3 162 59 VDD B1IN2 163 58 G2OUT4 B1IN1 164 57 G2OUT3 56 G2OUT2 B1IN0 165 TIMING GENERATOR B2IN9 166 55 G2OUT1 B2IN8 167 54 G2OUT0 B2IN7 168 53 VSS B2IN6 169 52 VDD B2IN5 170 51 TEST1 B2IN4 171 50 B1OUT9 B2IN3 172 49 B1OUT8 48 B1OUT7 B2IN2 173 B2IN1 174 47 B1OUT6 CLK SEL 46 B1OUT5 B2IN0 175 45 VSS VDD TEST0 B1OUT4 B1OUT3 B1OUT2 B1OUT1 B1OUT0 VSS VDD B2OUT9 B2OUT8 B2OUT7 B2OUT6 B2OUT5 VSS VDD B2OUT4 B2OUT3 B2OUT2 SELBA –2– B2OUT1 SELGA B2OUT0 SELRA VSS CLKSEL VDD VSS NC CMOSCK NC NC POLSLA VSS BEDGE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GEDGE 8 REDGE 7 NC 6 HDEDGE 5 HDSEL 4 HD 3 XCLR 2 SELB 1 PECLCK VDD 176 CXD3504R VSS R2OUT5 R2OUT6 R2OUT7 R2OUT8 R2OUT9 TEST3 VDD VSS R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 VDD VSS R1OUT5 R1OUT6 R1OUT7 R1OUT8 R1OUT9 VDD VSS R1IN9 R1IN8 R1IN7 R1IN6 R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN9 R2IN8 R2IN7 R2IN6 R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 R2IN0 VDD Pin Configuration 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS 133 88 VDD G1IN9 134 87 R2OUT4 G1IN8 135 86 R2OUT3 G1IN7 136 85 R2OUT2 G1IN6 137 84 R2OUT1 G1IN5 138 83 R2OUT0 G1IN4 139 82 VSS G1IN3 140 81 VDD G1IN2 141 80 TEST2 G1IN1 142 79 G1OUT9 G1IN0 143 78 G1OUT8 G2IN9 144 77 G1OUT7 G2IN8 145 76 G1OUT6 G2IN7 146 75 G1OUT5 G2IN6 147 74 VSS G2IN5 148 73 VDD G2IN4 149 72 G1OUT4 G2IN3 150 71 G1OUT3 G2IN2 151 70 G1OUT2 G2IN1 152 69 G1OUT1 G2IN0 153 68 G1OUT0 VDD 154 67 VSS VSS 155 66 VDD B1IN9 156 65 G2OUT9 B1IN8 157 64 G2OUT8 B1IN7 158 63 G2OUT7 B1IN6 159 62 G2OUT6 B1IN5 160 61 G2OUT5 B1IN4 161 60 VSS B1IN3 162 59 VDD B1IN2 163 58 G2OUT4 B1IN1 164 57 G2OUT3 B1IN0 165 56 G2OUT2 B2IN9 166 55 G2OUT1 B2IN8 167 54 G2OUT0 B2IN7 168 53 VSS B2IN6 169 52 VDD B2IN5 170 51 TEST1 B2IN4 171 50 B1OUT9 B2IN3 172 49 B1OUT8 B2IN2 173 48 B1OUT7 B2IN1 174 47 B1OUT6 B2IN0 175 46 B1OUT5 45 VSS VDD TEST0 B1OUT4 B1OUT3 B1OUT2 B1OUT1 B1OUT0 VSS VDD B2OUT9 B2OUT8 B2OUT7 B2OUT6 B2OUT5 VSS VDD B2OUT4 B2OUT3 B2OUT2 SELBA –3– B2OUT1 SELGA B2OUT0 SELRA VSS CLKSEL VDD VSS NC CMOSCK NC NC POLSLA VSS BEDGE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GEDGE 8 REDGE 7 NC 6 HDEDGE 5 HDSEL 4 HD 3 XCLR 2 SELB 1 PECLCK VDD 176 CXD3504R Pin Description Pin No. Symbol Description I/O Input pin for open status 1 VSS P GND 2 PECLCK I Very little amp. clock input∗1 3 NC 4 CMOSCK I CMOS clock input∗2 5 VSS P GND 6 CLKSEL I 0: PECL, 1: CMOS L 7 SELRA I SELA (Data path selection A) for R L 8 SELGA I SELA (Data path selection A) for G L 9 SELBA I SELA (Data path selection A) for B L 10 SELB I Data path selection B L 11 XCLR I 0: Direct Reset H 12 HD I Horizontal sync signal input 13 HDSEL I HD selection (0: ↓, 1: ↑) L 14 HDEDGE I CK trigger selection of HD (0: ↓, 1: ↑) L 15 NC 16 REDGE I CK trigger selection of R (0: ↓, 1: ↑) L 17 GEDGE I CK trigger selection of G (0: ↓, 1: ↑) L 18 BEDGE I CK trigger selection of B (0: ↓, 1: ↑) L 19 POLSLA I SELA polarity selection L 20 NC 21 NC 22 VDD P Power supply 23 VSS P GND 24 B2OUT0 O B2 output 25 B2OUT1 O B2 output 26 B2OUT2 O B2 output 27 B2OUT3 O B2 output 28 B2OUT4 O B2 output 29 VDD P Power Supply 30 VSS P GND 31 B2OUT5 O B2 output 32 B2OUT6 O B2 output 33 B2OUT7 O B2 output Reserve ∗1 Connect to GND or VDD when using CMOS clock. ∗2 Connect to GND or VDD when using small amplitude clock. –4– CXD3504R Pin No. Symbol Description I/O 34 B2OUT8 O B2 output 35 B2OUT9 O B2 output 36 VDD P Power supply 37 VSS P GND 38 B1OUT0 O B1 output 39 B1OUT1 O B1 output 40 B1OUT2 O B1 output 41 B1OUT3 O B1 output 42 B1OUT4 O B1 output 43 TEST0 I 1: Test mode 44 VDD P Power supply 45 VSS P GND 46 B1OUT5 O B1 output 47 B1OUT6 O B1 output 48 B1OUT7 O B1 output 49 B1OUT8 O B1 output 50 B1OUT9 O B1 output 51 TEST1 I 1: Test mode 52 VDD P Power supply 53 VSS P GND 54 G2OUT0 O G2 output 55 G2OUT1 O G2 output 56 G2OUT2 O G2 output 57 G2OUT3 O G2 output 58 G2OUT4 O G2 output 59 VDD P Power supply 60 VSS P GND 61 G2OUT5 O G2 output 62 G2OUT6 O G2 output 63 G2OUT7 O G2 output 64 G2OUT8 O G2 output 65 G2OUT9 O G2 output 66 VDD P Power supply 67 VSS P GND 68 G1OUT0 O G1 output Input pin for open status L L –5– CXD3504R Pin No. Symbol I/O 69 G1OUT1 O G1 output 70 G1OUT2 O G1 output 71 G1OUT3 O G1 output 72 G1OUT4 O G1 output 73 VDD P Power supply 74 VSS P GND 75 G1OUT5 O G1 output 76 G1OUT6 O G1 output 77 G1OUT7 O G1 output 78 G1OUT8 O G1 output 79 G1OUT9 O G1 output 80 TEST2 I 1: Test mode 81 VDD P Power supply 82 VSS P GND 83 R2OUT0 O R2 output 84 R2OUT1 O R2 output 85 R2OUT2 O R2 output 86 R2OUT3 O R2 output 87 R2OUT4 O R2 output 88 VDD P Power supply 89 VSS P GND 90 R2OUT5 O R2 output 91 R2OUT6 O R2 output 92 R2OUT7 O R2 output 93 R2OUT8 O R2 output 94 R2OUT9 O R2 output 95 TEST3 I 1: Test mode 96 VDD P Power supply 97 VSS P GND 98 R1OUT0 O R1 output 99 R1OUT1 O R1 output 100 R1OUT2 O R1 output 101 R1OUT3 O R1 output 102 R1OUT4 O R1 output 103 VDD P Power supply 104 VSS P GND Description Input pin for open status L L –6– CXD3504R Pin No. Symbol Description I/O 105 R1OUT5 O R1 output 106 R1OUT6 O R1 output 107 R1OUT7 O R1 output 108 R1OUT8 O R1 output 109 R1OUT9 O R1 output 110 VDD P Power supply 111 VSS P GND 112 R1IN9 I R1 input 113 R1IN8 I R1 input 114 R1IN7 I R1 input 115 R1IN6 I R1 input 116 R1IN5 I R1 input 117 R1IN4 I R1 input 118 R1IN3 I R1 input 119 R1IN2 I R1 input 120 R1IN1 I R1 input 121 R1IN0 I R1 input 122 R2IN9 I R2 input 123 R2IN8 I R2 input 124 R2IN7 I R2 input 125 R2IN6 I R2 input 126 R2IN5 I R2 input 127 R2IN4 I R2 input 128 R2IN3 I R2 input 129 R2IN2 I R2 input 130 R2IN1 I R2 input 131 R2IN0 I R2 input 132 VDD P Power supply 133 VSS P GND 134 G1IN9 I G1 input 135 G1IN8 I G1 input 136 G1IN7 I G1 input 137 G1IN6 I G1 input 138 G1IN5 I G1 input 139 G1IN4 I G1 input 140 G1IN3 I G1 input –7– Input pin for open status CXD3504R Pin No. Symbol Description I/O 141 G1IN2 I G1 input 142 G1IN1 I G1 input 143 G1IN0 I G1 input 144 G2IN9 I G2 input 145 G2IN8 I G2 input 146 G2IN7 I G2 input 147 G2IN6 I G2 input 148 G2IN5 I G2 input 149 G2IN4 I G2 input 150 G2IN3 I G2 input 151 G2IN2 I G2 input 152 G2IN1 I G2 input 153 G2IN0 I G2 input 154 VDD P Power supply 155 VSS P GND 156 B1IN9 I B1 input 157 B1IN8 I B1 input 158 B1IN7 I B1 input 159 B1IN6 I B1 input 160 B1IN5 I B1 input 161 B1IN4 I B1 input 162 B1IN3 I B1 input 163 B1IN2 I B1 input 164 B1IN1 I B1 input 165 B1IN0 I B1 input 166 B2IN9 I B2 input 167 B2IN8 I B2 input 168 B2IN7 I B2 input 169 B2IN6 I B2 input 170 B2IN5 I B2 input 171 B2IN4 I B2 input 172 B2IN3 I B2 input 173 B2IN2 I B2 input 174 B2IN1 I B2 input 175 B2IN0 I B2 input 176 VDD P Power supply –8– Input pin for open status CXD3504R Electrical Characteristics Item (Input/Output level/VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C) Symbol High level input voltage VIH Low level input voltage VIL Conditions Min. Typ. Max. Unit 0.7VDD — — V — — 0.2VDD V VDD – 0.8 — — V — — 0.4 V –10 — 10 µA ∗1, ∗2, ∗3 CMOS input Applicable pins ∗1, ∗2, ∗3 High level output voltage VOH IOH = –12mA Low level output voltage VOL IOL = 12mA Input leak current IIL VI = VSS, VDD Pull-up resistor RUP 80 160 320 kΩ ∗2 Pull-down resistor RDN 90 180 360 kΩ ∗3 ∗1 ∗2 ∗3 ∗4 ∗4 Input pins except PECLCK XCLR CLKSEL, SELRA, SELGA, SELBA, SELB, HDSEL, HDEDGE, REDGE, GEDGE, BEDGE, POLSLA All output pins AC Characteristics PECLCK (CMOSCK) t1 t2 HD t3 t4 Input Data (R, G, B ) d in 99b d in 100b d in 1c d in 2c d in 3c d in 4c d in 5c d in 6c d in 7c d in 8c d in 9c d in 10c d in 11c d in 12c d in 13c t5 d in 95b Delay Output d in 95a , , Through Output d in 96b d in 97b d in 98b d in 99b d in 100b No Care d in 4c d in 5c d in 6c d in 7c d in 8c d in 9c d in 96a d in 97a d in 98a d in 99a d in 100a No Care d in 4b d in 5b d in 6b d in 7b d in 8b d in 9b Symbol Min. Max. Unit f — 80 MHz HD set-up time to PECLCK bar t1 1.5 — ns HD hold time from PECLCK bar t2 4.5 — ns R, G, B input data set-up time to PECLCK bar t3 1 — ns R, G, B input data hold time from PECLCK bar t4 6.5 — ns R, G, B output data delay from PECLCK t5 4 13 ns HD set-up time to CMOSCK bar t1 2 — ns HD hold time from CMOSCK bar t2 3 — ns R, G, B input data set-up time to CMOSCK bar t3 1.5 — ns R, G, B input data hold time from CMOSCK bar t4 4.5 — ns R, G, B output data delay from CMOSCK t5 3 12 ns Item Input frequency Note: The above timing values are for PECCLK (CMOSCK) = 80MHz and an output pin capacitance of 20pF. –9– CXD3504R Description of Operation 1) The following describes only R, but the operation for G and B is the same. SELRA:SELB = 0:0 R2IN → through → R1OUT R1IN → delay → R2OUT SELRA:SELB = 0:1 R2IN → delay → R1OUT R1IN → through → R2OUT SELRA:SELB = 1:0 R1IN → through → R1OUT R2IN → delay → R2OUT SELRA:SELB = 1:1 R1IN → delay → R1OUT R2IN → through → R2OUT However, POLSLA = 0 2) Be sure to set XCLR to "0" for a clock or more while HD is "1". (when HDSEL = 0) Also, input the HD signal with a "0" period length of 6 clocks or more. Very Little Signal Amplifier (VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C) Item Symbol Min. Typ. Max. Unit High level input voltage VIH 0.4 — 3.6 V Low level input voltage VIL 0 — 3.2 V Input frequency Input amplitude∗1 f — — 80 MHz Vpp 0.4 — — V Applicable pins: PECLCK (Pin 2) ∗1 Input the signal through a capacitor. Also, this amplitude is the value between the through capacitor and the input pin. PECLCK 2 – 10 – CXD3504R Application Circuit From CXD2467Q 3.3V 0.1µ 0.1µ 0.1µ 0.1µ 10µ/16V VSS R2OUT5 R2OUT6 R2OUT7 R2OUT8 TEST3 R2OUT9 VSS VDD R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 VSS VDD R1OUT5 R1OUT6 R1OUT7 135 G1IN8 R2OUT3 86 136 G1IN7 R2OUT2 85 137 G1IN6 R2OUT1 84 138 G1IN5 R2OUT0 83 139 G1IN4 VSS 82 140 G1IN3 VDD 81 141 G1IN2 TEST2 80 142 G1IN1 G1OUT9 79 143 G1IN0 G1OUT8 78 144 G2IN9 G1OUT7 77 145 G2IN8 G1OUT6 76 146 G2IN7 G1OUT5 75 147 G2IN6 VSS 74 148 G2IN5 VDD 73 149 G2IN4 G1OUT4 72 150 G2IN3 G1OUT3 71 151 G2IN2 G1OUT2 70 152 G2IN1 G1OUT1 69 153 G2IN0 G1OUT0 68 154 VDD VSS 67 155 VSS VDD 66 0.1µ 0.1µ 0.1µ 0.1µ G2OUT9 65 156 B1IN9 157 B1IN8 G2OUT8 64 158 B1IN7 G2OUT7 63 159 B1IN6 G2OUT6 62 160 B1IN5 G2OUT5 61 161 B1IN4 VSS 60 162 B1IN3 VDD 59 163 B1IN2 G2OUT4 58 164 B1IN1 G2OUT3 57 165 B1IN0 G2OUT2 56 166 B2IN9 G2OUT1 55 167 B2IN8 G2OUT0 54 168 B2IN7 VSS 53 169 B2IN6 VDD 52 170 B2IN5 TEST1 51 171 B2IN4 B1OUT9 50 172 B2IN3 B1OUT8 49 0.1µ 0.1µ 0.1µ VDD TEST0 B1OUT4 B1OUT3 B1OUT2 B1OUT1 B1OUT0 VSS VDD B2OUT9 B2OUT8 B2OUT7 B2OUT6 B2OUT5 VSS VDD B2OUT4 B2OUT3 B2OUT2 B2OUT1 B2OUT0 VSS VDD NC NC POLSLA 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 BEDGE 8 GEDGE 7 REDGE 6 NC 5 HDEDGE 4 HDSEL SELBA 3 HD SELGA 2 XCLR SELRA 1 SELB CLKSEL B1OUT5 46 VSS 175 B2IN0 CMOSCK B1OUT6 47 NC B1OUT7 48 174 B2IN1 PECLCK 173 B2IN2 176 VDD 0.1µ VDD 88 R2OUT4 87 VSS 0.1µ R1OUT8 134 G1IN9 R1OUT9 VSS VDD R1IN9 R1IN8 R1IN7 R1IN6 R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN9 R2IN8 R2IN7 R2IN6 R2IN5 R2IN4 R2IN3 R2IN2 R2IN1 VDD 133 VSS R2IN0 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 0.1µ 0.1µ VSS 45 0.1µ 0.1µ To CXA3197R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – CXD3504R Package Outline Unit: mm 176PIN LQFP(PLASTIC) 26.0 ± 0.2 1.6 MAX 24.0 ± 0.2 (1.4) 132 89 0.1 133 88 176 45 A 1 0.5 + 0.05 0.2 – 0.04 44 0.1 M + 0.07 0.125 – 0.02 0.5 ± 0.2 0.1 ± 0.1 0 ° to 10 ° PACKAGE STRUCTURE DETAIL A SONY CODE LQFP-176P-L061 EIAJ CODE P-LQFP176-24X24-0.5 JEDEC CODE – 12 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 1.8 g Sony Corporation