SONY CXD3508TQ

CXD3508TQ
LCD Interface IC
For the availability of this product, please contact the sales office.
Description
The CXD3508TQ is a LCD interface IC for the color
LCD module ACX704AKM driver.
100 pin TQFP (Plastic)
Features
• Generates the color LCD module ACX704AKM drive
pulse.
• Standby mode function
• Thin package (100-pin TQFP)
Applications
PDA, compact LCD monitor, etc.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
Vss – 0.3 to +5.5
• Input voltage
VI
Vss – 0.3 to VDD + 0.3
• Output voltage
VO
Vss – 0.3 to VDD + 0.3
• Operating temperature Topr
–25 to +75
• Storage temperature
Tstg
–55 to +150
V
V
V
°C
°C
Recommended Operating Conditions
• Supply voltage
VDD
3.0 to 3.6
• Operating temperature Topr
–10 to +60
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00228-PS
CXD3508TQ
Block Diagram
R0
9
R1
8
31 to 28 R01, R11, R21, R31
R2
7
43 to 41 XR01, XR11, XR21, XR31
R3
6
94 to 97 R02, R12, R22, R32
G0 13
DATA IN
82 to 89 XR02, XR12, XR22, XR32
G1 12
G2 11
G3 10
B0 17
35 to 32 G01, G11, G21, G31
Serial/
Parallel
Conversion
Block
47 to 44 XG01, XG11, XG21, XG31
90 to 93 G02, G12, G22, G32
78 to 81 XG02, XG12, XG22, XG32
B1 16
39 to 36 B01, B11, B21, B31
B2 15
53, 52,
49, 48
B3 14
FA 24
86 to 89 B02, B12, B22, B32
72 to 74, XB02, XB12, XB22, XB32
77
MCK 20
PCI 21
Hsync/DENB 18
XB01, XB11, XB21, XB31
27 PCO
Power CTR.
64 HST1
H Counter
Delay
SLIN 22
65 XHST1
66 HST2
67 XHST2
60 HCK1
H Timing Pulse GEN.
Delay
61 XHCK1
62 HCK2
63 XHCK2
68 OE1
69 XOE1
V sync 19
V Counter
70 OE2
71 XOE2
54 VST
55 XVST
V Timing Pulse GEN.
58 VCK
59 XVCK
56 ENB
57 XENB
98 FRP
Timing Generator Block
–2–
CXD3508TQ
VSS
XB11
XB01
VST
XVST
ENB
XENB
VCK
XVCK
HCK1
XHCK1
HCK2
XHCK2
HST1
XHST1
HST2
XHST2
OE1
XOE1
OE2
XOE2
XB02
XB12
XB22
VSS
Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD 76
50 VDD
XB32 77
49 XB21
XG02 78
48 XB31
XG12 79
47 XG01
XG22 80
46 XG11
XG32 81
45 XG21
XR02 82
44 XG31
XR12 83
43 XR01
XR22 84
42 XR11
XR32 85
41 XR21
B02 86
40 XR31
B12 87
39 B01
B22 88
38 B11
B32 89
37 B21
G02 90
36 B31
G12 91
35 G01
G22 92
34 G11
G32 93
33 G21
R02 94
32 G31
R12 95
31 R01
R22 96
30 R11
R32 97
29 R21
FRP 98
28 R31
TESTV 99
27 PCO
VSS
R0
FA
R1
TESTP
R2
SLIN
R3
PCI
CLR
MCK
VSS
Vsync
TEST2
–3–
Hsync/DENB
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
B0
8
B1
7
B2
6
B3
5
G0
4
G1
3
G2
2
G3
1
VSS
26 VDD
TEST1
VDD 100
CXD3508TQ
Pin Description
Pin
No.
Symbol
I/O
Description
Input pin for
open status
1
VSS
2
TEST1
I
Test signal input
DWN∗1
3
TEST2
I
Test signal input
DWN∗1
4
VSS
—
5
CLR
I
System reset
6
R3
I
Red signal input (MSB)
—
7
R2
I
Red signal input
—
8
R1
I
Red signal input
—
9
R0
I
Red signal input (LSB)
—
10
G3
I
Green signal input (MSB)
—
11
G2
I
Green signal input
—
12
G1
I
Green signal input
—
13
G0
I
Green signal input (LSB)
—
14
B3
I
Blue signal input (MSB)
—
15
B2
I
Blue signal input
—
16
B1
I
Blue signal input
—
17
B0
I
Blue signal input (LSB)
—
18
Hsync/DENB
I
Hsync/data enable pulse input
—
19
Vsync
I
Vsync pulse input
—
20
MCK
I
Dot clock input
—
21
PCI
I
Power control signal input
—
22
SLIN
I
Sync input signal mode switch
23
TESTP
I
Test signal input
DWN∗1
DWN∗1
24
FA
I
Data phase adjustment
DWN∗1
25
VSS
—
GND
—
26
VDD
—
Power supply
—
27
PCO
O
Power control signal output
—
28
R31
O
Red signal output
—
29
R21
O
Red signal output
—
30
R11
O
Red signal output
—
31
R01
O
Red signal output
—
32
G31
O
Green signal output
—
33
G21
O
Green signal output
—
—
—
GND
GND
—
UP∗2
∗1 Built-in pull-down resistor (82.5kΩ)
∗2 Built-in pull-up resistor (82.5kΩ)
–4–
CXD3508TQ
Pin
No.
Symbol
I/O
Description
Input pin for
open status
34
G11
O
Green signal output
—
35
G01
O
Green signal output
—
36
B31
O
Blue signal output
—
37
B21
O
Blue signal output
—
38
B11
O
Blue signal output
—
39
B01
O
Blue signal output
—
40
XR31
O
Red signal output (inverse)
—
41
XR21
O
Red signal output (inverse)
—
42
XR11
O
Red signal output (inverse)
—
43
XR01
O
Red signal output (inverse)
—
44
XG31
O
Green signal output (inverse)
—
45
XG21
O
Green signal output (inverse)
—
46
XG11
O
Green signal output (inverse)
—
47
XG01
O
Green signal output (inverse)
—
48
XB31
O
Blue signal output (inverse)
—
49
XB21
O
Blue signal output (inverse)
—
50
VDD
—
Power supply
—
51
VSS
—
GND
—
52
XB11
O
Blue signal output (inverse)
—
53
XB01
O
Blue signal output (inverse)
—
54
VST
O
VST pulse output
—
55
XVST
O
VST pulse output (inverse)
—
56
ENB
O
ENB pulse output
—
57
XENB
O
ENB pulse output (inverse)
—
58
VCK
O
VCK pulse output
—
59
XVCK
O
VCK pulse output (inverse)
—
60
HCK1
O
HCK1 pulse output
—
61
XHCK1
O
HCK1 pulse output (inverse)
—
62
HCK2
O
HCK2 pulse output
—
63
XHCK2
O
HCK2 pulse output (inverse)
—
64
HST1
O
HST1 pulse output
—
65
XHST1
O
HST1 pulse output (inverse)
—
66
HST2
O
HST2 pulse output
—
67
XHST2
O
HST2 pulse output (inverse)
—
–5–
CXD3508TQ
Pin
No.
Symbol
I/O
Description
Input pin for
open status
68
OE1
O
OE1 pulse output
—
69
XOE1
O
OE1 pulse output (inverse)
—
70
OE2
O
OE2 pulse output
—
71
XOE2
O
OE2 pulse output (inverse)
—
72
XB02
O
Blue signal output (inverse)
—
73
XB12
O
Blue signal output (inverse)
—
74
XB22
O
Blue signal output (inverse)
—
75
VSS
—
GND
—
76
VDD
—
Power supply
—
77
XB32
O
Blue signal output (inverse)
—
78
XG02
O
Green signal output (inverse)
—
79
XG12
O
Green signal output (inverse)
—
80
XG22
O
Green signal output (inverse)
—
81
XG32
O
Green signal output (inverse)
—
82
XR02
O
Red signal output (inverse)
—
83
XR12
O
Red signal output (inverse)
—
84
XR22
O
Red signal output (inverse)
—
85
XR32
O
Red signal output (inverse)
—
86
B02
O
Blue signal output
—
87
B12
O
Blue signal output
—
88
B22
O
Blue signal output
—
89
B32
O
Blue signal output
—
90
G02
O
Green signal output
—
91
G12
O
Green signal output
—
92
G22
O
Green signal output
—
93
G32
O
Green signal output
—
94
R02
O
Red signal output
—
95
R12
O
Red signal output
—
96
R22
O
Red signal output
—
97
R32
O
Red signal output
—
98
FRP
O
Polarity inversion pulse signal output
—
99
TESTV
I
Test signal input
100
VDD
—
DWN∗1
Power supply
—
∗1 Built-in pull-down resistor (82.5kΩ)
–6–
CXD3508TQ
Electrical Characteristics
DC Characteristics
Item
Symbol
Supply voltage
VDD
Current
consumption
IDD
Input voltage 1
(VDD = 3.0 to 3.6V, Ta = –25 to + 75°C)
VIH1
VIL1
Applicable pins
VDD
Vt–
Input current 1
| IIH1 |
Input current 2
| IIL2 |
| IIH2 |
| IIL3 |
Input current 3
| IIH3 |
Output voltage
1
VOL1
VOH1
VOL2
Output voltage
2
VOH2
Output voltage
3
VOL3
Output voltage
4
VOL4
VOH3
VOH4
Typ.
Max.
Unit
—
3.0
3.3
3.6
V
MCK
LVTTL input
cell
All output pins excluding
MCK
LVTTL
Schmitt trigger
input cell
Vt+ – Vt–
| IIL1 |
Min.
No load, Ta = 25°C,
VDD = 3.3V,
MCK: 5.58MHz
—
Vt+
Input voltage 2
Conditions
R0, R1, R2, R3, G0, G1,
G2, G3, B0, B1, B2, B3,
Hsync/DENB, Vsync,
MCK, PCI
TEST1, TEST2,
SLIN, TESTV, FA,
TESTP
mA
2.0
0.8
V
2.0
V
0.5
0.2
VI = 0V
1.0
VI = VDD
1.0
µA
VI = 0V
CLR
0.9
10
100
VI = VDD
3.0
VI = 0V
3.0
µA
µA
VI = VDD
10
IOL1 = 0.75mA
100
0.2
ENB, XENB
V
IOH1 = –0.50mA VDD – 0.2
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32,
PCO, VST, XVST, VCK,
XVCK, OE1, XOE1, OE2,
XOE2, FRP
IOL2 = 1.5mA
0.2
V
IOH2 = –1.0mA VDD – 0.2
HST1, XHST1,
HST2, XHST2
IOL3 = 3.0mA
HCK1, XHCK1,
HCK2, XHCK2
IOL4 = 4.5mA
0.2
IOH3 = –2.0mA VDD – 0.2
IOH4 = –3.0mA VDD – 0.2
–7–
V
0.2
V
CXD3508TQ
AC Characteristics
(VDD = 3.0 to 3.6V, Ta = –10 to +60°C)
Item
Symbol
Applicable pins
HCK, HST
time difference
∆tHST-HCKU
∆tHST-HCKD
HCK1, HCK2, XCHK1,
XHCK2, HST1, HST2,
XHST1, XHST2
Data output
rise time
tRD
Data output
fall time
tFD
H pulse output
rise time
tRHP
H pulse output
fall time
tFHP
V pulse output
rise time
tRVP
V pulse output
fall time
tFVP
ENB pulse
output rise time
tREP
ENB pulse
output fall time
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
Conditions
Min.
Typ.
GND – VDD
(0 – 90%)
Max.
Unit
15∗2
ns
40
ns
VDD – GND
(100 – 10%)
40
HCK1, HCK2,
XCHK1, XHCK2,
HST1, HST2,
XHST1, XHST2
GND – VDD
(0 – 90%)
30
VDD – GND
(100 – 10%)
30
VCK, XVCK,
VST, XVST,
OE1, OE2, XOE1,
XOE2, FRP, PCO
GND – VDD
(0 – 90%)
60
VDD – GND
(100 – 10%)
60
GND – VDD
(0 – 90%)
80
VDD – GND
(100 – 10%)
80
ENB, XENB
tFEP
HCK1, HCK2,
XHCK1, XHCK2,
DATA
setup time
tSTP
HCK1, HCK2, XHCK1,
XHCK2, R01, R11, R21,
R31, R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31, G02,
∗3
G12, G22, G32, XG01,
XG11, XG21, XG31,
XG02, XG12, XG22,
XG32, B01, B11, B21,
B31, B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
HCK, VCK duty
dHCK
dVCK
HCK1, HCK2, XHCK1,
XHCK2, VCK, XVCK
∗4
ns
ns
ns
35
50
120
ns
48
50
52
%
∗1 CL of each output pin is shown below.
• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11,
G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21,
B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, ENB, XENB: CL = 70pF
• HCK1, HCK2, XHCK1, XHCK2
: CL = 150pF
• HST, XHST, VCK, XVCK
: CL = 100pF
• VST, XVST
: CL = 85pF
• OE1, XOE1, OE2, XOE2, PCO, FRP : CL = 60pF
∗2 The absolute value of time difference (HST1, XHST1, HCK1, XHCK1) is within 15ns.
In the same manner, the absolute value of time difference (HST2, XHST2, HCK2, XHCK2) is within 15ns.
∗3 tSTP: tST1D, tST1U, tST2D, tST2U
∗4 dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100
–8–
CXD3508TQ
Timing Definition
H system
tHH
tHL
VDD
HCK1
50%
50%
50%
GND
VDD
50%
XHCK1
GND
∆tH
∆tH
VDD
HCK2
50%
50%
50%
GND
VDD
50%
XHCK2
50%
GND
∆tH
∆tH
VDD
HST1
(HST2)
50%
50%
GND
VDD
XHST1
(XHST2)
50%
50%
GND
VDD
HCK1
(HCK2)
50%
50%
GND
VDD
XHCK1
(XHCK2)
50%
50%
GND
∆tHST-HCKU
∆tHST-HCKD
–9–
CXD3508TQ
V system
tVH
tVL
VDD
VCK
50%
50%
50%
GND
VDD
XVCK
50%
50%
GND
∆tV
∆tV
DATA
VDD
HCK1
50%
50%
GND
VDD
50%
XHCK1
50%
GND
VDD
HCK2
50%
50%
GND
VDD
50%
XHCK2
GND
VDD
DATA
GND
tST1D
tST2D
tSTX1U
tST1U
tSTX2U
– 10 –
tST2U
tSTX1D
tSTX2D
CXD3508TQ
PCI, PCO
These pins control to turn power on/off of the ACX704AKM and the CXD2475TQ when the LCD is turned
on/off.
Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM and the CXD2475TQ.
• When LCD is on, effective screen is displayed after entire white display (2 fields).
• When LCD is off, LCD is off after entire white display.
Power Up Sequence
VDD
VDD
0
VDD
CLR
0
PCI
Inactive (low)
Active
PCO
Inactive (low)
Active
Pulse∗
Inactive (low)
Active
DATA (out)
Inactive (low)
White Data
MCK
Hsync
Vsync
DENB
DATA (in)
Valid
2 Fields
Invalid (low)
Valid
1 Field (typ.) 288H (min.)
Power Down Sequence (Standby)
Standby Mode
PCI
Active (high)
Inactive (low)
Inactive (low)
Active (high)
PCO
VDD
VDD
DATA
Pulse∗
0
Valid
Invalid (all low)
White Data
Invalid (all low)
Valid
Vsync
DENB
3 Fields
10 Fields
∗ HST1, HST2, XHST1, XHST2, HCK1, HCK2, XHCK1, XHCK2, VST, XVST, VCK, XVCK,
ENB. XENB, OE1, XOE1, OE2, XOE2, FRP
– 11 –
CXD3508TQ
FA
This is a selector switch for phase relationship between data and other pulses.
(Normally, set to low.)
MCK
HCK1
XHCK1
HCK2
XHCK2
(FA: L)
Default
(FA: H)
OUTPUT DATA
R/G/B 01 to 31
Invalid
2
4
6
8
OUTPUT DATA
R/G/B 02 to 31
Invalid
1
3
5
7
OUTPUT DATA
R/G/B 01 to 31
Invalid
2
4
6
8
OUTPUT DATA
R/G/B 02 to 31
Invalid
1
3
5
7
SLIN
This is a selector switch for input sync signal mode.
SLIN: LOW → Hsync + Vsync Mode
SLIN: HIGH → DENB ONLY Mode (Vsync input is invalid.)
– 12 –
– 13 –
DATA
DENB∗
Hsync∗
MCK
DATA
DENB∗
Hsync∗
MCK
315
320
thsw
∗ Input either Hsync + Vsync or DENB as sync signal input.
thss
307 308 309 310 311 312 313 314 315 316 317 318 319 320
310
Horizontal Direction Input Signal Timing Chart
325
tds
1
tdes
16 dots
tdh
330
2
340
4 dots (min.)
320
tdeh
16 dots
345
350
0
1
2
3
4
tch
5
5
tclk
6
tcl
7
8
9 10 11
352 dots
tch, tcl
tds
tdh
tdes
tdeh
thss
thsw
MCK low, high pulse width
Hsync low pulse width
Hsync setup time
DENB hold time
DENB setup time
DATA hold time
DATA setup time
ftch
Symbol
MCK frequency
Item
4tclk
10ns
15ns
10ns
15ns
10ns
3MHz
Min.
0.5tclk
5.58MHz
Typ.
16tclk
8MHz
Max.
Input Signal AC Characteristics
(VDD = 3.0 to 3.6V, Ta = –25 to +75°C)
32 dots
335
CXD3508TQ
– 14 –
DATA
DENB∗
Vsync∗
Hsync∗
DENB∗
Vsync∗
Hsync∗
235
tvhde
240
tvsw
10 lines
245
∗ Input either Hsync + Vsync or DENB as sync signal input.
230
Vertical Direction Input Signal Timing Chart
250
260
0
5
10
15
334tclk
2 lines
tvsw
Vsync low pulse width
Min.
tvhde
Symbol
Vsync falling edge
→ Hsync rising edge
Item
Typ.
14 lines
349tclk
Max.
Input Signal AC Characteristics
(VDD = 3.0 to 3.6V, Ta = –25 to +75°C)
14 lines
255
264 lines
CXD3508TQ
Output
Input
– 15 –
FRP
XVCK
VCK
XVST
VST
XENB
ENB
XOE2
OE2
XOE1
OE1
XHCK2
HCK2
XHST2
HST2
XHCK1
HCK1
XHST1
HST1
R/G/B
01 to 31
R/G/B
02 to 32
DATA
DENB
Hsync
MCK
16 dot
320
328
334
32 dot
330
16 dot
344
340
4 dot
348
304
320
334
334
4 dot
340
342
350
346
0
0
3
4
1 23 4 5 6 7 8 9
0
1
310
269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 315 317 319
300
2
290
316
317
318
319
320
270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320
280
Horizontal Direction Timing Chart
5
6
7
8
20
352 dot
9
11 13 15 17 19 21 23
10 12 14 16 18 20 22 24
10
CXD3508TQ
Output
Input
– 16 –
FRP (E)∗
FRP (O)∗
XOE2
OE2
XOE1
OE1
XENB
ENB
XVCK
VCK
XVST
VST
DENB
Vsync
Hsync
240
245
250
255
FRP (E): FRP output timing at even field.
∗ FRP (O): FRP output timing at odd field.
10 line
Vertical Direction Timing Chart
14 line
260
0
5
10
15
20
264 lines
CXD3508TQ
CXD3508TQ
Application Circuit
To ACX704AKM
VDD
VSS
XB11
VST
XB01
ENB
XVST
VCK
XENB
HCK1
XVCK
HCK2
XHCK1
HST1
XHCK2
HST2
XHST1
OE1
76 VDD
XHST2
OE2
XOE1
XB02
XOE2
XB12
VSS
XB22
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD 50
XB21 49
78 XG02
XB31 48
79 XG12
XG01 47
80 XG22
XG11 46
81 XG32
XG21 45
82 XR02
XG31 44
83 XR12
XR01 43
84 XR22
XR11 42
85 XR32
XR21 41
86 B02
XR31 40
87 B12
B01 39
88 B22
B11 38
89 B32
B21 37
90 G02
B31 36
91 G12
G01 35
92 G22
G11 34
93 G32
G21 33
94 R02
G31 32
95 R12
R01 31
96 R22
R11 30
97 R32
R21 29
R31 28
VSS
FA
SLIN
PCI
MCK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Vsync
8
B0
R0
7
B1
R1
6
B2
R2
5
B3
R3
4
G0
CLR
3
G1
VSS
2
G2
TEST2
1
G3
TEST1
VDD 26
VSS
100 VDD
PCO 27
TESTP
99 TESTV
Hsync/DENB
98 FRP
To ACX704AKM
To ACX704AKM
77 XB32
VDD
∗ To DC-DC Converter
Input
To CXD2475TQ
(Pins 9, 10)
VDD
∗ Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM
and the CXD2475TQ.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 17 –
CXD3508TQ
Package Outline
Unit: mm
TQFP-100P-L111
1.2 MAX
16.0 ± 0.3
1.0 ± 0.1
14.0 ± 0.2
0.4375
75
0.1
51
76
15.0 ± 0.2
50
A
26
100
1
25
0.2 ± 0.06
0.5
0.08
0.125 ±
0.05
M
0.1 ± 0.1
0 ° to 10 °
PACKAGE STRUCTURE
DETAIL A
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TQFP-100P-L111
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
P-TQFP100-14X14-0.5
LEAD MATERIAL
42ALLOY
PACKAGE WEIGHT
0.6g
JEDEC CODE
– 18 –
Sony Corporation