CXG1068N SP4T Antenna Switch for GSM Dual band For the availability of this product, please contact the sales office. Description The CXG1068N is a high power antenna switch MMIC for use in Dualband GSM handsets. One antenna can be routed to either of the 2Tx or 2Rx ports. This IC is designed using the Sony’s GaAs J-FET process which enable the CXG1068N to be operated with low voltage. Features • Low control voltage • Low insertion loss : 0.5 dB (Typ.) @900 MHz 0.65 dB (Typ.) @1.8 GHz • Small package : SSOP-20pin (Pin interval of 0.5 mm pitch) • High power handling : P1dB : 38 dBm (Typ.) 0/5 V control • Harmonics : –31 dBm (Max.) Pin=35 dBm, 0/5 V control 20 pin SSOP (Plastic) Operating Conditions (Ta=25 °C) Control voltage Vctl (H)–Vctl (L): 2.5 to 5 V Applications • Dualband GSM 900/GSM 1800 or GSM 900/GSM 1900 handsets. • Dualmode GSM/DECT handsets. Structure GaAs J-FET MMIC GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E98920A8X-TE CXG1068N Truth Table ON Pass Ant.-Tx1 Ant.-Tx2 Ant.-Rx1 Ant.-Rx2 CTL 1 H L L L CTL 2 L H L L CTL 3 L L H L CTL 3 H H L H CTL 4 L L L H CTL 4 H H H L Electrical Characteristics 1 (Ta=25 °C) Symbol Port Ant-Tx1, Tx2 Insertion loss IL Ant-Rx1, Rx2 Ant-Tx1, Tx2 Isolation ISO Ant-Rx1, Rx2 VSWR Harmonics 1dB compression Input power Switching speed TSW Control current Bias current ∗1 ∗2 ∗3 ∗4 : : : : VSWR 2fo 3fo P1dB Condition ∗1 ∗2 ∗3 ∗4 ∗1, ∗3 ∗2, ∗4 ∗1, ∗3 ∗2, ∗4 Ant-Tx1, Tx2 Ant-Tx1, Tx2 TSW Ictl IDD Pin=34.5 dBm, 880 to 915 MHz, VDD=5 V, 0/5 V Control Pin=32 dBm, 1710 to 1785 MHz, VDD=5 V, 0/5 V Control Pin=10 dBm, 925 to 960 MHz, VDD=3 V, 0/3 V Control Pin=10 dBm, 1805 to 1880 MHz, VDD=3 V, 0/3 V Control —2— ∗1 ∗2 ∗1 ∗2 Min. 20 17 25 20 35 34 Typ. 0.5 0.65 0.6 0.85 24 20 30 25 1.2 38 37 100 150 60 Max. 0.7 0.85 0.8 1.05 1.4 –31 –31 500 300 120 Unit dB dB dB dB dB dB dB dB dBm dBm dBm dBm ns µA µA CXG1068N Electrical Characteristics 2 (Ta=–35 to +85 °C) Symbol Port Ant-Tx1, Tx2 Insertion loss IL Ant-Rx1, Rx2 Ant-Tx1, Tx2 Isolation ISO Ant-Rx1, Rx2 VSWR Harmonics 1dB compression Input power Switching speed TSW Control current Bias current ∗1 ∗2 ∗3 ∗4 : : : : VSWR 2fo 3fo P1dB Condition ∗1 ∗2 ∗3 ∗4 ∗1, ∗3 ∗2, ∗4 ∗1, ∗3 ∗2, ∗4 Ant-Tx1, Tx2 Ant-Tx1, Tx2 TSW Ictl IDD Pin=34.5 dBm, 880 to 915 MHz, VDD=5 V, 0/5 V Control Pin=32 dBm, 1710 to 1785 MHz, VDD=5 V, 0/5 V Control Pin=10 dBm, 925 to 960 MHz, VDD=3 V, 0/3 V Control Pin=10 dBm, 1805 to 1880 MHz, VDD=3 V, 0/3 V Control —3— ∗1 ∗2 ∗1 ∗2 Min. 20 17 25 20 35 34 Typ. 0.5 0.65 0.6 0.85 24 20 30 25 1.2 38 37 100 150 60 Max. 0.9 1.05 1.0 1.25 1.4 –30 –30 500 350 150 Unit dB dB dB dB dB dB dB dB dBm dBm dBm dBm ns µA µA CXG1068N Package Outline/Pin Configuration GND Tx1 GND GND Ant Tx2 GND GND VDD Rx1 GND GND CTL1 Rx2 CTL2 GND CTL3 CTL3 CTL4 CTL4 20 1 20pin SSOP Package Block Diagram ON Ant Tx1 CTL1 ON Tx2 CTL2 ON Rx1 CTL3 CTL3 ON Rx2 CTL4 —4— CTL4 CXG1068N Recommended Circuit CRF (100pF) 11 Tx1 10 56kΩ 12 9 13 8 CRF (100pF) CRF (100pF) Ant L1 L1 Tx2 56kΩ 56kΩ 14 7 15 6 L1 CRF (100pF) VDD Cbypass (100pF) RCTL (1kΩ) CTL1 Cbypass (100pF) Rx1 L1 CXG1068N 16 5 17 4 Rx2 L1 RCTL (1kΩ) CTL2 Cbypass (100pF) 18 3 RCTL (1kΩ) CTL3 Cbypass (100pF) 19 2 RCTL (1kΩ) CTL4 Cbypass (100pF) 20 1 RCTL (1kΩ) CTL3 Cbypass (100pF) RCTL (1kΩ) CTL4 Cbypass (100pF) ∗ Recommended to use DC blocking capacitors (CRF) and bypass capacitors (Cbypass). Rctl : This resistor is used to give improved ESD performance. 1 kΩ is recommended. L1 : This inductor is used to give improved ESD performance. Absolute Maximum Ratings (Ta=25 °C) • Control voltage 7 • Operating temperature Topr –35 to +85 • Storage temperature Tstg –65 to +150 V °C °C —5— CXG1068N Unit : mm 20PIN SSOP(PLASTIC) 0.1 ∗5.0 ± 0.05 1.25MAX A 20 S 6.4 ± 0.2 ∗4.4 ± 0.05 11 A 10 1 0.5 0.1 b 0.1 S 0.1 M S A 0° to 10° (0.2) DETAIL B : SOLDER b = 0.2 ± 0.03 + 0.03 0.15 – 0.01 0.6 ± 0.15 0.1 ± 0.1 (0.15) b = 0.22 ± 0.05 0.25 0.17 ± 0.03 B (0.5) Package Outline DETAIL B : PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE SSOP-20P-L03 LEAD TREATMENT EIAJ CODE SSOP020-P-0044 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE —6—