SONY CXG1096FN

CXG1096FN
Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS
Description
The CXG1096FN is an MMIC consisting of the
power amplifier, diversity antenna supported switch
and low noise down conversion mixer.
This IC is designed using the Sony's GaAs J-FET
process featuring a single positive power supply
operation.
Features
• Operates at a single positive power supply: VDD = 3V
• Diversity antenna supported switch
• Small mold package: 26-pin HSOF
26 pin HSOF (Plastic)
Absolute Maximum Ratings
<Power amplifier/antenna switch transmitter block >
• Low current consumption: IDD = 150mA
(POUT = 20.2dBm, f = 1.9GHz)
• High power gain: Gp = 40dB Typ.
(POUT = 20.2dBm, f = 1.9GHz)
<Antenna switch receiver block/
low noise down conversion mixer>
• Low current consumption: IDD = 5.5mA Typ
(When no signal)
• High conversion gain: Gc = 19.5dB Typ
(f = 1.9GHz)
• Low distortion: Input IP3 = –12dBm Typ. (f = 1.9GHz)
• High image compression ratio: IMR = 40dBc Typ.
(f = 1.9GHz)
• High 1/2 IF compression ratio: 1/2IFR = 47dBc Typ.
(f = 1.9GHz)
<Power amplifier block>
• Supply voltage
VDD
• Voltage between gate and source
VGSO
• Drain current
IDD
• Allowable power dissipation
PD
6
V
1.5
550
V
mA
3
W
V
<Switch block>
Control voltage
VCTL
6
<Front-end block>
• Supply voltage
• Input power
VDD
PRF
6
+10
<Common to each block>
• Channel temperature
Tch
• Operating temperature
Topr
• Storage temperature
Tstg
V
dBm
150
–35 to +85
–65 to +150
°C
°C
°C
Applications
Japan digital cordless telephones (PHS)
Structure
GaAs J-FET MMIC
Note on Handling
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99X06-PS
CXG1096FN
Block Diagram and External Circuit
2.2nH
PIN
14
13
15
12
16
11
VGG
100pF
2.2nH
VDD1
1nF
18nH
1nF
18nH
10nF
1.8nH
VDD2
VDD3
(POUT)
1nF
1pF
17
(TX)
10
30pF
30pF
18
VCTL1
9
100pF
19
ANT2
8
30pF
ANT1
7
20
(RX)
30pF
30pF
VCTL2
21
6
22
5
23
4
100pF
(RFIN)
10nH
10pF
3.9nH
6.8nH
13pF
24
3
25
2
100nF
VDD
(IF AMP, MIX)
26
1
82nH
1nF
5pF
IFOUT
Pin Configuration
PIN 14
13 VGG
GND 15
12 CAP
VDD1 16
11 POUT
VDD2 17
10 TX
VDD3 18
9
VCTL1
GND 19
8
ANT2
RX 20
7
ANT1
VCTL2 21
6
GND
RFIN 22
5
GND
CAP 23
4
VDD (RF AMP)
GND 24
3
GND
CAP 25
2
VDD (LO AMP)
IFOUT/VDD (IF AMP, MIX) 26
1
LOIN
–2–
13pF
1nF
18pF
1nF
VDD
(RF AMP)
VDD
(LO AMP)
LOIN
CXG1096FN
Electrical Characteristics
These specifications are when the Sony's recommended evaluation board shown on page 6 is used.
1. Power Amplifier Block + Antenna Switch Transmitter Block
These specifications are common to the ANT1 transmission and ANT2 transmission.
Unless otherwise specified: VDD = 3V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz
When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V
When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V
Item
Measurement conditions
Symbol
(Ta = 25°C)
Min. Typ. Max. Unit
mA
Current consumption
IDD
150
Gate voltage adjustment value
VGG
Output power
POUT
Power gain
GP
Adjacent channel leak power ratio
(600 ± 100kHz)
ACPR600kHz
Measured with the ANT pin
–63
–55
dBc
Adjacent channel leak power ratio
(900 ± 100kHz)
ACPR900kHz
Measured with the ANT pin
–70
–60
dBc
Occupied bandwidth
OBW
Measured with the ANT pin
250
275
kHz
0.04
Measured with the ANT pin
0.6
dBm
20.2
36
V
dB
40
2nd-order harmonic level
—
Measured with the ANT pin
–25
dBc
3rd-order harmonic level
—
Measured with the ANT pin
–25
dBc
2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block
These specifications are common to the ANT1 reception and ANT2 reception.
Unless otherwise specified: VDD = 3V, RF1 = 1.90GHz/–35dBm, LO = 1.66GHz/–15dBm
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
(Ta = 25°C)
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Current consumption
IDD
When no signal
5.5
Conversion gain
GC
When a small signal
Noise figure
NF
Input IP3
IIP3
When a small signal
∗1
–17
–12
dBm
Image suppression ratio
IMR
RF2 = 1.42GHz/–35dBm
25
40
dBc
1/2 IF suppression ratio
1/2IFR
RF2 = 1.78GHz/–35dBm
41
47
dBc
17
7.5
19.5
4.4
mA
dB
5.5
dB
2 × LO–IF suppression ratio
—
RF2 = 3.08GHz/–35dBm
39
45
dBc
2 × LO+IF suppression ratio
—
RF2 = 3.56GHz/–35dBm
34
65
dBc
–50
–40 dBm
LO to ANT leak
PLK
∗1 Conversion from IM3 compression ratio during FR1 = 1.9000GHz/–35dBm and FR2 = 1.9006GHz/–35dBm input.
–3–
CXG1096FN
Example of Representative Characteristics
1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C)
POUT
15
–50
10
–55
ACPR600kHz
5
–60
0
–65
–5
–40
–35
–30
–25
–20
–15
–70
–10
22
POUT – Output power [dBm]
–45
ACPR600kHz – Adjacent channel leak power ratio [dBc]
POUT – Output power [dBm]
20
VDD = var., VGG = const.,
IDD = 150mA (@VDD = 3V, POUT = 20.2dBm),
PIN = –19.7dBm
When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V
When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V
The data shown below is common to ANT1 and ANT2.
–40
23
–45
GP
40
–50
39
–55
ACPR600kHz
38
–60
37
–65
180
200
–70
220
ACPR600kHz – Adjacent channel leak power ratio [dBc]
Gp – Power gain [dB]
41
160
20
–55
19
–60
17
2.0
Gp, ACPR600kHz vs. IDD
140
–50
ACPR600kHz
2.5
3.0
3.5
4.0
VDD – Supply voltage [V]
VDD = 3V, VGG = var., IDD = var., PIN = var.,
POUT = 20.2dBm
When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V
When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V
The data shown below is common to ANT1 and ANT2.
42
–40
120
POUT
21
18
PIN – Input power [dBm]
36
100
–45
IDD – Current consumption [mA]
–4–
4.5
–65
–70
5.0
ACPR600kHz – Adjacent channel leak power ratio [dBc]
POUT, ACPR600kHz vs. VDD
POUT, ACPR600kHz vs. PIN
VDD = 3V, VGG = const.,
IDD = 150mA (@POUT = 20.2dBm),
PIN = var.
When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V
When ANT2 transmission: VCTL1 = 0V, VCTL2 = 3V
The data shown below is common to ANT1 and ANT2.
25
–40
CXG1096FN
2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C)
GC, NF vs. PLO
POUT, PIM3 vs. PIN
VDD = 3V, RF1 = 1.90GHz/small signal,
LO = 1.66GHz
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz,
LO = 1.66GHz/–15dBm
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
The data shown below is common to ANT1 and ANT2.
5.50
22
20
5.00
19
4.75
18
4.50
NF
17
4.25
16
–25
4.00
–20
–15
–10
–5
NF – Noise figure [dB]
GC
0
PLO – Local input [dBm]
Input IP3, PLK vs. PLO
Input IP3 is common to ANT1 and ANT2.
Input IP3 [dBm]
Input IP3
–12
–35
–14
–40
–16
–45
ANT1
–18
–50
–20
–55
PLK – LO to ANT leak level [dBm]
–30
–10
ANT2
–60
–20
–15
–10
0
POUT
–20
–40
PIM3
–60
–80
Input IP3
–100
–50
–40
–30
–20
–10
PIN – RF input power [dBm]
VDD = 3V, RF = 1.90GHz/–35dBm,
LO = 1.66GHz
When ANT1 reception: VCTL1 = 0V, VCTL2 = 3V
When ANT2 reception: VCTL1 = 3V, VCTL2 = 0V
–22
–25
POUT – IF output power,
PIM3 – 3rd-order intermodulation power [dBm]
5.25
21
GC – Conversion gain [dB]
The data shown below is common to ANT1 and ANT2.
20
–5
0
PLO – Local input [dBm]
–5–
0
CXG1096FN
Recommended Evaluation Board
Via Hole
PAIN
ANT2
VGG
VDD_PA
VCTL1
ANT1
VCTL2
VDD_LNA
VDD_LO
IFOUT
LOIN
VDD_IF
Via Hole
Glass fabric-base epoxy board (4 layers)
Thickness between layers 1 and 2: 0.2mm
Dimensions: 50mm × 50mm
Enlarged Diagram of External Circuit Block
C8
C8
L2
C7
L6
C1
L2
C8
C6
L6
C6
C9
C7
L1
C6
C6
C6
C7
L5
L4
C3
C4
C10
C4
L3
C2
C5
C8
L7
C8
–6–
C8
L1 = 1.8nH
L2 = 2.2nH
L3 = 3.9nH
L4 = 6.8nH
L5 = 10nH
L6 = 18nH
L7 = 82nH
C1 = 1pF
C2 = 5pF
C3 = 10pF
C4 = 13pF
C5 = 18pF
C6 = 30pF
C7 = 100pF
C8 = 1nF
C9 = 10nF
C10 = 100nF
CXG1096FN
Package Outline
Unit: mm
HSOF 26PIN(PLASTIC)
0.08
0.45 ± 0.15
0.9 ± 0.1
S
*5.6 ± 0.05
5.5
4.2
A
0.4
0.5
(1.5)
(0.7)
4.4 ± 0.1
(1.75)
14
3.8 ± 0.05
26
13
1
0.4
S
4.4
0.2
0.2
0.07 M S A
(0.2)
0.2 ± 0.05
+ 0.05
0.2 0
Solder Plating
B
+ 0.05
0.14 – 0.03
DETAILB
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.06g
SONY CODE
HSOF-26P-01
–7–
Sony corporation