CXG1127ER High Power 5 × 4 Antenna Switch MMIC with Integrated Control Logic for PDC Dual Phone Description The CXG1127ER is a high power antenna switch MMIC for PDC 800MHz and 1.5GHz dual phone. The CXG1127ER is suited to connect 2Tx/3Rx to one of 4 antennas. The CXG1127ER has on-chip logic circuit for operation with 5 CMOS inputs. The Sony’s GaAs J-FET process is used for low insertion loss and low voltage operation. 24 pin VQFN (Plastic) Features • Low insertion loss: 0.45dB @900MHz, 0.55dB @1.5GHz • High linearity: Harmonic < – 65dBc • CMOS compatible input control • Small package: 24-pin VQFN (4.0mm × 4.0mm) Applications 5 × 4 antenna switch for digital cellular such as PDC handsets Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD • Control voltage • Operating temperature • Storage temperature VDD Topr Tstg 7 5 –35 to +85 –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01743-PS CXG1127ER Block Diagram Tx1 Tx2 F2 F1 Ant4 Ant3 F21 F3 F4 F22 F5 F6 GND4A F8 GND4B GND3 F16 F9 Rx1 Ant2 F17 F10 Rx2 GND2 F12 F11 Rx3 Ant1 F20 F15 GND 1B –2– F14 GND 1A CXG1127ER 12 Z4B CTLD/GND4B 10 CRF (100pF) Tx2 9 GND CRF (100pF) Tx1 11 GND Z4A CRF (100pF) GND4A Ant4 Pin Configuration/Recommended Circuit 8 7 13 Ant3 6 CRF (100pF) Rx1 14 5 15 4 16 3 Z3 GND3 open CTLE GND Cbypass (100pF) Rx2 CRF (100pF) GND Rx3 Ant2 CRF (100pF) 17 2 18 1 24 Z1A GND1A Cbypass (100pF) VDD 23 Z1B 22 CTLA Cbypass (100pF) CTLB CTLC 21 Cbypass (100pF) 20 Cbypass (100pF) 19 When using this IC, the following external components should be used: CRF: This capacitor is used for RF de-coupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. In the case that Rx1 is not used, the processing of the pin is as follows: • Rx1 is recommended to be open. • CTLD/GNG4B should be grounded as a DC. –3– GND2 Ant1 CRF (100pF) GND1B CRF (100pF) Z2 CXG1127ER Truth Table A: Rx/Tx B: main/diversity C: External/antenna D: 800MHz digital/800MHz analog E: 800MHz/1.5GHz State On Pass A B C D E 1 Tx1 – Ant3 H — L — L L H 2 Tx1 – Ant4 H — H — L H 3 Tx2 – Ant3 H — L — H 4 Tx2 – Ant4 H — H — 5 Rx1 – Ant3 L L L 6 Rx2 – Ant3 L L 7 Rx3 – Ant3 L 8 Rx1 – Ant4 9 F1 F2 F3 F4 F5 F6 F8 H L L L L L L L L H L L H H H L L L H L L H L L L L H L L H H L L H L L H L L L L L L L L H L H H L H H L H H L L L H L L L L L H L H H L L H L H L H L L H L H L L L H L L H H H L L L L H L H L L H L L H L L H L L H H H L L L — H H L H L L H L L L H L L H L H L L H L L H H L L H L H H L H H L L L H L L H H L L Rx2 – Ant4 L L H L L L H L H H L H L H L L H L L H H L L 10 Rx3 – Ant4 L L H — H L H L H H L H L L H L L H L H L L L 11 Rx1 – Ant2 L H L H L L L L L L L H H L L L H L H L H H L 12 Rx2 – Ant2 L H L L L L L L L L L H L H L L H L H L H H L 13 Rx3 – Ant2 L H L — H L L L L L L H L L H L L H H L L L H 14 Rx1 – Ant1 L H H H L L L L L L L H H L L H L L L H H H L 15 Rx2 – Ant1 L H H L L L L L L L L H L H L H L L L H H H L 16 Rx3 – Ant1 L H H — H L L L L L L H L L H H L L L H L L H DC Bias Condition Item (Ta = 25°C) Min. Typ. Max. Unit VDD 2.4 3.0 3.3 V Vctl (H) 2.0 3.0 3.3 V Vctl (L) 0 0.4 V –4– F9 F10 F11 F12 F14 F15 F16 F17 F20 F21 F22 CXG1127ER Electrical Characteristics Item Insertion loss (Ta = 25°C) Symbol IL 2fo Harmonics 3fo ±50kHz ACP ±100kHz P1dB P1dB Port Condition Min. Typ. Max. Unit Tx1 – Ant3 ∗1 — 0.45 0.75 dB Tx1 – Ant4 ∗1 — 0.45 0.75 dB Tx2 – Ant3 ∗2 — 0.55 0.85 dB Tx2 – Ant4 ∗2 — 0.55 0.85 dB Rx2 – Ant3 ∗3 — 0.85 1.15 dB Rx2 – Ant4 ∗3 — 0.90 1.20 dB Rx2 – Ant2 ∗3 — 0.65 0.95 dB Rx2 – Ant1 ∗3 — 0.65 0.95 dB Rx3 – Ant3 ∗4 — 1.10 1.40 dB Rx3 – Ant4 ∗4 — 1.15 1.45 dB Rx3 – Ant2 ∗4 — 0.80 1.10 dB Rx3 – Ant1 ∗4 — 0.80 1.10 dB Tx1 – Ant3 ∗5 — –75 –60 dBc Tx1 – Ant4 ∗5 — –75 –60 dBc Tx2 – Ant3 ∗6 — –75 –60 dBc Tx2 – Ant4 ∗6 — –75 –60 dBc Tx1 – Ant3 ∗5 — –70 –60 dBc Tx1 – Ant4 ∗5 — –70 –60 dBc Tx2 – Ant3 ∗6 — –70 –60 dBc Tx2 – Ant4 ∗6 — –70 –60 dBc Tx1 – Ant3 ∗5 — –67 –57 dBc Tx1 – Ant4 ∗5 — –67 –57 dBc Tx2 – Ant3 ∗6 — –67 –57 dBc Tx2 – Ant4 ∗6 — –67 –57 dBc Tx1 – Ant3 ∗5 — –73 –65 dBc Tx1 – Ant4 ∗5 — –73 –65 dBc Tx2 – Ant3 ∗6 — –73 –65 dBc Tx2 – Ant4 ∗6 — –73 –65 dBc Tx1 – Ant3 VDD = 3V 33 34 — dBm Tx1 – Ant4 VDD = 3V 33 34 — dBm Tx2 – Ant3 VDD = 3V 33 34 — dBm Tx2 – Ant4 VDD = 3V 33 34 — dBm — 2 — µs Switching speed TSW Bias current IDD VDD = 3.0V — 0.8 1.2 mA Control current Ictl Vctl (H) = 3V — 30 70 µA –5– CXG1127ER ∗1 ∗2 ∗3 ∗4 ∗5 Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 889MHz to 960MHz Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,439MHz to 1,443MHz Pin = 10dBm, 0/3V control, VDD = 3.0V, 810MHz to 885MHz Pin = 10dBm, 0/3V control, VDD = 3.0V, 1,487MHz to 1,491MHz π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 889MHz to 960MHz, ACP (±50kHz) < – 70dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 75dBc, 3rd harmonics < – 75dBc ∗6 π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,439MHz to 1,443MHz, ACP (±50kHz) < – 70dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 75dBc, 3rd harmonics < – 75dBc ∗ Rx1 is open for all conditions. –6– CXG1127ER Package Outline Unit: mm 24PIN VQFN(PLASTIC) 0.9 ± 0.1 4.0 0.6 ± 0.1 3.6 18 A 19 0.05 S 0.7 C 13 12 B (0 .3 9) PIN 1 INDEX 24 ˚ 45 S 1.0 0.1 S A-B C 5) x4 (0 0.4 .1 6 C 1 0. 6 7 0.2 ± 0.01 0.1 S A-B C 0.03 ± 0.03 (Stand Off) 0.05 M S A-B C 0.225 ± 0.03 x4 Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 TERMINAL SECTION NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.04g VQFN-24P-03 SONY CODE LEAD SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY LEAD TREATMENT Sn-Bi 2.5% LEAD TREATMENT THICKNESS 5-18µm –7– Sony Corporation