CXG1173UR High Power SPDT Switch with Logic Control Description The CXG1173UR can be used in wireless communication systems, for example, CDMA handsets, W-CDMA handsets, 2.4GHz WLAN. The CXG1173UR has on-chip logic for operation with 1 CMOS control inputs. The Sony J-FET process is used for low insertion loss and on-chip logic circuit. 12 pin UQFN (Plastic) Features • Low insertion loss: 0.3dB@900MHz, [email protected] • 1 CMOS compatible control line • Small package size: 12-pin UQFN Applications • Antenna switch for cellular handsets W-CDMA, CDMA • Antenna switch for cellular handsets 2.4GHz WLAN IEEE 802.11b, 802.11g Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD 7 V • Control voltage Vctl 5 V • Operation temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C GaAs MMIC's are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E03Y12-PS CXG1173UR Block Diagram and Recommended Circuit 6 GND RF1 GND CRF 5 4 GND GND 7 3 F1 F2 CRF RF2 RF3 CRF 8 2 F4 F3 GND GND 9 1 VDD 12 CTL 11 GND 10 Cbypass (100pF) Cbypass (100pF) Rctl (1kΩ) When using this IC, the following external components should be used: Rctl: This resistor is used to improve ESD performance. 1kΩ is recommended. CRF: This capacitor is used for RF De-coupling and must be used all application. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL ON State F1 F2 H RF1 – RF2 ON OFF OFF ON L RF1 – RF3 OFF ON OFF F3 ON F4 –2– CXG1173UR DC Bias Condition Item (Ta = 25°C) Min. Typ. Max. Unit Vctl (H) 2.0 3.0 3.6 V Vctl (L) 0 — 0.4 V 2.5 3.0 3.6 V VDD Electrical Characteristics Item (Ta = 25°C) Symbol Insertion loss IL Isolation ISO. VSWR VSWR Switching speed TSW 1dB compression input power P1dB Input IP3 IIP3 ACLR1 ACLR ACLR2 ACLR3 ACLR4 Harmonics Typ. Max. Unit 900MHz 0.30 0.50 dB 1950MHz 0.45 0.65 dB Condition Min. 900MHz 24 30 dB 1950MHz 18 25 dB 50Ω ∗1, ∗2 34 ∗3 55 ±5MHz, ∗1 ±10MHz, ∗1 ±900kHz, ∗2 ±1.98MHz, ∗2 1.2 1.5 — 2 5 µs dBm dBm 63 –60 –50 dBc –65 –55 dBc –60 –50 dBc –65 –55 dBc 2fo ∗1 –75 –55 dBc 3fo ∗1 –75 –60 dBc 2fo ∗2 –75 –55 dBc 3fo ∗2 –75 –60 dBc Bias current IDD VDD = 3.0V 65 100 µA Control current Ictl Vctl (H) = 3.0V 15 30 µA ∗1 Pin = 25dBm, 0/3.0V control, VDD = 3.0V, 1920 to 1980MHz ∗2 Pin = 25dBm, 0/3.0V control, VDD = 3.0V, 900MHz ∗3 Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/3.0V control, VDD = 3.0V –3– CXG1173UR Pin Description Pin No. Symbol Description 2 RF3 RF input/output. Connect capacitor (recommended value: 100pF) in use 5 RF1 RF input/output. Connect capacitor (recommended value: 100pF) in use 8 RF2 RF input/output. Connect capacitor (recommended value: 100pF) in use 10 VDD DC power supply 12 CTL Logic control 1, 3, 4, 6, GND 7, 9, 11 GND –4– CXG1173UR Package Outline Unit: mm 12PIN UQFN㧔PLASTIC㧕 x4 0.1 2.0 S C 0.4 ± 0.1 0.55 ± 0.05 غ0.6 9 A-B 4-R0.2 C 7 6 12 4 B 2.0 10 A 1 0.14 3 0.4 0.18 PIN 1 INDEX 0.07 0.25 0.05 M S C A-B S 0.05 Solder Plating + 0.09 0.25 – 0.03 + 0.09 0.14 – 0.03 MAX0.02 S S TERMINAL SECTION PACKAGE STRUCTURE Note:Cutting burr of lead are 0.05mm MAX. PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.01g UQFN-12P-01 SONY CODE LEAD PLATING SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm –5– Sony Corporation