TI SN74LVC821ADB

SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
D
D
D
D
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
DB, DW, OR PW PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
description
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC821A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
1
EN
13
C2
2
23
2D
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
CLK
1
13
C1
1D
2
1D
To Nine Other Channels
2
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23
1Q
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
IOL
∆t/∆v
Low-level input voltage
MIN
MAX
1.65
3.6
1.5
Output voltage
High level output current
High-level
Low level output current
Low-level
V
0.65 × VCC
V
1.7
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Input voltage
UNIT
0.7
V
0.8
0
5.5
V
High or low state
0
3 state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
–4
VCC = 2.7 V
VCC = 3 V
–12
–8
–24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
Input transition rise or fall rate
mA
8
mA
24
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
VOH
12 mA
IOH = –12
IOH = –24 mA
IOL = 100 µA
MIN
1.65 V
VCC–0.2
1.2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
TYP†
MAX
UNIT
V
1.65 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
II
Ioff
VI = 0 to 5.5 V
VI or VO = 5.5 V
3.6 V
±5
µA
0
±10
µA
IOZ
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V‡
3.6 V
± 10
µA
VOL
ICC
∆ICC
Ci
IO = 0
One input at VCC – 0.6 V,
Control inputs
Data inputs
10
36V
3.6
Other inputs at VCC or GND
10
2.7 V to 3.6 V
VI = VCC or GND
500
5
33V
3.3
Co
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This applies in the disabled state only.
µA
µA
pF
4
3.3 V
V
7
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
§
MIN
§
MAX
VCC = 3.3 V
± 0.3 V
MIN
Clock frequency
Pulse duration, CLK high or low
§
§
3.3
3.3
ns
tsu
th
Setup time, data before CLK
§
§
1.9
1.9
ns
Hold time, data after CLK
§
§
1.5
1.5
ns
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150
UNIT
MAX
fclock
tw
§ This information was not available at the time of publication.
4
MAX
VCC = 2.7 V
150
MHz
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
†
MAX
MIN
†
MAX
†
†
†
VCC = 2.7 V
MIN
MAX
MIN
UNIT
MAX
fmax
tpd
CLK
Q
†
8.5
2.2
7.3
ns
ten
OE
Q
†
†
†
†
8.8
1.3
7.6
ns
Q
†
†
†
†
6.8
1.6
6.2
ns
1
ns
tdis
OE
150
VCC = 3.3 V
± 0.3 V
150
MHz
tsk(o)‡
† This information was not available at the time of publication.
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per flip-flop
Outputs enabled
Outputs disabled
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
†
TYP
†
TYP
†
†
48
f = 10 MHz
UNIT
65
pF
† This information was not available at the time of publication.
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SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1k Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1k Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
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SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
1.5 V
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
1.5 V
2.7 V
Output
Control
(low-level
enabling)
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
8
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Copyright  1998, Texas Instruments Incorporated