CXK5V16100TM -85LLX/10LLX 65536-word × 16-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Description CXK5V16100TM is a general purpose high speed CMOS static RAM organized as 65536-words by 16-bits. Operating on a single 3.3V supply, this asynchronous IC is suitable for high speed and low power consumption applications where battery back up for nonvolatility is required. 44 pin TSOP (PIastic) Features • Extended operating temperature range: –25 to +85°C • Fast access time: (Access time) -85LLX 85ns (max.) -10LLX 100ns (max.) • Low power consumption operation: Standby / DC operation 1.7µW (typ.) / 3.3mW (typ.) • Single 3.3V supply: 3.3V±0.3V • Fully static memory: No clock or timing strobe required • Equal access and cycle time • Common data input and output: three state output • Directly LVTTL compatible: All inputs and outputs • Low voltage data retention: 2.0V (min.) • 400mil 44pin TSOP (type II) package Function 65536-word × 16-bit static RAM Structure Silicon gate CMOS IC Block Diagram A1 A0 A7 A6 A5 Buffer A4 Vcc A3 A2 GND A15 A14 CE UB LB OE WE Vcc Memory Matrix 512 × 1024 Row Decoder I/O Gate Column Decoder Pre Decoder Memory Matrix 512 × 1024 GND Control I/O Gate Column Decoder A13 A12 A11 A10 Buffer A9 A8 I/O Buffer I/O1 I/O8 I/O Buffer I/O9 I/O16 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93869A57-PP CXK5V16100TM Pin Configuration (Top View) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 UB CE 6 39 LB Pin Description I/O1 7 38 I/O16 I/O2 8 37 I/O15 I/O3 9 36 I/O14 I/O4 10 35 I/O13 Vcc 11 34 GND 33 Vcc GND 12 Description Symbol A0 to A15 Address input I/O1 to I/O16 Data input/output CE Chip enable input LB Byte enable input (I/O1 to I/O8) UB Byte enable input (I/O9 to I/O16) WE Write enable input I/O5 13 32 I/O12 I/O6 14 31 I/O11 OE Output enable input I/O7 15 30 I/O10 29 I/O9 VCC +3.3V power supply 28 NC 27 A8 GND Ground 26 A9 NC No connection I/O8 16 WE 17 A15 18 A14 19 A13 20 A12 21 25 A10 NC 22 23 NC 24 A11 Absolute Maximum Ratings Item (Ta = 25°C, GND = 0V) Symbol Rating Unit V Supply voltage VCC Input voltage VIN –0.5 to +4.6 –0.5∗ to VCC + 0.5 Input and output voltage VI/O –0.5∗ to VCC + 0.5 V Allowable power dissipation PD 0.7 W Operating temperature Topr –25 to +85 °C Storage temperature Tstg –55 to +150 °C Soldering temperature • time Tsolder 235 • 10 °C • s V ∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE OE WE LB UB H × × × × Not selected Not selected ISB1, ISB2 L L Read Read ICC1, ICC2, ICC3 L H Read High-Z ICC1, ICC2, ICC3 H L High-Z Read ICC1, ICC2, ICC3 L L Write Write ICC1, ICC2, ICC3 L H Write Not Write/Hi-Z ICC1, ICC2, ICC3 H L Not Write/Hi-Z Write ICC1, ICC2, ICC3 L L L × H L I/O1 to I/O8 I/O9 to I/O16 Vcc Current L H H × × High-Z High-Z ICC1, ICC2, ICC3 L × × H H High-Z High-Z ICC1, ICC2, ICC3 ×: “H” or “L” –2– CXK5V16100TM DC Recommended Operating Conditions Item (Ta = –25 to +85°C, GND = 0V) Symbol Min. Typ. Max. Unit Supply voltage VCC 3.0 3.3 3.6 V Input high voltage VIH 2.0 — VCC + 0.3 V Input low voltage VIL –0.3∗ — 0.8 V ∗ VIL = –3.0V Min. for pulse width less than 50ns. Electrical Characteristics DC and operating characteristics Item Symbol (VCC = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C) Test condition Min. Typ.∗ Max. Unit Input leakage current ILI VIN = GND to VCC –1 — 1 µA Output leakage current ILO CE = VIH or UB = VIH or LB = VIH or OE = VIH or WE = VIL VI/O = GND to VCC –1 — 1 µA Operating power supply current ICC1 CE = VIL VIN = VIH or VIL IOUT = 0mA — 1 3 mA ICC2 Min. cycle Duty = 100% IOUT = 0mA 85LLX — 40 55 10LLX — 35 50 — 10 20 –25 to +85°C — — 40 –25 to +70°C — — 20 –25 to +40°C — — 4 +25°C — 0.5 2 Average operating current ICC3 Standby current ISB1 Cycle time 1µs Duty = 100% IOUT = 0mA CE ≤ 0.2V VIL ≤ 0.2V VIH ≥ VCC – 0.2V CE ≥ VCC – 0.2V mA mA µA ISB2 CE = VIH — 0.03 0.6 mA Output high voltage VOH IOH = –2.0mA 2.4 — — V Output low voltage VOL IOL = 2.0mA — — 0.4 V ∗ VCC = 3.3V, Ta = 25°C –3– CXK5V16100TM I/O capacitance Item (Ta = 25°C, f = 1MHz) Symbol Test conditions Min. Typ. Max. Unit Input capacitance CIN VIN = 0V — — 8 pF I/O capacitance CI/O VI/O = 0V — — 10 pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions (VCC = 3.3V ± 0.3V, Ta = –25 to +85°C) Item Conditions Input pulse high level VIH = 2.2V Input pulse low level VIL = 0.6V Input rise time tr = 5ns tf = 5ns Input fall time Input and output reference level Output load conditions TTL CL 85ns 1.4V CL∗ = 30pF, 1TTL 100ns CL∗ = 100pF, 1TTL ∗ CL includes scope and jig capacitances. –4– CXK5V16100TM • Read cycle (WE = “H”) -85LLX Item Symbol Chip disable to output in high Z (OE) tRC tAA tCO tBO tOE tOH tLZ tOLZ tBLZ tHZ∗ tOHZ∗ Byte disable to output in high Z (UB, LB) tBHZ∗ Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE) Ouput enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in high Z (CE) ∗ -10LLX Unit Min. Max. Min. Max. 85 — 100 — ns — 85 — 100 ns — 85 — 100 ns — 40 — 50 ns — 40 — 50 ns 10 — 10 — ns 10 — 10 — ns 5 — 5 — ns 5 — 5 — ns — 35 — 40 ns — 30 — 35 ns — 30 — 35 ns tHZ, tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle -85LLX Item Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE, UB, LB) Output active from end of write Write to output in high Z ∗ Symbol tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ -10LLX Unit Min. Max. Min. Max. 85 — 100 — ns 70 — 80 — ns 70 — 80 — ns 70 — 80 — ns 35 — 40 — ns 0 — 0 — ns 60 — 70 — ns 0 — 0 — ns 5 — 5 — ns 5 — 5 — ns 5 — 5 — ns — 35 — 40 ns tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage levels. –5– CXK5V16100TM Timing Waveform • Read cycle (1) : CE = OE = VIL, WE = VIH, UB and, or LB = VIL tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE tCO tHZ tLZ tBO UB, LB tBLZ tBHZ OE tOE tOHZ tOLZ Data out Data valid High impedance –6– CXK5V16100TM • Write cycle (1) : WE control tWC Address tWR tAW OE tCW CE tBW UB, LB tAS tWP (∗1) WE tDW tDH Data valid Data in tWHZ tOW Data out High impedance (∗2) (∗2) • Write cycle (2) : CE control tWC Address tAW OE tAS tWR1 tCW CE tBW UB, LB tWP WE tDH tDW Data valid Data in Data out High impedance –7– (∗ 3) CXK5V16100TM • Write cycle (3) : UB, LB control tWC Address tAW OE tCW CE tAS tWR1 (∗3) tBW UB, LB tWP WE tDH tDW Data valid Data in Data out High impedance ∗1 Write is executed when all of the CE, WE and (UB and, or LB) are at low simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 (for I/O1 to 8) is tested from either the rising edge of CE or LB, whichever comes earlier, until the end of the write cycle. tWR1 (for I/O9 to 16) is tested from either the rising edge of CE or UB, whichever comes earlier, until the end of the write cycle. –8– CXK5V16100TM Data Retention Waveform • Low supply voltage data retention waveform tCDRS tR Data retention mode VCC 3.0V 2.0V VDR CE CE ≥ VCC – 0.2V GND Data Retention Characteristics Item Symbol Data retention voltage VDR ICCDR1 Data retention current (Ta = –25 to +85°C) Test condition Min. Typ. Max. Unit 2.0 — 3.6 V –25 to +85°C — — 24 –25 to +70°C — — 12 –25 to +40°C — — 2.4 +25°C — 1.2 40 µA CE ≥ VCC – 0.2V VCC = 3.0V µA ICCDR2 VCC = 2.0 to 3.6V — 0.4 0.5∗ Data retention setup time tCDRS Chip disable to data retention mode 0 — — ns Recovery time tR 5 — — ms ∗ VCC = 3.3V, Ta = 25°C –9– CXK5V16100TM Package Outline Unit: mm 44PIN TSOP (II) (PLASTIC) 400mil 1.2 MAX ∗18.41 ± 0.1 0.1 1 11.76 ± 0.2 23 ∗10.16 ± 0.1 44 A 22 0.8 0.3 ± 0.1 0.13 M + 0.05 0.125 – 0.02 B (0.3) 0.145 ± 0.055 (0.125) 0.32 ± 0.08 0.5 ± 0.1 + 0.1 0.1 – 0.05 0° to 10° DETAIL A DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE SONY CODE TSOP (II) -44P-L01 EIAJ CODE TSOP (II) 044-P-0400-A JEDEC CODE MOLDING COMPOUND EPOXY / PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.5g – 10 –