CXK77B3610GB -6/7 High Speed Bi-CMOS Synchronous Static RAM Preliminary For the availability of this product, please contact the sales office. Description The CXK77B3610GB-6/7 is a high speed 1M bit Bi-CMOS synchronous statis RAM organized as 32768 words by 36 bits. This SRAM integrates input registers, high speed SRAM and write buffer onto a single monolithic IC and features the delayed write system to reduce the dead cycles. 119 pin BGA (Plastic) Features • Fast cycle time (Cycle) (Frequency) CXK77B3610GB-6 6ns 166MHz CXK77B3610GB-7 7ns 142MHz • Inputs and outputs are LVTTL/LVCMOS compatible • Single 3.3V power supply: 3.3V ± 0.15V • Byte-write possible • OE asynchronization • JTAG test circuit • Package 119TBGA • 3 kinds of synchronous operation mode Register-Register mode (R-R mode) Register-Flow Thru mode (R-F mode) Register-Latch mode (R-L mode) Function 32768 word × 36bit High Speed Bi-CMOS Synchronous SRAM Structure Silicon gate Bi-CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE95128-PS CXK77B3610GB Block Diagram 15 Input Reg. A0 to 14 2:1 Mux Add. Dout 2:1 Mux 32K × 36 Write Store Reg. Output latch Din Write pulse Reg. Read Comp. S Reg. W Reg. Salf Time Write Logic 4 BW a to d Reg. Output Clock K/K M1 M2 Mode Control G –2– DQ CXK77B3610GB Pin Configuration (Top View) 1 2 3 4 5 6 7 A VDDQ A A NC A A VDDQ B NC NC NC NC NC NC NC C NC A A VDD A A NC D DQc DQc VSS NC VSS DQb DQb E DQc DQc VSS S VSS DQb DQb F VDDQ DQc VSS G VSS DQb VDDQ G DQc DQc BWc NC BWb DQb DQb H DQc DQc VSS NC VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS K VSS DQa DQa L DQd DQd BWd K BWa DQa DQa M VDDQ DQd VSS W VSS DQa VDDQ N DQd DQd VSS A VSS DQa DQa P DQd DQd VSS A VSS DQa DQa R NC A M1 VDD M2 A NC T NC NC A A A NC ZZ U VDDQ TME TDI TCK TDO NC VDDQ Pin Description Symbol Description Symbol Description Symbol Description A Address Input G Asyn Output Enable VDDQ Output power supply DQx Data I/O in byte a to d ZZ Sleep Mode Select VSS Ground K Positive Clock TCK JTAG Clock M1, M2 Mode Select K Negative Clock TMS JTAG Mode Select NC No Connect W Write Enable TDI JTAG Data In BWx Byte Write Enable (a to d) TDO JTAG Data Out S Chip Select VDD +3.3V power supply –3– CXK77B3610GB Absolute Maximum Ratings Item (Ta = 25°C, GND = 0V) Symbol Rating Unit Supply voltage VCC –0.5 to +4.6 V Input voltage VIN –0.5 to VCC +0.5 (4.6V max.) V Output voltage VO –0.5 to VCC +0.5 (4.6V max.) V Allowable power dissipation PD TBD W operating temperature Topr 0 to 70 °C Strorage temperature Tstg –55 to +150 °C Soldering temperature · time Tsolder 235 · 10 °C · sec Truth Table W (tn) BWx (tn) G DQ0 to 35 DQ0 to 35 VDD (tn) (tn+1) Current ZZ S (tn) Mode H X X X X Sleep mode, Power down L H X X X Deselect L L H X H L L H X L L L L L L L Hi-Z Hi-Z ISB X Hi-Z ICC Read Hi-Z Hi-Z ICC L Read X Q (tn) ICC L X Write all bytes (bits 0 to 35) X D (tn) ICC L X X Write bytes with BWx = L X D (tn) ICC L H X Aborted Write X X ICC DC Recommended Operating Conditions Item Symbol (Ta = 25°C, GND = 0V) Min. Typ. Max. Unit Supply voltage VDD 3.15 3.3 3.45 V Output supply voltage VDDQ 3.15 3.3 3.45 V Input high voltage VIH 2.0 — VDD +0.3 V Input low voltage VIL –0.3 — 0.8 V Differential clock input signal ∆VK 0.4 0.8 — V Differential clock input common mode VK, COM 1.2 2.0 2.2 V –4– CXK77B3610GB Mode Select Truth Table M1 M2 Register-Resister mode L H Register-Flow Thru mode L L Register-Latch mode H L Item Electrical Characteristics • DC and operating characteristics Item Symbol (VCC = 3.3V ± 10%, GND = 0V, Ta = 0 to 70°C) Test conditions Min. Typ.∗ Max. Unit Input leakage current ILI VIN = GND to VCC –1 — 1 µA Output leakage current ILO VO = GND to VCC G = VIH –10 — 10 µA Operating power supply current ICC Cycle = min. Duty = 100% IOUT = 0mA — — TBD mA Standby current ISB ZZ ≥ VIH 20 mA Output high voltage VOH IOH = –2.0mA 2.4 — — V Output low voltage VOL IOL = 2.0mA — — 0.4 V ∗ VCC = 3.3V, Ta = 25°C • I/O capacitance Item (Ta = 25°C, f = 1MHz) Symbol Test conditions Min. Max. Unit Input capacitance CIN VIN = 0V — 5 pF Clock input capacitance CCLK VIN = 0V — 8 pF Output capacitance COUT VOUT = 0V — 8 pF Note) These parameters are sampled and are not 100% tested. –5– CXK77B3610GB • AC Electrical Characteristics Item Symbol Address access (except Register-Register mode) -6 -7 Unit Min. Max. Min. Max. — 9 — 10 ns 6 — 7 — ns 2 — 3 — ns 2 — 3 — ns 0.5 — 1 — ns 1 1.5∗2 — 1 1.5∗2 — ns 3.5 ns — 1.5∗2 6 7 ns 3.5 ns 17 ns Clock low to output (R-L mode) tAA tKP tKH tKL tS tH tKQ tKQ1 tKQ2 Write cycle clock high to following Read cycle output (R-F mode, R-L mode) tKQ3 Clock high to output high impedance (S deselect cycle) tHZ∗2 1.5 3 1.5 3.5 ns Write cycle clock high to output high impedance (R-F mode, R-L mode) tWHZ∗2 1.5 3 1.5 3.5 ns Clock high to output low impedance (R-R mode) tLZ∗2 1.5 — 1.5 — ns Clock high to output low impedance (R-F mode) tLZ1∗2 2 — 2 — ns Clock low to output low impedance (R-L mode) tLZ2∗2 tOE tOLZ∗2 tOHZ∗2 1.5 — 1.5 — ns — 3 — 3.5 ns 1 — 1 — ns — 3 — 3.5 ns Clock period Clock pulse high Clock pulse low Setup time Hold time Clock high to output (R-R mode) Clock high to output (R-F mode, R-L mode) Output enable to output valid (G) Output enable to output in low Z (G) Output disable to output in high Z (G) 3 3 — 1.5∗2 15 ∗1 All parameters are specified over the range 0 to 70°C. ∗2 These parameters are sampled and are not 100% tested. AC characteristics • AC test conditions (VDD = 3.3V ± 0.15V, Ta = 0 to 70°C) Item Input pulse high level VIH = 2.4V Input pulse low level VIL = 0.4V Input rise & fall time 1V/ns Input reference level 2.0/0.8V Clock input reference level K/K cross; C/C cross Clock input differential signal 0.8V Clock input rise & fall time 1V/ns Output reference level 1.4V Output load conditions Fig. 1 Output Load (2) ∗2 Output Load (1) Conditions 3.3V I/O 50Ω 50Ω I/O 5pF∗1 1.4V ∗1 Including scope and jig capacitance. ∗2 For tLZ, tHZ. Fig. 1. –6– 1178Ω 868Ω CXK77B3610GB Register-Register mode Timing waveform of READ CYCLE K K tKH tKL tKP tS A0 to 14 tH n n+1 n+2 W tS tH tS tH S tKQ tKQ tOE G tOHZ tLZ tOLZ tHZ Qn – 2 DQ0 to 35 Qn – 1 Qn Timing waveform of WRITE CYCLE K K tH tS A0 to 14 n n+1 Dn – 1 Dn n+2 S W/BWx G DQ0 to 35 –7– Dn + 1 CXK77B3610GB Register-Register mode Timing waveform of READ-WRITE-READ CYCLE I (S controlled) K K A0 to 14 N N+2 N+3 N+4 N+5 S W/BWx G = VIL Qn – 1 DQ0 to 35 Reed N Dn + 2 Qn Deselect (Hi-Z) Write N + 2 Qn + 3 Reed N + 3 Timing waveform of READ-WRITE-READ CYCLE II (G controlled) K K A0 to 14 N N+2 N+3 N+4 N+5 S = VIL W/BWx G DQ0 to 35 Qn – 1 Reed N Qn Dn + 2 Hi-Z; Write N + 2 –8– Reed N + 3 Qn + 3 CXK77B3610GB Register-Latch mode Timing waveform of READ CYCLE K K tKH tKP tKL tS A0 to 14 tH n n+1 n+2 W tS tH tS tH tS tH S tKQ1 tKQ2 tKQ2 tKQ1 tAA tOE G tLZ2 tOHZ Qn – 1 DQ0 to 35 Qn tOLZ tHZ Qn + 1 Timing waveform of WRITE CYCLE K tKP K tH tS A0 to 14 n n+1 n+2 S W/BWx G DQ0 to 35 Dn – 1 Dn –9– Dn + 1 CXK77B3610GB Register-Latch mode Timing waveform of READ-WRITE-READ CYCLE K K tKP A0 to 14 S tKP N tS N+1 tKP N+2 N+3 N+4 N+5 tH tS W/BWx tKP tS tH tH tKQ2 tKQ1 tKQ2 tAA tWHZ tKQ1 tS tH tKQ2 G = VIL tLZ2 Qn DQ0 to 35 Dn + 1 Qn + 2 tLZ1 tKQ3 Reed N Write N + 1 Qn + 4 Reed N + 2 – 10 – Deselect (Hi-Z) Reed N + 4 CXK77B3610GB Register-Flow Thru mode Timing waveform of READ CYCLE K K tKH tKP tKL tS A0 to 14 tH n n+1 n+2 W tS tH tS tH tS tH S tKQ1 tKQ1 tOE tAA G tOHZ tLZ1 Qn – 1 DQ0 to 35 Qn tOLZ tHZ Qn + 1 Timing waveform of WRITE CYCLE K K tH tS A0 to 14 n n+1 Dn – 1 Dn n+2 S W/BWx G DQ0 to 35 – 11 – Dn + 1 CXK77B3610GB Register-Flow Thru mode Timing waveform of READ-WRITE-READ CYCLE K K N A0 to 14 S tS N+1 N+2 N+3 N+4 N+5 tH tS tH tS tH W/BWx tKQ1 tAA tWHZ tKO1 tS tKQ1 tH G = VIL Qn DQ0 to 35 Dn + 1 Qn + 2 tLZ1 tKQ3 Reed N Write N + 1 Qn + 4 Reed N + 2 – 12 – Deselect (Hi-Z) Reed N + 4 CXK77B3610GB Test Mode Description Fuctional Description The CXK77B3610 provides JTAG boundary scan interface using IEEE std. 1149.1 protocol. The test mode is intended to provided a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs other components and print circuit board. In conformance with IEEE std. 1149.1, the CXK77B3610 contains a TAP controller, Instruction register, Boundary scan register and Bypass register. Test Access Port (TAP) 4 pins as defined in Pin Description table are used to perform JTAG functions. TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary scan register and Bypass register). TDO is output pin used to scan test data serially out. The TDI send the data into LSB of selected register and the MSB of the selected register feeds the data to TDO. TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI, TMS are registered on the rising edge of TCK clock and the output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP conroller is in Shift-IR state or in Shift-DR state. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enter reset state in one of three ways: 1. Power up 2. Apply logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Resister (3 bits) The JTAG Instruction resister is consisted of shift resister stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal MSB LSB Instruction 0 0 0 0 Bypass 1 0 0 1 IDCODE. read device ID 2 0 1 0 Sample-Z. Sample Inputs and tri-state DQs 3 0 1 1 Bypass 4 1 0 0 Sample. Sample Inputs. 5 1 0 1 Private. Manufacturer use only. 6 1 1 0 Bypass 7 1 1 1 Bypass Bypass Register (1 bit) The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO. – 13 – CXK77B3610GB ID Registers (32 bits) The ID Register are 32 bits wide and are listed as follow: ID [0] 1 Sony ID ID [11:1] 0000 1110 001 Part Number ID [27:12] Revision Number ID [31:28] 0000 0000 0000 0000 xxxx∗1 ∗1 Please contact Sony Sales Department. Boundary Scan Register (70 bits) The Boundary Scan Registers are 70 bits wide and are listed as follow: DQ 36 A 15 W, BWx 5 S, G 2 K, K, C, C 4 ZZ 1 Mode 2 Place Holder 5 K/K, C/C inputs are sampled through one differential stage and internal inverted to generate internal K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 70 bits Scan Register for different types of same family SRAM and for density upgrade. All Place Holder Registers are connected to VSS internally regardless of pin connection externally. – 14 – CXK77B3610GB Scan Order (Order by exit sequence) 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 — — 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G — 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R VSS VSS A A A A DQc DQc DQc DQc DQc DQc DQc DQc DQc /Wc VSS /S /C C /W /Wd DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A M1 VSS VSS A A A A DQb DQb DQb DQb DQb DQb DQb DQb DQb /Wb /G K /K /Wa DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ A A A A M2 – 15 – — — 5A 5C 6C 6A 6D 7D 6E 7E 6F 6G 7G 6H 7H 5G 4F 4K 4L 5L 7K 6K 7L 6L 6M 7N 6N 7P 6P 7T 5T 6R 4T 4P 5R 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CXK77B3610GB Package Outline Unit: mm 119 TERMINAL BGA (PLASTIC) X 0.84 C 46 0. C 19.5 22.0 1. 0 ×4 0.35 C 1 2 3 4 5 6 7 3- 5 1. 0.10 1.27 U T R P N M L K J H G F E D C B A C C 3.19 20.32 B 11.5 7.62 0.6 ± 0.1 A 1.27 14.0 0.6 ± 0.1 φ0.75 ± 0.15 1.5 φ0.3 C A B φ0.1 0.15 DETAIL X C PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN BOARD MATERIAL COPPER-CLAD LAMINATE EIAJ CODE TERMINAL MATERIAL SOLDER JEDEC CODE PACKAGE WEIGHT 0.8g SONY CODE BGA-119P-01 – 16 –