CXL1512M CCD Delay Line for NTSC For the availability of this product, please contact the sales office. Description The CXL1512M is an IC developed for use in conjunction with Y/C signal processing ICs for NTSC. This CCD delay line provides the comb filter output for eliminating the chrominance signal cross talk and 1H delay output for luminance signals. 24 pin SOP (Plastic) Features • Single power supply (5V) • Built-in quadruple progression PLL circuit • Built-in comb filter • 1H delay output • Built-in peripheral circuits • Positive phase signal input, positive phase signal output Functions • Comb filter output • 1H delay output for luminance signal • Clock driver • Autobias circuit • Input clamp circuit (for luminance signals) • Center bias circuit (for chrominance signals) • Sample-and-hold circuit • Quadruple progression PLL circuit • Clock buffer output circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD +6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Voltage (Ta = 25°C) VDD 5V ± 5% Structure CMOS-CCD Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94803-ST CXL1512M Recommended Clock Conditions (Ta = 25*C) • Input clock amplitude VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.) • Clock frequency fCLK 3.579545MHz • Input clock waveform sine wave Input Signal Amplitude Vsig 350mVp-p (Typ.), 575mVp-p (Max.) Vss C-OUT (IC) AB-C fsc AB-P (NC) (NC) (NC) PCOUT VCOIN Vss Block Diagram and Pin Configuration (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 PLL fsc buffer Timing D Output circuit (S/H) Autobias circuit (C) 1H + D Driver φ1 φ2 Autobias circuit (Y) –2– C-IN2 (NC) (IC) 7 8 9 10 11 12 CLK 6 (NC) 5 (NC) 4 Y-OUT 3 (NC) 2 Output circuit (S/H) 1H Y-IN 1 VDD Clamp circuit C-IN1 Bias circuit Vss Bias circuit Driver CXL1512M SOP 24pin Pin No. Symbol Description I/O 1 VSS 2 C-IN1 3 VDD 4 C-IN2 I Chrominance signal input 2 5 (NC) — — 6∗ (IC) — (Connected internally) 7 Y-IN I Luminance signal input 8 (NC) — 9 Y-OUT O 10 (NC) — — 11 (NC) — — 12 CLK I 13 VSS — 14 VCOIN I VCO input 15 PCOUT O Phase comparator output 16 (NC) — — 17 (NC) — — 18 (NC) — — 19 AB-P O Autobias output (P) 20 fsc O fsc buffer output 21 AB-C O Autobias output (C) 22 ∗ (IC) I (Connected internally) 23 C-OUT O Chrominance signal output 24 VSS — GND — I — GND Chrominance signal input 1 Power supply — Luminance signal output Clock input GND ∗ Pins 6 and 22 are internally connected. Therefore, connect a voltage of 5V when using these pins. –3– CXL1512M Description of Functions The CXL1512M provides chrominance signal comb filters and luminance signal delay outputs. Number of CCD bits Chrominance comb filter output 1H (910bit) Luminance signal delay output 1H (908bit) • fsc Output Pin The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a 2.2kΩ pull-down resistor when the fsc output is to be used. <When in use> <When not in use> fsc fsc 2.2k –4– VDD CXL1512M Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave) See Electrical Characteristics Measurement Circuit Item Supply current Symbol IDD Measurement condition 1 — b SW condition 2 3 4 5 6 b b a — — Min. Typ. Max. Unit Note 35 50 mA 1 Min. Typ. Max. Unit Note Chrominance signal Characteristics (No signals input to Y-IN) Symbol SW condition Measurement condition 1 2 3 4 5 6 Low frequency gain GLC (See Note 2) a a b — a b –2 0 2 dB 2 Frequency response FC (See Note 3) a a b — a b –2.0 –1.0 0 dB 3 Linearity LIC (See Note 4) a a b — a b –0.3 0 0.3 dB 4 Comb depth min. gain CCD (See Note 5) a a b — a b –40 –25 dB 5 SN ratio SNC 50% white video signal a a b — a d dB 6 Coupling level CPC (See Note 7) b b b — a b Delay time DC (See Note 8) a b b — a a Item 52 56 10 50 mVrms 7 230 — ns 8 Min. Typ. Max. Unit Note — <Luminance Signal Characteristics> (No signals input to C-IN1, C-IN2) Symbol SW condition Measurement condition 1 2 3 4 5 Low frequency gain GLY (See Note 2) b b a b b b –2 0 2 dB 2 Frequency response FY (See Note 3) b b a b b b –2.0 –1.0 0 dB 3 Differential gain DGY 5-step b staircase wave b a a b c 0 3 5 % 9 Differential phase DPY 5-step b staircase wave b a a b c 0 3 5 deg 9 Linearity LNY (See Note 10) b b a a b a 35 40 43 % 10 SN ratio SNY 50% white video signal b b a b b d 52 56 dB 6 Coupling level CPY (See Note 7) b b b b b b mVrms 7 Item –5– 6 10 50 CXL1512M Note 1. This is the IC's supply current value when no signals are input. 2. This is the C-OUT and Y-OUT pin output gain when 500 mVp-p sine waves are input to C-IN1, C-IN2 and Y-IN. (Example of calculation) GLC = 20 log C-OUT pin output voltage (mVp-p) [dB] 500 (mVp-p) Input signal frequency GLC : 204.545kHz GLY : 200kHz 3. This indicates the difference in the C-OUT and Y-OUT pin output gain when 200mVp-p low- and highfrequency sine waves are input to C-IN1, C-IN2 and Y-IN. Set the input bias (Vbias) to 2.0V when measuring the luminance signal characteristics (GLY, GHY). (Example of calculation) FC = 20 log C-OUT pin output voltage (high frequency) (mVp-p) [dB] C-OUT pin output voltage (low frequency) (mVp-p) Input signal frequency (low frequency) → see Note 2 Input signal frequency (high frequency) Chrominance signal : 3.571678MHz Luminance signal : 3.58MHz 4. Calculate with the gain applying when 200mVp-p and 500mVp-p sine waves (see Note 2 for the frequencies) are input to C-IN1 and C-IN2. (Example of calculation) LIC = 20 log Output voltage with 500mVp-p input (mVp-p) 500mVp-p Output voltage with 200mVp-p input (mVp-p) 200mVp-p –6– [dB] CXL1512M 5. Measure the difference of the C-OUT output gain when 500mVp-p sine waves have been input to C-IN1 and C-IN2 at the following frequencies shown below. Input signal frequency CCD fp 3.571678MHz fN 3.563811MHz The frequency response for the outputs at fp and fN are shown in the figure below. Gain fN fp Frequency 6. Using the BPF 100kHz to 4MHz in the Sub Carrier Trap mode, measure the SN ratio on the video noise meter when the 50 % white video signal shown in the figure below is input. 178mV 321mV 143mV 7. Measure the internal clock component (4fsc: 14.31818MHz component) when no signals are input. 8. Measure the delay time of the C-OUT output when the C-IN1 signal is input. –7– CXL1512M 9. On the vector scope, measure the differential gain and differential phase when the 5-step staircase wave shown in the figure below is input. 143mV 357mV 500mV 143mV 10. Input the 5-step staircase wave only for the luminance signal shown in the figure below, and measure the Y-OUT luminance level (Y) and SYNC level (S). (Example of calculation) Y LNY = 357mV 500mV S 143mV –8– S (mV) × 100 Y (mV) Signal generator –9– 0.01µ 0.01µ b 0.1µ a SW3 b a SW2 b a SW1 1 24 2 3.3µ 23 Electrical Characteristics Measurement Circuit 4 21 A 5V 1000P 3 22 5 20 0.1µ 6 19 1M a 7 Vbias 1k 8 17 SW4 b 18 0.1µ 9 16 10 15 11 14 1k 12 13 0.01µ 5V 1k CLK fsc (3.579545MHz) 0.5Vp-p sine wave 82k 0.1µ 5V 1k b SW6 a SW5 d c b a BPF LPF Noise meter Vector scope Spectrum analyzer Oscilloscope CXL1512M Application Circuit – 10 – Y-IN C-IN2 C-IN1 0.1µ 0.01µ 0.01µ 1 24 3.3µ 5V 4 21 1000P 3 22 5 20 2.2k 18 1M 6 7 CXL1512M 19 0.1µ 8 17 9 16 10 15 11 14 12 13 0.01µ 5V 1k CLK fsc (3.579545MHz) 0.5Vp-p sine wave 82k 1k 0.1µ 5V 1k Y-OUT C-OUT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2 23 0.1µ fsc out When Pin 20 (fsc) output is used (connect to VDD when not used) CXL1512M CXL1512M Example of Representative Characteristics Frequency response vs. Supply voltage Low frequency gain vs. Supply voltage 0 Frequency response [dB] Low frequency gain [dB] 2 1 0 –1 –2 4.75 5 –1 –2 –3 4.75 5.25 5 5.25 Supply voltage [V] Supply voltage [V] Comb depth vs. Supply voltage Chrominance linearity vs. Supply voltage –30 0.3 Chrominance linearity [dB] Comb depth [dB] 0.2 –35 0.1 0 –0.1 –0.2 –40 4.75 5 –0.3 4.75 5.25 5 5.25 Supply voltage [V] Supply voltage [V] Differential gain vs. Supply voltage Differential phase vs. Supply voltage 8 5 Differential phase [degree] 4 Differential gain [%] 6 4 2 3 2 1 0 4.75 5 0 4.75 5.25 Supply voltage [V] 5 Supply voltage [V] – 11 – 5.25 Low frequency gain vs. Ambient temperature Frequency response vs. Ambient temperature 2 0 Frequency response [dB] Low frequency gain [dB] CXL1512M 1 0 –1 –2 –10 0 10 20 30 40 Ambient temperature [°C] 50 –1 –2 –3 60 –10 Comb depth vs. Ambient temperature 10 20 30 40 Ambient temperature [°C] 50 60 Chrominance linearity vs. Ambient temperature –30 2 Chrominance linearity [dB] Comb depth [dB] 0 –35 –40 –10 1 0 –1 –2 0 10 20 30 40 50 –10 60 0 Ambient temperature [°C] 10 20 30 40 Ambient temperature [°C] 50 60 Differential phase vs. Ambient temperature Differential gain vs. Ambient temperature Differential phase [degree] 8 Differential gain [%] 6 4 2 0 –10 4 2 0 0 10 20 30 40 Ambient temperature [°C] 50 60 –10 – 12 – 0 10 20 30 40 Ambient temperature [°C] 50 60 CXL1512M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 + 0.4 1.85 – 0.15 13 6.9 + 0.2 0.1 – 0.05 12 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 ± 0.12 M PACKAGE STRUCTURE SONY CODE SOP-24P-L01 EIAJ CODE ∗SOP024-P-0300-A JEDEC CODE MOLDING COMPOUND EPOXY/PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY / 42ALLOY PACKAGE WEIGHT 0.3g – 13 –