CXL5502M/N/P CMOS-CCD 1H Delay Line for NTSC For the availability of this product, please contact the sales office. Description The CXL5502M/N/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. The ICs contain a PLL circuit (quadruple progression). Features • Single power supply (5V) • Low power consumption 95mW (Typ.) • Built-in peripheral circuits • Clamp level of I/O signal can be selected • Built-in quadruple PLL circuit CXL5502M 14 pin SOP (Plastic) CXL5502N 16 pin SSOP (Plastic) CXL5502P 14 pin DIP (Plastic) Functions • 905-bit CCD register • Clock driver • Autobias circuit • Input clamp circuit • Sample and hold circuit • PLL circuit (quadruple progression) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5502M 400 mW CXL5502N 260 mW CXL5502P 800 mW Structure CMOS-CCD Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 572mVp-p (Max.) (at internal clamp condition) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89930E79-PS CXL5502M/N/P Block Diagram and Pin Configuration (Top View) CXL5502M/P AA VSS AB VDD VCO IN PC OUT VDD CLK 14 13 12 11 10 9 8 PLL Autobias circuit Clock driver Timing circuit CCD (905bit) Bias circuit (A) Output circuit Bias circuit (B) (S/H 1bit) Clamp circuit I/O control 1 2 3 4 5 6 7 IN I/O1 I/O2 OUT VSS VSS VCO OUT CXL5502N VSS AB 16 15 AA Autobias circuit VDD VCO OUT PC OUT (N.C) VDD CLK 14 13 12 11 10 9 PLL Clock driver Timing circuit CCD (905bit) Bias circuit (A) Output circuit Bias circuit (B) (S/H 1bit) Clamp circuit I/O control 1 2 3 4 5 6 7 8 IN I/O1 I/O2 OUT VSS (N.C) VSS VCO OUT –2– CXL5502M/N/P Pin Description CXL5502M/P Pin No. Symbol I/O Description Impedance 1 IN I Signal input 2 I/O1 I I/O control 1 3 I/O2 I I/O control 2 4 OUT O Signal output 5 VSS — GND 6 VSS — GND 7 VCO OUT O VCO output 8 CLK I Clock input 9 VDD — Power supply (5V) 10 PC OUT O Phase comparator output 11 VCO IN I VCO input 12 VDD — Power supply (5V) 13 AB O Autobias DC output 14 VSS — GND (SUB) > 10kΩ at no clamp 40 to 500Ω > 100kΩ 600 to 200kΩ CXL5502N Pin No. Symbol I/O Description Impedance 1 IN I Signal input 2 I/O1 I I/O contorl 1 3 I/O2 I I/O contorl 2 4 OUT O Signal output 5 VSS — GND 6 (N.C) — — 7 VSS — GND 8 VCO OUT O VCO output 9 CLK I Clock input 10 VDD — Power supply (5V) 11 (N.C) — — 12 PC OUT O Phase comparator output 13 VCO IN I VCO input 14 VDD — Power supply (5V) 15 AB O Autobias DC output 16 VSS — GND (SUB) > 10kΩ at no clamp 40 to 500Ω > 100kΩ 600 to 200kΩ –3– CXL5502M/N/P Description of Function In the CXL5502M/N/P, the condition of I/O control pins (Pins 2 and 3) control the input signal clamp condition and the mode of the output signal with relation to its input signal. There are 2 modes for the I/O signal. Input waveform Output waveform (1) PN mode (Low level clamp/reverse phase output mode) (2) NP mode (High level clamp/positive phase output mode) Clamp level Clamp level I/O Control Pin (1) I/O1 (Pin 2) Control of the I/O signal condition DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling capacitor of around 1000pF is necessary. GND ............. Input signal is high level clamped and the output signal turns into an inverted signal. (2) I/O2 (Pin 3) Control of the input signal clamp condition 0V ................. Internal clamp condition 5V ................. Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ). Usage in this mode is limited to APL 50% signals and in this mode, the maximum input signal amplitude is 200mVp-p. –4– CXL5502M/N/P Electrical Characteristics Item Symbol Supply current IDDPN Low frequency gain GLPN Frequency response fPN Differential gain DGPN Differential phase DPPN S/H pulse coupling CPPN (Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, Sine wave) See "Electrical Characteristics Test Circuit" Test condition Bias condition Vbias1 (V) Min. 1 2 3 4 5 6 7 (Note 1) SW condition DGNP DPNP SNPN SNNP Note — 10 19 28 mA 2 a b — –2 0 2 dB 3 200kHz ←→ 3.57MHz, b b b 150mVp-p, a a b b a a sine wave c 2.1 –2 –1 0 dB 4 a c — 0 5 7 % 5 a c — 0 5 7 degree 5 — — 350 mVp-p 6 52 56 200kHz, 500mVp-p, sine wave a a b a 5-staircase wave (See Note 5) d 5-staircase wave (See Note 5) d No signal input — c a CPNP S/N ratio Unit a a b b a a ←→ fNP Max. a — — c b — IDDNP GLNP b b Typ. 50% white video signal (See Note 7) e b a b a b b b b b b a a b b a a b b a a b b a a VINPN + 0.5 b a a d VINNP — — dB 7 Notes (1) VINPN and VINNP are defined as follows. VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync tip level. CXL5502 1 Input (IN) VINPN VINNP Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions. Item SW condition 1 2 3 4 5 6 7 VINPN — c b b b a — VINNP — c b a a a — Test point V1 –5– CXL5502M/N/P (2) This is the IC supply current value during clock and signal input. (3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. (Example of calculation) GLPN = 20 log OUT pin output voltage (PN mode) [mVp-p] 500 [mVp-p] [dB] (4) Indicates the dissipation at 3.57MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made according to the following formula. The input part bias is tested at 2.1V. (Example of calculation) fPN = 20 log OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p] OUT pin output voltage (PN mode, 200kHz) [mVp-p] [dB] (5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is input are tested at the vector scope. 143mV 357mV 500mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) (6) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP modes respectively. Test value (mVp-p) –6– CXL5502M/N/P (7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µs Input waveform (Input waveform of NP mode is the inverted waveform in the figure above) Clock fsc (3.579545MHz) sine wave 0.3Vp-p to 1.0Vp-p (0.5Vp-p typ.) –7– –8– e d –1 1 c Vbias1 b SW2 a a SW4 1k a SW3 1µ a V1 b 2 0.1µ 1000P CXL5502M/P b SW5 3 5 5V A a 1000P 4 7 2.1k BPF Note 2) LPF Note 1) ×3 ×3 Noise meter Vector scope Spectrum analyzer Oscilloscope 0 –3 –50 –50 14.3M [Hz] 200 6M Frequency 14.3M [Hz] Note 2) [dB] BPF frequency response d 0 –3 6M Frequency b a SW7 c Note 1) [dB] LPF frequency response b SW6 6 VCO OUT 9V CLK fSC (3.579545MHz) 0.5Vp-p sine wave 9 12 8 11 10 VDD VCO PC VDD CLK IN OUT 82k 0.1µ 1k 1000P 3.3µ I/O1 I/O2 OUT VSS VSS 13 AB 1µ 1000P 1M b 1 IN 14 VSS 3.3µ ∗ When using CXL5502N, change the connection terminal only. (See the block diagram and pin configuration. For NC pins, ground them.) 50% white video signal 5-staircase wave c SW1 b 200kHz 150mVp-p sine wave 3.57MHz 150mVp-p sine wave a 200kHz 500mVp-p sine wave Electrical Characteristics Test Circuit (Using CXL5502M/P) CXL5502M/N/P –9– 1µ 7 VCO OUT (Pin 7) in use 1.8k Input (Positive phase signal) AA 2 1 3 12 AA 1µ 4 2SC403 1k 470 7 8 Transistor used PNP : 2SA1175 6 9 0.1µ 1000P Delay time 250ns LPF 5V 2200 Transistor used NPN : 2SC403 2200 2200 (ex. TH356LSM-4303ZED Toukou made) 27p 33p 2700 fSC 0.5Vp-p sine wave (Positive phase signal) A Output ∗ When using CXL5502N, change the connection terminal only. (See the block diagram and pin configuration. For NC pins, ground them.) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 4fSC 560k 1µ 330k 5 10 1k 0.1µ 3.3µ CXL5502M/P 11 82k 1000P (Reverse phase signal) 1000P 13 3.3µ 14 5V 1M 1.8k 5V Application Circuit (Using CXL5502M/P) CXL5502M/N/P CXL5502M/N/P Example of Representative Characteristics Supply current vs. Ambient temperature Low frequency gain vs. Ambient temperature 1 Low frequency gain [dB] Supply current [mA] 30 20 10 –20 0 20 40 60 0 –1 –2 –3 –20 80 0 20 40 60 80 Ambient temperature [°C] Ambient temperature [°C] Differential gain vs. Ambient temperature Frequency response vs. Ambient temperature 10 0 Differential gain [%] Frequency response [dB] 8 –1 –2 6 4 2 –3 –20 0 20 40 60 0 –20 80 Ambient temperature [°C] 40 60 80 Low frequency gain vs. Supply voltage Supply current vs. Supply voltage 1 Low frequency gain [dB] Supply current [mA] 20 Ambient temperature [°C] 30 20 10 4.75 0 5 0 –1 –2 –3 4.75 5.25 5 Supply voltage [V] Supply voltage [V] – 10 – 5.25 CXL5502M/N/P Differential gain vs. Supply voltage Frequency response vs. Supply voltage 0 10 Differential gain [%] –1 –2 6 4 2 –3 4.75 5 Supply voltage [V] 0 4.75 5.25 5 Supply voltage [V] 5.25 Frequency response 2 0 Gain [dB] Frequency response [dB] 8 –2 –4 –6 10k 100k Frequency [Hz] – 11 – 1M 10M CXL5502M/N/P Package Outline Unit: mm CXL5502M 14PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 9.9 – 0.1 14 8 6.9 7 0.45 ± 0.1 + 0.1 0.2 – 0.05 1.27 0.24 0.5 ± 0.2 1 + 0.2 0.1 – 0.05 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-14P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP014-P-0300 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE 14PIN SOP (Plastic) 300mil 10.2 ± 0.3 0.15 5.3 ± 0.3 A 7 1 1.44 MAX 7.8 ± 0.4 8 14 0.15 ± 0.05 0.4 ± 0.1 20 MAX 1.27 0.75 ± 0.2 0.05 MIN 0.13 M DETAIL A 10° MAX PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-14P-L121 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗SOP014-P-0300-AX LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE – 12 – CXL5502M/N/P CXL5502N 16PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗5.0 ± 0.1 0.1 9 16 6.4 ± 0.2 ∗4.4 ± 0.1 A 8 1 + 0.05 0.15 – 0.02 0.65 + 0.1 0.22 – 0.05 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-16P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE SSOP016-P-0044 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE CXL5502P + 0.1 05 0.25 – 0. 14PIN DIP (PLASTIC) 8 7.62 14 + 0.3 6.4 – 0.1 + 0.4 19.2 – 0.1 1 0° to 15° 7 0.5 MIN 3.0 MIN 0.5 ± 0.1 + 0.4 3.7 – 0.1 2.54 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-14P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP014-P-0300 LEAD MATERIAL 42/COPPER ALLOY JEDEC CODE Similar to MO-001-AH PACKAGE MASS 0.9g – 13 –