SONY CXL5507M

CXL5507M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5507M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
CXL5507M
8 pin SOP (Plastic)
CXL5507P
8 pin DIP (Plastic)
Features
• Single 5V power supply
• Low power consumption 50mW (Typ.)
• Built-in peripheral circuits
Functions
• 453-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
Absolute Maximum Ratings (Ta = 25°C)
6
V
• Supply voltage
VDD
• Operating temperature Topr
–10 to +60
°C
• Storage temperature Tstg
–55 to +150 °C
• Allowable power dissipation
PD
CXL5507M
350
mW
CXL5507P
480
mW
Structure
CMOS-CCD
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5%
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK
7.159090
MHz
• Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 527mVp-p (Max.)
(at internal clamp condition)
AB
VDD
VGA
CLK
Blook Diagram and Pin Configuration (Top View)
8
7
6
5
Auto-bias circuit
Timing circuit
Bias circuit
Clock driver
CCD
(453bit)
Bias circuit (A)
Output circuit
Bias circuit (B)
(S/H 1bit)
VGB
3
4
VSS
2
OUT
1
IN
Clamp circuit
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E90908A7X-PS
CXL5507M/P
Pin Description
Pin No.
Symbol
Description
I/O
Impedance
> 10kΩ at no clamp
1
IN
I
Signal input
2
VGB
I
Gate control B
3
OUT
O
Signal output
4
VSS
—
GND
5
CLK
I
Clock input
6
VGA
O
Gate control A
7
VDD
—
Power supply (5V)
8
AB
O
Auto-bias DC output
40 to 500Ω
> 100kΩ
600 to 200kΩ
Description of I/O Signals
Input signals are low level clamped and output signals are
inverted in relation to the input signals. Also, the clamp
condition of input signals are controlled by VGB (Pin 2)
conditions.
0V ........ Internal clamp condition
5V ........ Non internal clamp condition
Center biased to approx. 2.1V by means of
the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to
APL 50% and the maximum input signal
amplitude is 200mVp-p.
Input waveform
Output waveform
Clamp
level
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 7.159090MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Item
Symbol
Test condition
SW condition
Bias
condition
V1 (V)
Min.
Typ.
Max.
Unit
Note
—
5
10
15
mA
1
–2
0
2
dB
2
0
dB
3
1
2
3
4
5
a
a
b
a
Supply current
IDD
Low frequency
gain
GL
200kHz,
a
500mVp-p, sine wave
a
b
a
b
Frequency
response
fg
200kHz ←
→ 2MHz,
b
150mVp-p, sine wave c
a
a
b
b
2.1
–2
–1
S/H pulse
coupling
CP
No signal input
— b
a
b
a
2.1
—
—
S/N ratio
SN
No signal input
— b
a
b
c
54
56
—
b
a
b
a
a
37
40
43
b
a
b
a
a
18
20
22
b
a
b
a
a
56
60
64
LIS
Linearity
LIL
LIC
—
5-staircase wave
(For luminance
signals only)
–2–
—
350 mVp-p
4
dB
5
%
6
CXL5507M/P
Notes
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
(3) Indicates the dissipation at 2MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, calculation is made
according to the following formula. Input bias is tested at 2.1V.
fg = 20 log
OUT pin otuput voltage (2MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
(4) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. Input bias is tested at 2.1V.
Test value
(mVp-p)
(5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is
calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following
formula.
S/N = –20 • Iog
Noise (mVrms)
[dB]
0.5 • 10 GL/20
(6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance
signals only) and calculated according to the formula below.
(However, output signals become inverted with regards to input.)
Va
LIS = Vs × 100 [%]
Va
100 IRE
Vc
500mV
Vp
Vs
40 IRE
–3–
LIL =
Vp
× 100 [%]
Va
LIC = Vc × 100 [%]
Va
CXL5507M/P
Clock
2fsc (7.159090MHz) sine wave
(0.5Vp-p typ.)
–4–
–5–
5-staircase wave
(Luminance
signals only)
d
c
SW1
b
200kHz
150mVp-p
sine wave
2MHz
150mVp-p
sine wave
a
200kHz
500mVp-p
sine wave
Electrical Characteristics Test Circuit
b
a SW2
V1
1k
a
SW3
1µ
1M
b
2
1
1000p
VGB
VDD
7
IN
AB
8
1µ
3.3µ
5V
a
6
1000p
3
b
SW4
OUT
VGA
1000p
4
VSS
CLK
5
0.1µ
9V
2.1k
b
a
BPF
Note)
×3
–50
0
–3
10k
3M
7.2M
Frequency [Hz]
Note)
[dB] BPF frequency response
SW5 c
CLK
2fSC (7.159090MHz)
0.5Vp-p
sine wave
Noise meter
Spectrum
analyzer
Oscilloscope
CXL5507M/P
Input
Application Circuit
1µ
5V
1M
1
8
1µ
3.3µ
–6–
3
6
10
1000p
2.2k
PNP: 2SA1175
4
5
0.1µ
Delay time
140ns
LPF
2.2k
5V
NPN: 2SC403
2.2k
2.2k
Output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2
12
7
1000p
2fSC
0.5Vp-p
sine wave
CXL5507M/P
CXL5507M/P
Example of Representative Characteristics
Low frequency gain vs. Supply voltage
1.5
15
1
Low frequency gain [dB]
Supply current [mA]
Supply current vs. Supply voltage
20
10
5
0
4.75
5
Supply voltage [V]
0.5
0
–0.5
4.75
5.25
Frequency response vs. Supply voltage
5
Supply voltage [V]
5.25
Linearity (LIS) vs. Supply voltage
0
–0.5
Linearity (LIS) [%]
Frequency response [dB]
44
–1
36
–1.5
–2
4.75
40
5
Supply voltage [V]
32
4.75
5.25
Linearity (LIL) vs. Supply voltage
5
Supply voltage [V]
5.25
Linearity (LIC) vs. Supply voltage
30
70
66
Linearity (LIC) [%]
Linearity (LIL) [%]
25
20
62
58
15
54
10
4.75
5
Supply voltage [V]
50
4.75
5.25
–7–
5
Supply voltage [V]
5.25
CXL5507M/P
Low frequency gain vs. Ambient temperature
1.5
15
1
Low frequency gain [dB]
Supply current [mA]
Supply current vs. Ambient temperature
20
10
5
0
–20 –10
0
10 20 30 40 50
Ambient temperature [°C]
60
0.5
0
–0.5
–20 –10
70
Frequency response vs. Ambient temperature
0
10 20 30 40 50
Ambient temperature [°C]
60
70
Linearity (LIS) vs. Ambient temperature
0
–0.5
Linearity (LIS) [%]
Frequency response [dB]
44
–1
40
36
–1.5
–2
–20 –10
0
10 20 30 40 50
Ambient temperature [°C]
60
32
–20 –10
70
Linearity (LIL) vs. Ambient temperature
0
10 20 30 40 50
Ambient temperature [°C]
60
70
Linearity (LIC) vs. Ambient temperature
30
70
66
Linearity (LIC) [%]
Linearity (LIL) [%]
25
20
62
58
15
54
10
–20 –10
0
10 20 30 40 50
Ambient temperature [°C]
60
50
–20 –10
70
–8–
0
10 20 30 40 50
Ambient temperature [°C]
60
70
CXL5507M/P
Package Outline
Unit: mm
CXL5507M
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1 – 0.1
8
5
1
+ 0.2
0.1 – 0.05
6.9
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
0.5 ± 0.2
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-8P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP008-P-0300
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
CXL5507P
+ 0.3
6.4 – 0.1
+ 0.4
9.4 – 0.1
5
7.62
8
+ 0.1
0.05
0.25 –
8PIN DIP (PLASTIC)
0° to 15°
4
1
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-8P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP008-P-0300
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
–9–