CXP5084/5086 CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP5084/5086 is a CMOS 4-bit microcomputer which consists of 4-bit CPU, ROM, RAM, I/O port, 8-bit timer, 8-bit timer/counter, 18-bit time base timer, 8-bit serial I/O, vector interruption, power on reset function and a liquid crystal displayer (LCD) controller/ driver. They are integrated into a single clip with the standby function etc. which are to be operated at low power consumption. • • • • • • • • • • • • • 64 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Instruction cycle • 64 pin SDIP (Plastic) 3.8µs/4.19MHz 1.9µs/4.19MHz (High speed version) ROM capacity 4096 × 8 bits (CXP5084) 6144 × 8 bits (CXP5086) RAM capacity 400 × 4 bits (Including stack, display area) 32 general purpose I/O ports LCD controller/driver (Direct drive possible) — Optional specification of 24, 20 or 16 segment outputs — 1/2, 1/3, 1/4 duty selectable through program — 1/3 bias 2 external interruption input pins 8-bit/4-bit variable serial I/O 8-bit timer, 8-bit timer/event counter and 18-bit time base timer are independently controllable Arithmetic and logical operations possible between the entire RAM area, I/O area and the accumulator by means of memory mapped I/O Reference to the entire ROM area is possible with the table look-up instruction 2 types of power down modes: sleep and stop Power on reset circuit (Mask option) Available option of either crystal oscillation or CR oscillation (mask option) types for the oscillation circuit 64-pin plastic SDIP/QFP available Piggyback package (CXP5080) available Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E90377A7Z-PS CXP5084/5086 Block Diagram (Enables to specify the I/O with bit unit) Port A (Enable to specify the I/O with port unit) Port B (Combines use of mask with segment output, optional) 4 4 4 4 Port C Port D Port E Port F Program counter (13) ALU Register Accumulator Flag Data memory Program memory 400 × 4 bits Timer (8) Timer/Counter (8) 4096 × 8 bits (CXP5084) Serial I/O (8) 6144 × 8 bits (CXP5086) Stack Data memory Interrupt control Instruction control EXTAL Port X Clock contorl Port Y XTAL (Common with Port E, Port F) (Common with serial I/O) –2– RST VSS VDD INT1 WP PY0 PY1 PY2/INT2 PY3/EC SEG16 SEG0 COM0 to to to SEG23 SEG15 COM3 PX0/SC 4 PX2/SOA 16 PX1/SOB 8 PX3/SI VL VLC1 VLC2 VLC3 Time base timer (18) LCD controller/driver CXP5084/5086 Pin Assignment 1 (Top View) 64-pin SDIP Package VL 1 64 VDD XTAL 2 63 VLC3 EXTAL 3 62 VLC2 RST 4 61 VLC1 WP 5 60 COM0 INT1 6 59 COM1 PY0 7 58 COM2 PY1 8 57 COM3 PY2/INT2 9 56 SEG0 PY3/EC 10 55 SEG1 PX0/SC 11 54 SEG2 PX1/SOB 12 53 SEG3 PX2/SOA 13 52 SEG4 PX3/SI 14 51 SEG5 PD0 15 50 SEG6 PD1 16 49 SEG7 PD2 17 48 SEG8 PD3 18 47 SEG9 PC0 19 46 SEG10 PC1 20 45 SEG11 PC2 21 44 SEG12 PC3 22 43 SEG13 PB0 23 42 SEG14 PB1 24 41 SEG15 PB2 25 40 SEG16/PF0 PB3 26 39 SEG17/PF1 PA0 27 38 SEG18/PF2 PA1 28 37 SEG19/PF3 PA2 29 36 SEG20/PE0 PA3 30 35 SEG21/PE1 NC 31 34 SEG22/PE2 VSS 32 33 SEG23/PE3 Note) Do not make any connection to NC pin. –3– CXP5084/5086 COM2 COM1 COM0 VLC1 VLC2 VLC3 VL VDD XTAL EXTAL RST WP INT1 Pin Assignment 2 (Top View) 64-pin QFP Package 64 63 62 61 60 59 58 57 56 55 54 53 52 PY0 1 51 COM3 PY1 2 50 SEG0 PY2/INT2 3 49 SEG1 PY3/EC 4 48 SEG2 PX0/SC 5 47 SEG3 PX1/SOB 6 46 SEG4 PX2/SOA 7 45 SEG5 PX3/SI 8 44 SEG6 PD0 9 43 SEG7 PD1 10 42 SEG8 PD2 11 41 SEG9 PD3 12 40 SEG10 PC0 13 39 SEG11 PC1 14 38 SEG12 PC2 15 37 SEG13 PC3 16 36 SEG14 PB0 17 35 SEG15 PB1 18 34 SEG16/PF0 PB2 19 33 SEG17/PF1 SEG18/PF2 SEG19/PF3 SEG20/PE0 SEG21/PE1 SEG22/PE2 SEG23/PE3 NC VSS PA3 PA2 PA1 PA0 PB3 20 21 22 23 24 25 26 27 28 29 30 31 32 Note) Do not make any connection to NC pin. –4– CXP5084/5086 (Ta = –20 to +75°C, VSS = 0V reference) Absolute Maximum Ratings Item Symbol Ratings Unit Power supply voltage VDD V LCD bias voltage VLC1, VLC2, VLC3 –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +7.0∗1 V Input voltage VIN Output voltage VOUT High level output current IOH –5 mA High level total output current ∑IOH –50 mA Low level output current IOL 15 mA Low level total output current ∑IOL 50 mA Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C 1000 mW 600 mW Allowable power dissipation PD Remarks V V General purpose port∗2 : per pin Entire pin total General purpose port∗2 : per pin Entire pin total SDIP QFP ∗1 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. ∗2 The PE and PF are specified when PA to PD, PX0 to PX2, PY0, PY1 and mask option are selected as the port. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. (VSS = 0V reference) Recommended Operating Conditions Item Power supply voltage LCD bias voltage Symbol Min. Max. Unit 4.5 5.5 V Guaranteed range during operation 3.5 5.5 V Guaranteed data hold operation range during stop VSS VDD V Liquid crystal power supply voltage∗1 0.7VDD VDD V 0.8VDD VDD V VDD – 0.4 VDD + 0.3 V VIL 0 0.3VDD V VILS 0 0.2VDD V VILEX –0.3 0.4 V Topr –20 +75 °C VDD VLC1, VLC2, VLC3 VIH High level input voltage VIHS VIHEX Low level input voltage Operating temperature Remarks Hysteresis input∗2 EXTAL pin∗3 Hysteresis input∗2 EXTAL pin∗3 ∗1 The optimum value is determined by the characteristics of the liquid crystal display element used. ∗2 They are the respective pins of INT1, WP, PX0, PX3, PY2, PY3 and RST. ∗3 Specified only during external clock input. –5– CXP5084/5086 Electrical Characteristics DC characteristics Item High level output voltage Low level output voltage Symbol VOH Pin PA to PF∗1, PX0 to PX2, PY0, PY1, VL (VOL only) RST (VOL only) VOL IIH Input current (Ta = –20 to +75°C, VSS = 0V reference) EXTAL∗4 IIL High impedance IIZ I/O leakage current RST∗5 PA to PF∗6, PX0 to PX2∗6, PX3∗8, PY0∗7, PY1∗7, PY2∗8, PY3∗8, INT1∗8, WP∗8, RST∗5 Common output impedance RCOM COM0 to COM3 Segment output impedance RSEG SEG0 to SEG15 SEG16 to SEG23∗1 VDD = 4.5V, IOH = –10µA∗3 VDD = 4.5V, IOH = –200µA∗3 IDDSP IDDS CIN Min. Typ. Max. Unit 4.0 V 3.5 V 4.0 V 2.4 V VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V 0.5 40 µA –0.5 –40 µA –1.5 –400 µA –2.0 mA ±10 µA 3 5 kΩ 5 15 kΩ 1.3 (2)∗9 4 (6)∗9 mA 0.4 1.2 (0.5)∗9 (2)∗9 mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V VI = 0, 5.5V VDD = 5V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V VDD = 5.5V During external clock 1MHz operation Entire output pins open IDD Input capacitance VDD = 4.5V, IOH = –0.5mA∗2 VDD = 4.5V, IOH = –1.0mA∗2 IILE IILR Current power supply Condition VDD Sleep mode Stop mode VLC1 to VLC3, COM0 to COM3, SEG0 to SEG15, Clock 1MHz SEG16 to SEG23∗1, 0V for no measured pins Other pins than VDD, VSS 10 10 µA 20 pF ∗1 PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when the combined pins are selected as the segment output. ∗2 It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and PY1 are when the inverter output circuit is selected. ∗3 It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance. ∗4 It is when the crystal or ceramic oscillation circuit is selected. ∗5 The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. ∗6 The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during the 3-state output circuit or standby is selected at high impedance. ∗7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and specify the leakage current when the port state during standby is selected at high impedance. ∗8 The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current. ∗9 The value in parentheses shows the specification of the current power supply of the high speed version. –6– CXP5084/5086 AC characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Symbol System clock frequency Pin Condition XTAL EXTAL fc tXL tXH System clock input rising and falling tCR times tCF tEL Event count clock input pulse width tEH Event count clock input rising and tER falling times tEF System clock input pulse width Min. Fig. 1., Fig. 2. 1 EXTAL Fig. 1., Fig. 2.∗1 External clock drive Fig. 1., Fig. 2.∗1 External clock drive EC Fig. 3. EC Fig. 3. EXTAL Max. Unit 5 90 MHz ns 200 tsys∗2 + 0.05 ns µs 20 ms ∗1 The external clock in Fig. 2. is specified only when the option is selected for crystal or ceramic oscillation. ∗2 In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc Note) When adjusting the frequency accurately, there may be cases in which they differ from Fig. 2. 1/fc VDD – 0.4V EXTAL 0.4V tCF tXH tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation EXTAL External clock∗1 CR oscillation XTAL EXTAL XTAL EXTAL XTAL R OPEN C1 C2 C Fig. 2. Clock applying condition 0.8VDD EC 0.2V tEH tEF tEL Fig. 3. Event count clock timing –7– tER CXP5084/5086 (2) Serial transfer Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Symbol Serial transfer clock (SC) cycle time tKCY Serial transfer clock (SC) high and low level widths tKH tKL Pin SC Condition tSIK SI Serial data input hold time (against SC ↑) tKSI SI High data∗3 output delay time from the SC falling time tKSOA tKSOB High data∗4 output delay time tKSOA from the SC falling time tKSOB tKSOA Low data output delay time from the SC falling time tKSOB Unit µs Output mode∗1 Output mode∗2 SC input mode 0.1 µs SC output mode 0.2 µs tsys/8 + 0.5 µs 0.1 µs Input mode Serial data input setup time (against SC ↑) Max. tsys/4 + 1.42 tsys tsys/8 + 0.7 tsys/2 – 0.1 tsys/2 – 1.6 Input mode Output mode SC Min. SC input mode SC output mode SOA SOB SOA SOB SOA SOB µs µs µs µs tsys/8 + 0.5 µs tsys/8 + 1.6 µs tsys/8 + 0.5 µs ∗1 It is specified when SC pin is selected to the 3-state output by the mask option. ∗2 It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. ∗3 It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option. ∗4 It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option. Note 1) In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc Note 2) The load of data output delay time is 50pF + 1TTL. –8– CXP5084/5086 tKCY tKL tKH SC 0.8VDD 0.2VDD tSIK tKSI 0.8VDD Input data SI 0.2VDD tKSOA tKSOB 0.8VDD SOA SOB Output data 0.2VDD Fig. 4. Serial transfer timing (3) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Pin Condition Min. INT1 During edge detection mode tsys + 0.05 tsys + 0.05 2tsys µs Reset input low level width tI1H, tI1L tI2H, tI2L tRSL WP Stop mode ns tWPH 500 Wake-up input high level width Sleep mode tsys + 0.05 µs Item External interruption high and low level widths Symbol INT2 RST Note) In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc –9– Max. Unit µs µs CXP5084/5086 tI1L tI1H 0.8VDD INT1 (Rising edge) 0.2VDD tI1H tI1L 0.8VDD INT1 (Falling edge) 0.2VDD tI2L tI2H 0.8VDD INT2 0.2VDD Fig. 5. Interruption input timing tRSL RST 0.2VDD Fig. 6. Reset input timing tWPH 0.8VDD WP Fig. 7. Wake-up input timing Power on reset∗ (Ta = –20 to +75°C, VSS = 0V reference) Item Symbol tR Power supply cut-off time tOFF Power supply rising time Pin VDD Condition Power on reset Min. Max. Unit 0.05 50 ms Repectitive power on reset 1 ∗ Specifies only when power on reset function is selected. VDD 4.5V 0.2V 0.2V tR tOFF Raise the power supply smoothly. Fig. 8. Power on reset – 10 – ms CXP5084/5086 Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750 LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 32 64 20 1 16.3 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 + 0.4 14.0 – 0.1 Package Outline PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 11 –