CXP740000 CMOS 8-bit Single Chip Microcomputer Description The CXP740000 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP740056/740096/740010. Piggy/evaluation chip 100 pin PQFP (Ceramic) Features • A wide instruction set (211 instructions) which LQFP supported QFP supported covers various types of data. —16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 167ns at 24MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (2.7 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Applicable EPROM CXP27C702K (Maximum 120K bytes are available.) • Incorporated RAM capacity 4096 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 10.3µs/24MHz) — Serial interface Start-stop sync type (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels 8-bit clock sync type (MSB/LSB first selectable), 1 channel — Timer 8-bit timer, 2 channels 8-bit timer/counter, 2 chennels 19-bit time-base timer, 16-bit capture timer/counter 32kHz timer/counter — Remote control unit receive circuit Internal noise elimination circuit Internal 8-bit, 6-stage FIFO for measured data — PWM output 12 bits, 12 channels • Interruption 24 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP740000. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98429-PS CXP740000 PI5/SCK1 PI4/INT1/CS1 PI2/NMI PI3/TO0/ADJ PI1/RMC PK2/TEX VSS PK1/TX VDD NC PA6 PA7 PA4 PA5 PA3 PA1 PA2 PA0 PC6 PC7 Pin Assignment in Piggyback Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PC5 1 80 PI6/SO1 PC4 2 79 PI7/SI1 PC3 3 78 PE0/INT0 PC2 4 77 PE1/INT2 PE4 73 PE5 72 PE6 71 PE7 8 9 PB4/TO2 10 PB3 11 PB2 12 PB1 13 PB0 14 PJ7 15 PJ6 16 PJ5 17 PJ4 18 PJ3 19 PJ2 20 PJ1 PJ0 A6 3 2 1 32 31 30 5 29 A8 A5 6 28 A9 A4 7 27 A11 A3 8 NC 26 A2 9 25 OE A1 10 24 A10 A0 11 CE 23 NC 12 22 D7 D0 13 21 D6 70 PG0/TxD 69 PG1/RxD 68 PG2/EC0 67 PG3/EC1 66 PG4/EC2 65 PG5/INT3 64 PG6/INT4 63 PG7/CINT 62 AN0 61 AN1 21 60 AN2 22 59 AN3 58 PF0/AN4 D5 D4 D3 A16 D2 23 GND 14 15 16 17 18 19 20 D1 PD7 4 A14 PB6/SO2 PB5/SCK2 A13 7 VDD PE3/PWM1 74 PB7/SI2 NC PE2/PWM0 75 A12 76 6 A15 5 PC0 A7 PC1 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 PK3/SCK0 PK5/SI0 PK4/SO0 PK6/CS0 XTAL EXTAL VSS RST PK7/TO1 PH0 PH1 PH2 PH4 PH3 PH5 PH7 PH6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. –2– CXP740000 PE0/INT0 PI6/SO1 PI7/SI1 PI4/INT1/CS1 PI5/SCK1 PI3/TO0/ADJ PI2/NMI PK2/TEX PI1/RMC PK1/TX VDD VSS NC PA6 PA7 PA4 PA5 PA2 PA3 PA1 PA0 PC6 PC7 PC5 PC4 Pin Assignment in Piggyback Mode (LQFP package) A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PC3 1 PC2 2 PC1 3 PC0 4 PB7/SI2 PB6/SO2 PB5/SCK2 PE1/INT2 PE2/PWM0 73 PE3/PWM1 72 PE4 5 71 PE5 6 70 PE6 A15 7 1 A12 VDD 30 2 A14 29 PB4/TO2 8 A7 3 28 A13 PB3 9 A6 4 27 A8 PB2 75 74 10 A5 5 A9 26 PB1 11 A4 6 25 A11 PB0 12 A3 7 24 OE PJ7 13 A2 8 23 A10 PJ6 14 A1 9 22 CE PJ5 15 PJ4 16 NC 11 20 D6 PJ3 17 D0 12 19 D5 PJ2 18 PJ1 19 PJ0 20 PD7 A0 10 D7 21 69 PE7 68 PG0/TxD 67 PG1/RxD 66 PG2/EC0 65 PG3/EC1 64 PG4/EC2 63 PG5/INT3 62 PG6/INT4 61 PG7/CINT 60 AN0 59 AN1 58 AN2 57 AN3 56 PF0/AN4 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF D1 13 D2 14 D3 17 15 GND D4 18 A16 16 AVSS PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 PK3/SCK0 PK4/SO0 PK5/SI0 EXTAL PK6/CS0 XTAL VSS RST PH0 PK7/TO1 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD1 PD2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. –3– CXP740000 PI5/SCK1 PI3/TO0/ADJ PI4/INT1/CS1 PI1/RMC PI2/NMI PK2/TEX PK1/TX VSS NC VDD PA7 PA5 PA6 PA4 PA3 PA2 PA1 PC7 PA0 PC6 Pin Assignment in Evaluator Mode (QFP package) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 78 PE0/INT0 4 77 PE1/INT2 PC1 5 76 PE2/PWM0 PC0 6 75 PE3/PWM1 PB7/SI2 7 74 PE4 73 PE5 9 72 PE6 10 71 PE7 PB6/SO2 PB5/SCK2 PB4/TO2 8 PB3 11 PB2 12 PB1 13 PB0 14 PJ7 15 PJ6 4 A6/D6 1 32 31 30 5 29 A8 A5/D5 6 28 A9 A4/D4 7 27 A11 A3/D3 8 26 NC A2/D2 16 2 3 A13 3 PC2 A14 PC3 VDD PI7/SI1 NC PI6/SO1 79 A15 80 2 A12 1 PC4 A7/D7 PC5 9 25 HALT A1/D1 10 24 A10 A0/D0 11 23 E/P 70 PG0/TxD 69 PG1/RxD 68 PG2/EC0 67 PG3/EC1 66 PG4/EC2 65 PG5/INT3 64 PG6/INT4 63 PG7/CINT 62 AN0 61 AN1 21 60 AN2 59 AN3 58 PF0/AN4 57 PF1/AN5 PJ5 17 PJ4 18 PJ3 19 PJ2 20 PJ1 NC 12 22 I/T RD 13 21 MON 14 15 16 17 18 19 20 PF2/AN6 26 PF3/AN7 C1 56 55 RST 25 PD4 C2 PD5 A16 24 GND PD6 SYNC 22 23 WR PJ0 PD7 PD3 27 54 AVDD PD2 28 53 AVREF PD1 29 52 AVSS PD0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 PK3/SCK0 PK5/SI0 PK4/SO0 PK6/CS0 EXTAL XTAL VSS RST PK7/TO1 PH0 PH1 PH3 PH2 PH4 PH6 PH5 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. –4– CXP740000 PE0/INT0 PI6/SO1 PI7/SI1 PI4/INT1/CS1 PI5/SCK1 PI2/NMI PI3/TO0/ADJ PK2/TEX PI1/RMC PK1/TX VDD VSS NC PA6 PA7 PA4 PA5 PA2 PA3 PA1 PA0 PC6 PC7 PC5 PC4 Pin Assignment in Evaluator Mode (LQFP package) A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE1/INT2 74 PE2/PWM0 PC3 1 PC2 2 PC1 3 73 PE3/PWM1 4 72 PE4 PC0 PB7/SI2 5 71 PE5 PB6/SO2 6 70 PE6 PB5/SCK2 7 69 PE7 PB4/TO2 8 A7/D7 PB3 9 A6/D6 PB2 10 A5/D5 A15 1 A12 VDD 30 2 A14 29 28 A13 4 27 A8 5 26 A9 3 PB1 11 A4/D4 6 25 A11 PB0 12 A3/D3 7 24 HALT PJ7 13 PJ6 14 PJ5 15 A0/D0 PJ4 16 NC 11 20 MON PJ3 17 RD 12 19 RST PJ2 18 PJ1 19 PJ0 20 PD7 A2/D2 8 A1/D1 9 E/P 22 10 WR A10 23 I/T 21 13 C1 18 68 PG0/TxD 67 PG1/RxD 66 PG2/EC0 65 PG3/EC1 64 PG4/EC2 63 PG5/INT3 62 PG6/INT4 61 PG7/CINT 60 AN0 59 AN1 58 AN2 57 AN3 56 PF0/AN4 21 55 PF1/AN5 PD6 22 54 PF2/AN6 PD5 23 53 PF3/AN7 PD4 24 52 AVDD PD3 25 51 AVREF SYNC 14 15 GND C2 17 A16 16 AVSS PF5/AN9 PF4/AN8 PF6/AN10 PF7/AN11 PK4/SO0 PK3/SCK0 PK5/SI0 EXTAL PK6/CS0 XTAL VSS RST PH0 PK7/TO1 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PD0 PD2 PD1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. –5– CXP740000 EPROM Read Timing (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference) Item Symbol Pin Min. Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Max. Unit 100∗1 50∗2 0 ns ns ∗1 At 12MHz operation (VDD = 4.5 to 5.5V) ∗2 At 12MHz operation (VDD = 2.7 to 5.5V), at 24MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Mask ROM Piggy/evaluation chip CXP740056 CXP740096 CXP740010 CXP740000-U01Q CXP740000-U01R 100-pin plastic QFP/LQFP 100-pin ceramic PQFP Option item Package ROM capacity Pull-up resistor for reset pin 56K bytes 96K bytes 120K bytes Existent/Non-existent –6– EPROM 120K bytes Existent CXP740000 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggy/evaluation chip Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe EPROM adaptor Pin 1 marking Note) Evaluation cap should be connected to CPU probe. Pin 1 index –7– CXP740000 Package Outline Unit: mm 100PIN PQFP (CERAMIC) 18.7 PIN NO. 1 INDEX 16.3 ± 0.2 INDEX 100 81 81 80 PIN No. 1 INDEX 1 80 0.65 ± 0.05 1 100 0.3 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 1.0 0.7 0.3 6.0 30 51 31 1.3 ± 0.3 51 50 9.48 11.66 30 50 31 0.45 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL PQFP-100C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g 10.44 MAX 0.50 ± 0.25 + 0.05 0.15 – 0.02 100PIN PQFP(CERAMIC) 16.0 ± 0.5 76 + 0.08 0.18 – 0.03 1.5 50 3.2 ± 0.2 0.5± 0.05 51 26 100 1 25 INDEX INDEX 6.9 0.8 ± 0.1 + 0.15 0.2 – 0.13 + 0.05 0.127 – 0.02 3.32 12.0 ± 0.15 12.4 14.0 ± 0.2 75 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC SONY CODE PQFP-100C-L05 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000 LEAD MATERIAL 42 ALLOY PACKAGE MASS 2.4g JEDEC CODE –8– CERAMIC SONY CODE JEDEC CODE 3.57 ± 0.36 24.7 22.3 ± 0.25 4.5