CXP853P40A CMOS 8-bit Single-chip Microcomputer Description The CXP853P40A are a highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM generator, remote control receiver, HSYNC counter, power supply frequency counter, and watchdog timer. Also, this IC provides power-on reset and sleep functions. The designers have ensured low power consumption for these powerful microcomputers. The CXP853P40A is the one-chip PROM version of the CXP85340A with on-chip mask ROM, providing the function of being able to write directly into the program. Furthermore, because of the OSD character ROM can also be written directly into, it is suitable for evaluation use during system development and for small quantity production. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Features • A wide instruction set (213 instructions) which covers various of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle 1µs/4MHz (4MHz verison) 0.5µs/8MHz (8MHz verison) • Incorporated PROM capacity 40K bytes (For program) 6.75K bytes (For OSD) • Incorporated RAM capacity 576 bytes • Peripheral funcitons — On-screen display function 12 × 18 dots, 256 types, 15 colors, 12 lines of 21 characters Black frame output half blanking, shadow, background color on full screen/half blanking Double scanning mode supported, jitter elimination circuit — I2C bus interface — PWM output 14 bits, 1 channel 8 bits, 8 channels — Remote control receiver circuit 8-bit pulse measuring counter, 6-stage FIFO — A/D converter 8-bit, 4 channels, successive approximation system (conversion time of 40µs/4MHz, 8MHz) — HSYNC counter — Power supply frequency counter — Watchdog timer — Serial I/O 8-bit synchronized — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer • Interruption 14 factors, 14 vectors, multiple interrupt possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93Z19A7Z-PS HSYNC COUNTER AC TIMER A/D CONVERTER I2C INTERFACE UNIT PD4/HSI PD5/ACI PE2/AN0 to PE5/AN3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 REMOCON TIMER/COUNTER PD7/EC PE7/TO PD6/RMC SERIAL I/O PD3/SI PD2/SO PD1/SCK FIFO ON SCREEN DISPLAY 2 2 PE1/INT1 INTERRUPT CONTROLLER PD0/INT2 PE0/INT0 14BIT PWM WATCHDOG TIMER PE6/PWM XLC EXLC R G B I YS YM PA7/HSYNC PA6/VSYNC 8 BIT PWM 8CH PROM 40K BYTES SPC700 CPU CORE PF0/PWM0 to PF7/PWM7 Vpp VSS MP VDD XTAL RST EXTAL PRESCALER/ TIME BASE TIMER RAM 576 BYTES CLOCK GEN./ SYSTEM CONTROL PF0 to PF7 PE6 to PE7 PE0 to PE5 PD0 to PD7 PC0 to PC7 PA0 to PA7 PB0 to PB7 PORT A PORT B PORT C PORT D PORT E –2– PORT F Block Diagram CXP853P40A CXP853P40A Pin Assignment 1 (Top View) 64 pin SDIP Package PA7 1 64 VDD PA6 2 63 Vpp PA5 3 62 VSS PA4 4 61 MP PA3 5 60 PF0/PWM0 PA2 6 59 PF1/PWM1 PA1 7 58 PF2/PWM2 PA0 8 57 PF3/PWM3 PB7 9 56 PF4/PWM4/SCL0 PB6 10 55 PF5/PWM5/SCL1 PB5 11 54 PF6/PWM6/SDA0 PB4 12 53 PF7/PWM7/SDA1 PB3 13 52 BLK PB2 14 51 R PB1 15 50 G PB0 16 49 B PC7 17 48 VSYNC PC6 18 47 HSYNC PC5 19 46 EXLC PC4 20 45 XLC PC3 21 44 PE0/INT0 PC2 22 43 PE1/INT1 PC1 23 42 PE2/AN0 PC0 24 41 PE3/AN1 PD7/EC 25 40 PE4/AN2 PD6/RMC 26 39 PE5/AN3 PD5/ACI 27 38 PE6/PWM PD4/HSI 28 37 PE7/TO RST PD3/SI 29 36 PD2/SO 30 35 EXTAL PD1/SCK 31 34 XTAL VSS 32 33 PD0/INT2 Note) 1. Vpp (Pin 63) is always connected to VDD. 2. Vss (Pins 32 and 62) are both connected to GND. 3. MP (Pin 61) is always connected to GND. –3– CXP853P40A PF2/PWM2 PF1/PWM1 PF0/PWM0 MP Vpp VDD VSS PA7 PA6 PA5 PA4 PA3 PA2 Pin Assignment 2 (Top View) 64 pin QFP Package 64 63 62 61 60 59 58 57 56 55 54 53 52 1 51 PA0 2 50 PF4/PWM4/SCL0 PB7 3 49 PF5/PWM5/SCL1 PB6 4 48 PF6/PWM6/SDA0 PB5 5 47 PF7/PWM7/SDA1 PB4 6 46 BLK PB3 7 45 R PB2 8 44 G PB1 9 43 B PB0 10 42 VSYNC PC7 11 41 HSYNC PC6 12 40 EXLC PC5 13 39 XLC PC4 14 38 PE0/INT0 PC3 15 37 PE1/INT1 PC2 16 36 PE2/AN0 PC1 17 35 PE3/AN1 PA1 PF3/PWM3 PC0 18 34 PE4/AN2 PD7/EC 19 33 PE5/AN3 PE6/PWM RST PE7/TO XTAL EXTAL PD0/INT2 VSS PD1/SCK PD3/SI PD2/SO PD4/HSI PD5/ACI PD6/RMC 20 21 22 23 24 25 26 27 28 29 30 31 32 Note) 1. Vpp (Pin 56) is always connected to VDD. 2. Vss (Pins 26 and 58) are both connected to GND. 3. MP (Pin 55) is always connected to GND. –4– CXP853P40A Pin Description Symbol I/O Description PA0 to PA5 I/O PA6/VSYNC I/O/Input (Port A) Single bit selectable 8-bit I/O port. (8 pins) CRT display vertical synchronization signal input pin. PA7/HSYNC I/O/Input CRT display horizontal synchronization signal input pin. PB0 to PB7 I/O (Port B) Single bit selectable 8-bit I/O port. (8 pins) PC0 to PC7 I/O (Port C) Single bit selectable 8-bit I/O port. (8 pins) PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4/HSI I/O/Input PD5/ACI I/O/Input PD6/RMC I/O/Input Remote control receiver circuit input pin. PD7/EC I/O/Input External event timer/counter input pin. PE0/INT0 PE1/INT1 Input/Input Input pin for external interrupt request. Active on falling edge. (2 pins) Input pin for external interrupt request. Active on falling edge. Serial clock I/O pin. (Port D) Single bit selectable Serial data output pin. 8-bit I/Oport. Serial data input pin. 12mA sink current drive possible. HSYNC counter input pin. (8 pins) Power supply frequency counter input pin. (Port E) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 pins) PE2/AN0 to PE5/AN3 Input/Input PE6/PWM Output/Output PE7/TO Output/Output PF0/PWM0 to PF3/PWM3 Output/Output PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 Output/Output/ I/O PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Output/Output/ I/O (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits middle voltage tolerance (12V), upper 4 bits 5V suppression. (8 pins) R, G, B, I, YS, YM Output CRT display 6-bit output pin. Analog input pin for A/D converter. (4 pins) 14-bit PWM output pin. (CMOS output) Square wave output for timer 1. (50% duty cycle) –5– 8-bit PWM output pin. (8 pins) I2C bus interface transfer clock I/O pin. I2C bus interface transfer data I/O pin. CXP853P40A Symbol I/O Description EXLC Input XLC Output EXTAL Input XTAL Output RST I/O "L" level active system reset. This pin also acts as an I/O pin during power up. While internal power-on reset function is talking place a "L" level is output. (Mask option) MP Input Test mode input pin. Must be connected to GND. CRT display clock oscillator I/O pin. Oscillator frequency is determined by external L, C circuit. System clock oscillator crystal connection pin. When using an external clock, input to EXTAL pin and leave XTAL pin open. VDD Positive supply voltage pin. Vpp Positive power supply pin for incorporated PROM writing. Connect to VDD for normal operation. Vss GND. Both Vss pins should be connected to common GND. –6– CXP853P40A Input/Output Circuit Formats for Pins Pin Circuit format Port A Port B Port C PA0 to PA5 PB0 to PB7 PC0 to PC7 When reset AAAA AAAA AAAA AAAA AA AA AA AA Port A data Port B data Port C data Port A I/O direction Port B I/O direction Port C I/O direction IP Data bus RD (Port A, B, C) 22 pins Port A AAAA AAAA AAAA Port A I/O direction PA6/VSYNC PA7/HSYNC Input protection circuit AA AA AA AA Port A data IP Data bus RD (Port A) VSYNC HSYNC Hi-Z Input protection circuit Hi-Z AAAA Schmitt input Input polarity 2 pins Port D PD0/INT2 PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC AAAA AAAA AAAA Port D data Port D I/O direction AA AA AA AA Large current source 12mA IP Data bus RD (Port D) INT2, SI, HSI, ACI, RMC, EC Schmitt input 6 pins –7– Hi-Z CXP853P40A Pin Circuit format When reset Port D SCK or SO Output enable AAAA AAAA PD1/SCK PD2/SO AA AA AA AA Large current source 12mA Port D data IP Port D I/O direction Schmitt input Data bus Hi-Z RD (Port D) SCK only 2 pins Port E PE0/INT0 PE1/INT1 AAAA AA AA AA AAAA Schmitt input (To interrupt circuit) IP 2 pins Port E Hi-Z Data bus RD (Port E) Input multiplexer PE2/AN0 to PE5/AN3 IP To A/D converter Hi-Z Data bus RD (Port E) 4 pins Port E TO, PWM PE6/PWM PE7/TO AAAAA AAAAA AA Port E data Port E selection 2 pins –8– High level CXP853P40A Circuit format Pin When reset Port F PF0/PWM0 to PF3/PWM3 AAAAA AAAAA AAAAA AA AA AA AA PWM 12V voltage torelance Port F data Large current source 12mA Port F selection 4 pins Port F SCL, SDA PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Large current source 12mA I2C output enable AAAAA AAAAA AAAAA PWM Port F data R G B I YS YM 6 pins EXLC XLC 2 pins A A Hi-Z IP Port F selection Schmitt input SCL, SDA (To I2C circuit) 4 pins BUS SW To other I2C pins AAAA AAAA AA AA R, G, B, I, YS, YM Output polarity To output polarity register Writing data to port register brings output from high impedance to active AA A AAA AA AA AA AA EXLC Hi-Z IP IP XLC –9– Hi-Z Oscillator control Oscillation halted CRT display clock CXP853P40A Pin EXTAL XTAL Circuit format AA AA AA AA EXTAL When reset • Diagram indicates circuit composition during oscillation IP • Feedback resistor is disconnected during stop Oscillation XTAL 2 pins RST 1 pin AA AA Mask option OP Pull-up resistor Schmitt input Low level From power-on reset circuit (Mask option) – 10 – CXP853P40A Absolute Maximum Ratings Item Supply voltage (Vss = 0V reference) Symbol Ratings Unit VDD –0.3 to +7.0 V Vpp V Remarks Input voltage VIN –0.3 to +13.0 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V Medium voltage tolerance output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Excludes large current output Large current output∗2 Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 1000 mW SDIP 600 mW QFP Low level output current Incorporated PROM V Pins PF0 to PF3 ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current drivetransistor for the PD and PF ports is a N-ch transistor. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 11 – CXP853P40A Recommended Operating Conditions Item Symbol VDD Supply voltage Min. Max. Unit 4.5 5.5 V Guaranteed range during operation 3.5 5.5 V Guaranteed range for low speed data∗1 2.5 5.5 V Vpp = VDD Vpp High level input voltage Low level input voltage Operating temperature (Vss = 0V reference) V Remarks Guaranteed data hold operation range during stop ∗5 VIH 0.7VDD VDD V VIHS 0.8VDD VDD V I2C Schmitt input included∗2 CMOS Schmitt input∗3 VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗4 VIL 0 0.3VDD V VILS 0 0.2VDD V I2C Schmitt input included∗2 CMOS Schmitt input∗3 VILEX –0.3 0.4 V EXTAL pin∗4 Topr –10 +75 °C ∗1 Rating for 1/16 frequency mode and sleep mode. ∗2 Normal input port (All pins of PA, PB, PC, PE2 to PE5), PF4 to PF7 pins. ∗3 Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HSI, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1, HSYNC, VSYNC, RST pins. ∗4 It specifies only when the external clock is input. ∗5 Vpp and VDD should be set to the same voltage. – 12 – CXP853P40A Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage (Ta = –10 to +75°C, Vss = 0V reference) Symbol VOH VOL IIHE Input current Pin Condition PA to PD, PE6, PE7, VDD = 4.5V, IOH = –0.5mA R, G, B, I, YS, YM VDD = 4.5V, IOH = –1.2mA Min. Typ. Max. Unit 4.0 V 3.5 V PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, I, YS, YM, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, RST 0.4 V 0.6 V PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V EXTAL IIHL VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA IILR RST VDD = 5.5V, VIL = 0.4V I/O leakage current IIZ PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (N-ch Tr off case) PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA ILOH PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA I2C bus switch connection impedance (output Tr off case) RBS SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω IDD VDD∗1 Supply current Input capacitance ∗1 ∗2 ∗3 ∗4 Operating mode (1/2, 1/4 clock rate) 4MHz, 8MHz crystal oscillator (C1 = C2 = 22pF) All output pins open IDDSL Sleep mode IDDST Stop mode∗4 CIN Pins other than VDD and Vss 1MHz clock 0V other than the measure pins Rating applies only if OSD oscillator is halted. Oscillator clock 4MHz version Oscillator clock 8MHz version This device does not enter the stop mode. – 13 – 11∗2 30∗2 mA — 17∗3 40∗3 0.6∗2 0.8∗3 3∗2 3∗3 mA — — µA 10 20 pF CXP853P40A AC Characteristics (1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency fC System clock input pulse width tXL, tXH System clock rise and fall times tCR, tCF tEH, tEL tER, tEF Event counter input clock pulse widtth Event counter input clock rise and fall times Pin Condition Min. 3.5∗2 7∗3 XTAL EXTAL Fig. 1, Fig. 2 EXTAL Fig. 1, Fig. 2 External clock drive EXTAL Fig 1, Fig 2 External clock drive EC Fig. 3 EC Fig. 3 Max. 4.5 9 100∗2 50∗3 Unit MHz ns 200 tsys + 50∗1 ns ns 20 ms ∗1 tsys indicates one of three values according to the contents of the clock control register (address : 00FEH) upper 2 bits (CPU clock selection) tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") ∗2 Oscillator clock 4MHz version ∗3 Oscillator clock 8MHz version 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA Crystal oscillator Ceramic oscillator EXTAL External clock EXTAL XTAL C1 C2 XTAL OPEN Fig. 2. Clock applied condition 0.8VDD EC 0.2VDD tEH tEF tEL Fig. 3. Event count clock timing – 14 – tER CXP853P40A (2) Serial transfer Item SCK cycle time SCK High and Low level widths (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin tKCY SCK tKH tKL SCK Condition Min. Input mode Output mode tSIK SI SI input hold time (referenced to SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO ns 8000/fc'∗1 ns ns 400 ns 4000/fc' – 50∗1 ns SCK output mode 100 ns SCK input mode 200 ns SCK output mode 200 ns SCK input mode 100 SCK input mode SCK output mode 200 ns 100 ns Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. ∗1 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 tKCY tKL tKH 0.8VDD SCK 0.2VDD tKSI tSIK 0.8VDD Input data SI Unit 1000 SCK input mode SCK output mode SI input setup time (referenced to SCK ↑) Max. 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD Fig. 4. Serial transfer timing – 15 – CXP853P40A (3) Interrupt, Reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol External interrupt High and Low level widths Reset input low level width tIH tIL tRSL Pin Condition Min. Unit 1 µs 8/fc' ∗1 µs INT0 to INT2 RST Max. ∗1 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 tIH tIL 0.8VDD INT0 to INT2 (falling edge) 0.2VDD Fig. 5. Interrupt input timing tRSL RST 0.2VDD Fig. 6. RST input timing (4) Power-on reset Power-on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Power supply rise time Power supply cutt-off time tR tOFF Pin VDD Condition Power-on reset Repeated power-on reset Min. Max. Unit 0.05 50 ms 1 ms 4.5V VDD 0.2V 0.2V tR tOFF The power supply should rise smoothly. Fig. 7. Power-on reset – 16 – CXP853P40A (5) A/D converter characteristics Item Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Max. Unit Resolution 8 Bits Linearity error ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pin Condition Ta = 25°C VDD = 5.0V Vss = 0V Min. Typ. –10 70 150 mV 4930 5050 5120 mV 160/fc' ∗3 12/fc' ∗3 AN0 to AN3 0 µs µs VDD V Digital conversion value FFH FEH ∗1 VZT: Digital conversion values change between 00H←→01H. ∗2 VFT: Digital conversion values change between FEH←→FFH. ∗3 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 Linearity error 01H 00H VZT Analog input VFT Fig. 8. Definitions for A/D converter terms – 17 – CXP853P40A (6) I2C bus timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 Since for part of data hold time SCL rise time (max: 300ns) is not considered , allow at least 300ns. SDA tBUF tR tF tHD; STA SCL tHD; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STA tSU; STO P Fig. 9. I2C bus transfer data timing I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 10. I2C device recommended circuit • A pull-up resistor (RP) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 18 – CXP853P40A (7) OSD (On Screen Display) timing Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Condiiton Shadow Existent Shadow Non-existent Min. Max. Min. Max. 7∗1 14∗2 4 11∗1 16∗2 Unit OSD clock frequency fOSC EXLC XLC Fig. 12 4 HSYNC pulse width tHWD HSYNC Fig. 11 1.2 HSYNC afterwrite rise and fall times tHCG HSYNC Fig. 11 200 200 ns VSYNC afterwrite rise and fall times tVCG VSYNC Fig. 11 1.0 1.0 µs 1.2 ∗1 Oscillator clock 4MHz version ∗2 Oscillator clock 8MHz version tHCG tHWD 0.8VDD HSYNC For OPOL register (01FAH) bit 7 at “0” 0.2VDD tVCG 0.8VDD VSYNC For OPOL register (01FAH) bit 6 at “0” 0.2VDD Fig. 11. OSD timing EXLC XLC L C2 C1 Fig. 12. LC oscillator circuit connection – 19 – MHz µs CXP853P40A Supplement AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) EXTAL XTAL Rd XTAL Rd C2 C1 C1 C2 Fig. 13. Recommended oscillation circuit Manufacturer MURATA MFG CO., LTD. Model fc (MHz) CSA4.00MG 4.00 CSA4.19MG 4.19 CSA8.00MTZ 8.00 CST4.00MGW∗ CST4.19MGW∗ CST8.00MTW∗ C1 (pF) C2 (pF) Rd (Ω) Circuit Example (i) 30 30 0 4.00 (ii) 4.19 8.00 4.00 RIVER ELETEC CORPORATION HC-49/U03 4.19 12 12 0 (i) 27 27 0 (i) 8.00 4.00 KINSEKI LTD. HC-49/U(-S) 4.19 8.00 ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Product List Option item CXP853P40AS-2CXP853P40AQ-2- Mask CXP853P40AS-3CXP853P40AQ-3- 64-pin plastic SDIP/QFP 64-pin plastic SDIP/QFP 64-pin plastic SDIP/QFP 24K/32K/40K bytes PROM 40K bytes PROM 40K bytes Reset pin pull-up resistor Existent/Non-existent Existent Existent Power-on reset circuit Existent/Non-existent Existent Existent Package PROM capacitance Font data Oscillator clock User specified User specified (PROM)∗1 User specified (PROM)∗1 4MHz/8MHz 4MHz 8MHz ∗1 The font data for the one-time PROM version is operated in the same way as the program writing. – 20 – CXP853P40A IDD vs. VDD IDD vs. VDD (fC = 4MHz, Ta = 25°C, Typical) (fC = 8MHz, Ta = 25°C, Typical) 15 20 1/2 frequency mode 10 10 1/2 frequency mode 1/4 frequency mode IDD – Supply current [mA] 1/16 frequency mode 1 Sleep mode 0.1 1/16 frequency mode 1 Sleep mode 0.1 2 3 4 5 VDD – Supply voltage [V] 2 6 IDD vs. fC 3 4 5 VDD – Supply voltage [V] 6 Parameter curve for OSD oscillator L vs. C (Analytically calculated value) (VDD = 5V, Ta = 25°C, Typical) 100 20 1/2 frequency mode 1/4 frequency mode 10 1/16 frequency mode L – Inductance [µH] 15 IDD – Supply current [mA] IDD – Supply current [mA] 1/4 frequency mode 5.0MHz 6.5MHz 10 5 13.0MHz Sleep mode 0 1 5 10 fC – System clock [MHz] fOSC = 1 0 Fig. 14. Characteristic curves – 21 – 1 2π √ LC C = C1//C2 50 C1, C2 – Capacitance [pF] 100 CXP853P40A Package Outline Unit: mm + 0.1 0.05 0.25 – 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 19.05 + 0.3 17.1 – 0.1 33 1 0° to 15° 32 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP064-P-0750 LEAD MATERIAL 42 ALLOY PACKAGE MASS 8.6g JEDEC CODE 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 22 –