CXP87940/87948 CMOS 8-bit Single Chip Microcomputer Description The CXP87940/87948 is a CMOS 8-bit single chip microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control reception circuit, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. Also the CXP87940/87948 provides sleep/stop functions which enable to lower power consumption. 100 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V) 122µs at 32kHz operation (2.7V to 5.5V) • Incorporated ROM capacity 40K bytes (CXP87940), 48K bytes (CXP87948) • Incorporated RAM capacity 1376 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0µs at 16MHz) — Serial Interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz) DA gate pulse output: 13 bits, 4 channels — Servo input control Capstan FG, drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits — VISS/VASS circuit Pulse duty auto detection circuit — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP • Piggyback/evaluator CXP87800 100-pin ceramic PQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X01-PS CKOUT ADJ PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 PWM RMC CFG DFG DPG PBCTL SYNC0 SYNC1 EXI0 EXI1 TO/DDO FIFO RAM FIFO AVss 12 BIT PWM GENERATOR CH1 12 BIT PWM GENERATOR CH0 14 BIT PWM GENERATOR VISS/VASS FIFO SERVO INPUT CONTROL REMOCON INPUT CTL DRUM CAPSTAN VSYNC SEPARATOR 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 SERIAL INTERFACE UNIT (CH1) SI1 SO1 SCK1 EC SERIAL INTERFACE UNIT (CH0) CS0 SI0 SO0 SCK0 A/D CONVERTER AVDD SERIAL INTERFACE UNIT (CH2) 12 4 2 2 3 2 2 2 INT1/NMI INT2 2 XTAL RST MP 32kHz TIMER/COUNTER PRESCALER/ TIME BASE TIMER RAM 1376 BYTES CH1 REALTIME PULSE GENERATOR CH0 VDD CLOCK GENERATOR/ SYSTEM CONTROL 5 RAM FIFO ROM 40K/48K BYTES SPC700 CPU CORE A A AA 19 PROGRAMMABLE PATTERN GENERATOR FRC CAPTURE UNIT INTERRUPT CONTROLLER AVREF SCL0 SCL1 SDA0 SDA1 AN0 to AN11 2 TEX PPO0 to PPO18 PC0 to PC7 PD0 to PD7 PE0 to PE1 PE2 to PE7 8 8 2 6 PH0 to PH7 8 8 PJ0 to PJ7 PI1 to PI7 PG0 to PG7 8 7 PF4 to PF7 4 PF0 to PF3 PB0 to PB7 8 4 PA0 to PA7 8 PORT B TX EXTAL RTO3 to RTO7 PORT A PORT C PORT D PORT E PORT F PORT G PORT H PORT I –2– PORT J Block Diagram CXP87940/87948 Vss INT0 CXP87940/87948 PI5/SCK1 PI4/INT1/NMI PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PI6/SO1 PB4/PPO12 2 79 PI7/SI1 PB3/PPO11 3 78 PE0/INT0/CKOUT PB2/PPO10 4 77 PE1/EC/INT2 PB1/PPO9 5 76 PE2/PWM0 PB0/PPO8 6 75 PE3/PWM1 PC7/RTO7 7 74 PE4/DAA0 PC6/RTO6 8 73 PE5/DAA1 PC5/RTO5 9 72 PE6/DAB0 PC4/RTO4 10 71 PE7/DAB1 PC3/RTO3 11 70 PG0/CFG PC2/PPO18 12 69 PG1/DFG PC1/PPO17 13 68 PG2/DPG PC0/PPO16 14 67 PG3/PBCTL PJ7 15 66 PG4/SYNC0 PJ6 16 65 PG5/SYNC1 PJ5 17 64 PG6/EXI0 PJ4 18 63 PG7/EXI1 PJ3 19 62 AN0 PJ2 20 61 AN1 PJ1 21 60 AN2 PJ0 22 59 AN3 PD7 23 58 PF0/AN4 PD6 24 57 PF1/AN5 PD5 25 56 PF2/AN6 PD4 26 55 PF3/AN7 PD3/SDA1 27 54 AVDD PD2/SDA0 28 53 AVREF PD1/SCL1 29 52 AVSS PD0/SCL0 30 51 PF4/AN8 PF5/AN9 PF6/AN10 PF7/AN11 SO0 SCK0 SI0 CS0 XTAL EXTAL VSS RST MP PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –3– CXP87940/87948 Pin Description Symbol I/O PA0/PPO0 to PA7/PPO7 Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PB0/PPO8 to PB7/PPO15 Output/ Real-time output (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PC0/PPO16 to PC2/PPO18 I/O/ Real-time output PC3/RTO3 to PC7/RTO7 I/O/ Real-time output PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1 I/O PD4 to PD7 PE0/INT0/ CKOUT Description (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG) output. Functions as high-precision real-time pulse output port. PB0 and PB2 can be 3-state controlled with PPG. (19 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. PC3 can be 3-state controlled with RTG. (5 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits for upper 4 bits. Can drive 12mA sink current. Lower 4-bit output is N-ch open drain. (8 pins) Input to request external interruption. Active at the falling edge. Input/Input/Output (Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins) Serial clock (CH2) I/O. (2 pins) Serial data (CH2) I/O. (2 pins) System clock frequency dividing output. External event Input to request external interruption. input for Active at the falling edge. timer/counter. PE1/EC/INT2 Input/Input/Input PE2/PWM0 Output/Output PE3/PWM1 Output/Output PE4/DAA0 Output/Output PE5/DAA1 Output/Output PE6/DAB0 Output/Output PE7/DAB1 Output/Output AN0 to AN3 Input PF0/AN4 to PF3/AN7 Input/Input PF4/AN8 to PF7/AN11 Output/Input (Port F) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pin. (8 pins) SCK0 I/O Serial clock (CH0) I/O. SO0 Ouput Serial data (CH0) output. SI0 Input Serial data (CH0) input. CS0 Input Serial chip select (CH0) input. PWM outputs. (2 pins) DA gate pulse outputs. (4 pins) Analog inputs to A/D converter. (12 pins) –4– CXP87940/87948 Symbol I/O Description PG0/CFG Input/Input Capstan FG input. PG1/DFG Input/Input Drum FG input. PG2/DPG Input/Input Drum PG input. PG3/PBCTL Input/Input PG4/SYNC0 Input/Input PG5/SYNC1 Input/Input PG6/EXI0 Input/Input PG7/EXI1 Input/Input (Port G) 8-bit input port. (8 pins) Playback CTL pulse input. External event input for timer/counter. Composite sync signal input. (2 pins) External input to FRC capture unit. (2 pins) (Port H) 8-bit output port. N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) PH0 to PH7 Output PI1/RMC I/O/Input Remote control reception circuit input. PI2/PWM I/O/Output 14-bit PWM output. PI3/TO/ DDO/ADJ I/O/Output/ Output/Output PI4/INT1/ NMI I/O/Input/Input PI5/SCK1 I/O/I/O PI6/SO1 I/O/Output Serial data (CH1) output. PI7/SI1 I/O/Input Serial data (CH1) input. PJ0 to PJ7 I/O EXTAL Input XTAL Output TEX Input TX Output Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz crystal oscillator is inserted between TEX and TX. When used as event input, connect the clock source to TEX and leave TX open. RST Input System reset; active at Low level. MP Input Test mode input. Always connect to GND. Timer/counter, CTL duty detection, 32kHz oscillation adjustment output. Input to request external interruption and non-maskable interruption. Active at the falling edge. Serial clock (CH1) I/O. (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL and input the opposite phase clock to XTAL . Positive power supply of A/D converter. AVDD AVREF (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Input Reference voltage input of A/D converter. AVss GND of A/D converter. VDD Positive power supply. Connect VDD pin to VDD. NC No connected. Connect to VDD in normal operation. Vss GND. Connect both Vss pins to GND. –5– CXP87940/87948 Input/Output Circuit Formats for Pins Pin When reset Circuit format Port A Port B PA0 /PPO0 to PA7/PPO7 PB4/PPO12 to PB7/PPO15 AA AA AAAA PPO data Ports A, B data Hi-Z Output becomes active from high impedance by data writing to port register. Data bus RD (Ports A, B) 12 pins PB0/PPO8 PB2/PPO10 AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA PPO8, PPO10 data PB0, PB2 data Hi-Z Data bus RD (Port B) 2 pins PPO9, PPO11 data PPG control status register bit 0 3-state control selection Output becomes active from high impedance by data writing to port register. AA AA PPO9, PPO11 data PB1/PPO9 PB3/PPO11 PB1, PB3 data Data bus RD (Port B) Output becomes active from high impedance by data writing to port register. 2 pins –6– Hi-Z CXP87940/87948 Pin When reset Circuit format Port C PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7 AA AA AA AA AAA AAA AAA PPO, RTO data Input protection circuit Port C data Hi-Z IP Port C direction “0” when reset Data bus RD (Port C) 6 pins AAA AAA AAA AAAAA AAAAA AAAAA AAA AAA AAA RTO3 data PC3 data PC3/RTO3 PC3 direction “0” when reset AA AA AA AA Hi-Z AA AA AA AA Hi-Z IP Data bus RD (Port C) RTO4 data 1 pin RTG interruption control register bit 7 3-state control selection “0” when reset RTO4 data PC4 data PC4/RTO4 PC4 direction “0” when reset IP Data bus RD (PortC) RTO data is OR-gate data of CH0 and CH1. 1 pin –7– CXP87940/87948 Pin When reset Circuit format Port D A SCL, SDA AAAA AAAA ∗ Serial interface CH2 output enable PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1 Port D data AA IP Data bus Schmitt input RD (Port D) SCL, SDA (Serial interface CH2 circuit) Hi-Z BUS SW To another serial CH2 pin ∗ Large current 12mA 4 pins Port D PD4 to PD7 AAAA AAAA AAAA ∗ Port D data AA AA AA AA Hi-Z IP Port D direction “0” when reset Data bus 4 pins ∗ Large current 12mA RD (Port D) Port E ESL0 Port E selection ESL1 PS1 PS2 PS3 PE0/INT0/ CKOUT AAA AAA 01 10 MPX 11 Data bus RD (Port E) 1 pin Interruption circuit –8– AA AA AA AA IP Hi-Z CXP87940/87948 Pin When reset Circuit format Port E AAA Data bus IP PE1/EC/INT2 Hi-Z RD (Port E) Interruption circuit/ event counter 1 pin Port E AA AA AAAA AA AAAA AA AAAA AA DA gate output, PWM output MPX Hi-Z control PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Port E data Port/DA output selection Hi-Z “0” when reset Data bus 4 pins RD (Port E) Port E AA AA AAAA AA AAAA AAAA AA DA gate output MPX Hi-Z control PE6/DAB0 PE7/DAB1 Port E data Port/DA output selection High level “1” when reset Data bus 2 pins AN0 to AN3 RD (Port E) AAAA Input multiplexer IP 4 pins –9– Hi-Z A/D converter CXP87940/87948 Pin When reset Circuit format AAAA Port F Input multiplexer PF0/AN4 to PF3/AN7 IP A/D converter Hi-Z Data bus 4 pins RD (Port F) AAAA AAAAAAAA AAAA Port F PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 IP Port/AD selection “0” when reset 4 pins AAAA AA A/D converter Schmitt input Servo input IP Data bus Hi-Z RD (Port G) Note) For PG4/SYNC0, PG5/SYNC1, CMOS Schmitt input and TTL Schmitt input can be selected with the mask option. Port H AAAA ∗ Port H data Data bus 8 pins Hi-Z Input multiplexer 8 pins PH0 to PH7 AA AA AA AA RD (Port H) – 10 – AA AA ∗ Large current 12mA Medium drive voltage 12V Hi-Z CXP87940/87948 Pin AAA AAAAA AA AAAA AA AA AAAA AA A AAAA A AAA AA AAA AA AAA AA AA Circuit format Port I When reset Port I function selection “0” when reset PI2...14-bit PWM PI3...Timer/counter, CTL duty detection circuit, 32kHz timer PI2/PWM PI3/TO/ DDO/ADJ MPX Port I data Port I direction Hi-Z IP “0” when reset Data bus 2 pins RD (Port I) Port I PI1/RMC PI4/INT1/NMI PI7/SI1 Port I data Port I direction “0” when reset IP Hi-Z Data bus RD (Port I) Schmitt input PI1...Remote control circuit PI4...Interruption circuit PI7...Serial interface CH1 3 pins AAAA AAAA AA AAAA AA A AAAA AA AAA A AAAA AAA A AAA AAA AAA A AAA A AA A Port I Port I function selection PI5/SCK1 PI6/SO1 “0” when reset Serial interface CH1 MPX Port I data MPX Port I direction Hi-Z IP “0” when reset Data bus 2 pins RD (Port I) Serial interface CH1 PI6 is not Schmitt input. Port J Port J data Port J direction PJ0 to PJ7 “0” when reset IP Data bus RD (PortJ) Edge detection Standby release Data bus 8 pins RD (Port J direction) – 11 – Hi-Z CXP87940/87948 Pin When reset Circuit format AA A AAA CS0 SI0 Schmitt input 2 pins AA AA SO0 SO0 Serial interface CH0 1 pin SO0 output enable SCK0 SCK0 Serial interface CH0 SCK0 output enable Schmitt input 1 pin 2 pins TEX TX 2 pins RST AA AA AA AA AA AA AA AA EXTAL XTAL TEX AA AA Hi-Z Hi-Z • Shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop mode and XTAL becomes High level. AA AA 32kHz timer/counter IP TX AA AA AA AA • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level. Oscillation Oscillation Pull-up resistor Mask option Schmitt input OP 1 pin AA AA AA AA IP SCK0 EXTAL XTAL Hi-Z CS0 Serial interface CH0 SIO IP IP – 12 – Low level CXP87940/87948 Absolute Maximum Ratings Item (Vss = 0V reference) Symbol VDD AVDD Supply voltage AVSS AVREF Symbol Unit –0.3 to +7.0 AVss to +7.0∗1 V –0.3 to +0.3 AVss to +7.0∗1 V Unit V V Input voltage VIN Output voltage VOUT –0.3 to +7.0∗2 –0.3 to +7.0∗2 Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA –50 mA Total of output pins IOL 15 mA Ports excluding large current output (value per pin) IOLC 20 mA Large current output port (value per pin∗3) Low level total output current ∑IOL 130 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW High level total output current ∑IOH V V Low level output current Port H pin ∗1 AVDD and AVREF should not exceed VDD + 0.3V. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The large current output ports are the pins of the port D (PD) and Port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 13 – CXP87940/87948 Recommended Operating Conditions Item Supply voltage Analog voltage High level input voltage Symbol (Vss = 0V reference) Min. Max. Unit Remarks 4.5 5.5 V Guaranteed operation range for 1/2 and 1/4 frequency dividing modes 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing mode or during sleep mode 2.7 5.5 V Guaranteed operation range by TEX clock 2.0 5.5 V 4.5 5.5 V VIH 0.7VDD VDD V VIHS 0.8VDD VDD V 5.5 V VIHTS 2.2 5.5 V CMOS Schmitt input∗7 TTL Schmitt input∗4 V EXTAL pin∗5 and TEX pin∗6 VDD AVDD VIHEX VDD – 0.4 VDD + 0.3 VIL 0 0.3VDD V VILS 0 0.2VDD V VILTS 0 0.8 V VILEX –0.3 0.4 V Operating temperature Topr –20 +75 °C Low level input voltage ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 Guaranteed data hold range during stop mode ∗1 Includes the serial CH2 input∗2 CMOS Schmitt input∗3 and PE0/INT0 pin Includes the serial CH2 input∗2 CMOS Schmitt input∗3 and PE0/INT0 pin TTL Schmitt input∗4 EXTAL pin∗5 and TEX pin∗6 AVDD and VDD should be set to the same voltage. Normal input port (PC, PD4 to PD7, PF0 to PF3, PG, PI and PJ), MP pin SCK0, RST, EC/INT2, RMC, INT1/NMI, SCK1 and SI1 PG4 and PG5 (When TTL Schmitt input is selected with mask option) Specifies only when the external clock is input. Specifies only when the external event count clock is input. CS0, SI0, and PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option.) – 14 – CXP87940/87948 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL IIHE Pins IIHT Typ. Max. Unit 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PD, PH VDD = 4.5V, IOL = 12.0mA 1.5 V PD0 to PD3 (SCL0, CSL1 SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 6.0mA 0.6 V EXTAL VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA TEX IILR RST∗1 VDD = 5.5V, VIL = 0.4V IIZ PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA PH VDD = 5.5V VOH = 12V 50 µA PD0 to PD3 VDD = 5.5V VOH = 5.5V 10 µA 120 Ω Open drain output leakage ILOH current (in N-CH Tr off state) Serial interface CH2 bus switch connection impedance (in output Tr off state) Min. VDD = 4.5V, IOH = –0.5mA IILT I/O leakage current Conditions PA to PC, PD4 to PD7, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 IILE Input current (Ta = –20 to +75°C, Vss = 0V reference) RBS VDD = 4.5V SCL0: SCL1 VSCL0 = VSCL1 = 2.25V SDA0: SDA1 VSDA0 = VSDA1 = 2.25V – 15 – CXP87940/87948 Item Symbol Pins Conditions Min. Typ. Max. Unit VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 16pF) 36 50 mA VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) 60 100 µA 2.8 8 mA 10 30 µA 10 µA 20 pF 1/2 frequency dividing clock operation IDD1 IDD2 Supply current∗2 Input capacity Sleep mode IDDS1 VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 16pF) IDDS2 VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) IDDS3 Stop mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation CIN PC, PD, PE0, PE1, PF, PG, PI1 to PI7, PJ, CS0, Clock 1MHz SI0, SCK0, 0V for all pins excluding measured AN0 to AN3, pins EXTAL, XTAL, TEX, TX, MP, RST 10 ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When all output pins are open. – 16 – CXP87940/87948 AC Characteristics (1) Clock timing Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins Min. Conditions System clock frequency fC XTAL Fig. 1, EXTAL Fig. 2 1 System clock input pulse width tXL, tXH XTAL Fig. 1, EXTAL Fig. 2 (External clock drive) 28 System clock input rise and fall times XTAL Fig. 1, Fig. 2 EXTAL (External clock drive) Event count input clock rise and fall times tCR, tCF tEH, tEL tER, tEF System clock frequency fC Event count input clock pulse width tTL, tTH tTR, tTF Event count input clock pulse width Event count input clock rise and fall times Typ. Max. Unit 16 MHz ns 200 4tsys∗1 EC Fig. 3 EC Fig. 3 TEX TX Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) TEX Fig. 3 TEX Fig. 3 ns ns 20 ns kHz 32.768 µs 10 20 ms ∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL C1 32kHz clock applied condition crystal oscillation External clock EXTAL XTAL C2 TEX XTAL TX C1 74HC04 C2 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR – 17 – CXP87940/87948 (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS0 ↑ → SCK0 floating delay time tDCSKF SCK0 Chip select transfer mode (SCK = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↓ → SO0 floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time Input mode SCK0 2tsys + 200 ns tKCY 16000/fc ns SCK0 High and Low level widths tKH tKL tsys + 100 ns SCK0 Output mode 8000/fc – 100 ns SI0 input setup time (for SCK0 ↑) SCK input mode SI0 –tsys + 100 ns tSIK 200 ns SI0 input hold time (for SCK0 ↑) SI0 2tsys + 100 ns tKSI 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode Input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 2tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 18 – CXP87940/87948 Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 19 – CXP87940/87948 Serial transfer (CH1) (SIO mode) Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin Condition tKCY SCK1 SCK1 High and Low level widths tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Max. Unit 2tsys + 200 ns Output mode 16000/fc ns Input mode tsys +100 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode SCK1 cycle time Min. Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing (SIO mode) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD – 20 – CXP87940/87948 Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Condition Min. ∗1 Typ. Max. Unit SO1 cycle time tLCY SO1 SI1 SI1 data setup time tLSU tLHD SI1 2 µs SI1 2 µs SI1 data hold time ∗1 104 µs tLCY is specified only when serial mode register (CH1) (SIOM1: 05FZH) lower 2 bits (SO1 clock selection) are set at 104µs. Note) The load of SO1 pin is 50pF + 1TTL. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY SO1 tLCY Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD Input data bit SI1 – 21 – 0.8VDD 0.2VDD CXP87940/87948 Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Item Pin Condition Min. Max. Unit 400 kHz SCL0, SCL1 clock frequency fSLC SCL0, SCL1 Bus-free time before starting transfer tBUF SDA0, SCL1 SDA0, SCL1 2.6 µs Hold time for starting transfer tHD; STA SDA0, SCL1 SDA1, SCL1 1.0 µs Clock Low level width SCL0, SCL1 1.0 µs Clock High level width tLOW tHIGH SCL0, SCL1 1.0 µs Setup time for repeated transfers tSU; STA SDA0, SCL0 SDA0, SCL1 1.0 µs Data hold time tHD; DAT SDA0, SCL0 SDA1, SCL1 0∗1 µs Data setup time tSU; DAT SDA0, SCL0 SDA1, SCL1 100 ns SDA0, SCL0, SDA1, SCL1 rise time tR SDA0, SCL0 SDA1, SCL1 300 ns SDA0, SCL0, SDA1, SCL1 fall time tF SDA0, SCL0 SDA1, SCL1 300 ns Setup time for transfer completion tSU; STO SDA0, SCL0 SDA1, SCL1 1.6 µs ∗1 The SCL0, SCL1 fall time (300ns Max.) is not included in the data hold time. Fig. 7. Serial transfer CH2 timing SDA0 SDA1 tBUF SCL0 SCL1 tR tF tHD; STA tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P Fig. 8. Device recommended circuit Device RS Device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) • A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 22 – CXP87940/87948 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Symbol Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error 160/fADC∗1 12/fADC∗1 tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage VIAN AVREF AN0 to AN11 IREF AVREF current IREFS µs AVDD – 0.5 AVDD V 0 AVREF V 1.0 mA 10 µA 0.6 Operation mode AVREF µs Sleep mode Stop mode 32kHz operation mode Fig. 9. Definitions of A/D converter terms ∗1 fADC indicates the below values due to the peripheral clock control register (PCC: 05F8H) bit 3 and clock control register (CLC: 00FEH) upper 2 bits. Digital conversion value FFH FEH PCC bit 3 0 (φ/2 selection) 1 (φ selection) CLC upper 2 bits Linearity error 01H 00H 00 (φ = fEX/2) fADC = fc/2 fADC = fc 01 (φ = fEX/4) fADC = fc/4 fADC = fc/2 11 (φ = fEX/16) fADC = fc/16 fADC = fc/8 Analog input – 23 – CXP87940/87948 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions External interruption High and Low level widths tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 Reset input Low level width tRSL RST Min. Max. Unit 1 µs 32/fc µs Fig. 10. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 11. RST input timing tRSL RST 0.2VDD (5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol tCFH tCFL DFG input tDFH High and Low level widths tDFL DPG minimum pulse width tDPW CFG input High and Low level widths DPG minimum removal time trem tCTH tCTL EXI input tEIH High and Low level widths tEIL PBCTL input High and Low level widths Pins Conditions Min. Max. Unit CFG 24tFRC + 200 ns DFG 16tFRC + 200 ns DPG 8tFRC + 200 ns DPG 16tFRC + 200 ns PBCTL tsys = 2000/fc 8tFRC + 200 + tsys ns EXI0 EXI1 tsys = 2000/fc 8tFRC + 200 + tsys ns Note 1) tFRC = 1000/fc [ns] Note 2) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) – 24 – CXP87940/87948 Fig. 12. Other timings tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD tDPW trem trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD – 25 – CXP87940/87948 Appendix Fig. 13. Recommended oscillation circuit for SPC 700 series AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA (i) EXTAL (ii) TEX XTAL Rd C1 Manufacturer RIVER ELETEC CO., LTD. Rd C2 Model C2 C1 fc (MHz) C1 (pF) C2 (pF) 8.00 10 10 5 5 8.00 16 16 10.00 16 16 12.00 12 12 16.00 12 12 32.768kHz 30 18 10.00 HC-49/U03 TX 12.00 Rd (Ω) Circuit example 0 (i) 0 (i) 470k (ii) 16.00 HC-49/U (-S) KINSEKI LTD. P3 Mask option table Content Item Reset pin pull-up resistor Input circuit format∗1 Non-existent Existent C-MOS Schmitt TTL Schmitt ∗1 The input circuit format can be selected for PG4/SYNC0 and PG5/SYNC1, respectively. – 26 – CXP87940/87948 Characteristics Curve IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5.0V, Ta = 25°C, Typical) 1/2 dividing mode 1/4 dividing mode 10 40 1/16 dividing mode Sleep mode 32kHz mode (instruction) 0.1 32kHz Sleep mode 0.01 (10µA) IDD – Supply current [mA] IDD – Supply current [mA] 30 1 20 1/2 dividing mode 10 1/4 dividing mode 1/16 dividing mode Sleep mode 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD – Supply voltage [V] 5.5 6.0 0 – 27 – 5 10 fc – System clock [MHz] 15 CXP87940/87948 Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE SONY CODE QFP-100P-L01 EIAJ CODE ∗QFP100-P-1420-A JEDEC CODE – 28 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g