CXP88100A CMOS 8-bit Single Chip Microcomputer Description The CXP88100 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP88132/88140/88152/88160/88216/88220/88224. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which cover various types of data. — 16-bit operation/multiplication and division/ boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Applicable EPROM LCC type 27C512 (Maximum 60Kbytes are available.) • Incorporated RAM capacity 1296 bytes • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 20.0µs/16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO (auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronous type, 1 channel — Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 8-pin, 21-stage programmable, RTG 5 pins, 2 channels — PWM/DA gate output PWM output 12 bits 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output 13 bits, 4 channels — Servo input control Capstan FG, drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO — Fluorescent display panel controller/driver Maximum 144 segments display possible Hardwave key scan function (Maximum 16 x 3 key matrix compatible.) — Tri-state output PPG output 1 pin, RTG output 1 pin, output 8 pins — Psendo HSYNC output function — High-speed head switching circuit • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic QFP Note) Mask option depends on the type of the CXP88100A. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95626-ST CXP88100A PI5/SCK0 PI4/INT1/NMI/CS0 PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PH2/KR2 PH1/KR1 PH0/KR0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Pin Assignment in Piggyback Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 78 VFDP PC5/RTO5 4 77 PD0/S0 PC4/RTO4 5 76 PD1/S1 PC3/RTO3 6 75 PD2/S2 PC2 7 74 PD3/S3 PC1 8 73 PD4/S4 PC0 9 72 PD5/S5 PA7/PPO7 10 71 PD6/S6 (HAMP) PA6/PPO6 11 A6 5 A8 70 PD7/S7 (ROTA) PA5/PPO5 12 A5 6 A9 69 T15/S8 (RF-PLS) PA4/PPO4 13 68 T14/S9 PA3/PPO3 14 67 T13/S10 PA2/PPO2 15 66 T12/S11 PA1/PPO1 16 65 T11/S12 PA0/PPO0/HGO 17 64 T10/S13 PF7 18 63 T9/S14 PF6/SI1 19 62 T8/S15 PF5/SO1 20 61 T7 PF4/SCK1 21 60 T6 PF3/AN7 22 59 T5 PF2/AN6 23 58 T4 PF1/AN5 24 57 T3 PF0/AN4 25 56 T2 AN3 26 55 T1 AN2 27 54 T0 PE0/INT0 (ENV-DET) 4 A4 2 3 1 A13 3 A14 PI7/SI0 PC6/RTO6 VDD 79 NC PI6/SO0 2 A15 80 PC7/RTO7 A12 1 A7 PB0 32 31 30 29 28 27 7 A3 NC 26 8 A2 A11 OE 25 9 A1 10 24 A10 A0 11 23 CE NC 12 22 D7 D0 13 21 D6 D5 D4 D3 NC GND D2 D1 14 15 16 17 18 19 20 28 53 AVSS 29 52 PE1/EC0/INT2 AVDD 30 51 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG EXTAL XTAL VSS RST MP PG2/DPG PG3/PBCTL/EC1 PG4/SYNC0/EC2 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AN1 AVREF Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –2– CXP88100A PI5/SCK0 PI4/INT1/NMI/CS0 PI3/TO/DDO/ADJ PI2/PWM PI1/RMC TEX TX VDD VSS NC PH2/KR2 PH1/KR1 PH0/KR0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Pin Assignment in Evaluator Mode 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 78 VFDP PC5/RTO5 4 77 PD0/S0 PC4/RTO4 5 76 PD1/S1 PC3/RTO3 6 75 PD2/S2 PC2 7 74 PD3/S3 PC1 8 73 PD4/S4 PC0 9 72 PD5/S5 PA7/PPO7 10 71 PD6/S6 (HAMP) PA6/PPO6 11 A6/D6 5 29 A8 70 PD7/S7 (ROTA) PA5/PPO5 12 A5/D5 6 28 A9 69 T15/S8 (RF-PLS) PA4/PPO4 13 A4/D4 7 27 A11 68 T14/S9 PA3/PPO3 14 A3/D3 8 26 NC 67 T13/S10 PA2/PPO2 15 HALT 66 T12/S11 PA1/PPO1 16 65 T11/S12 PA0/PPO0/HGO 17 64 T10/S13 PF7 18 63 T9/S14 PF6/SI1 19 62 T8/S15 PF5/SO1 20 61 T7 PF4/SCK1 21 60 T6 PF3/AN7 22 59 T5 PF2/AN6 23 58 T4 PF1/AN5 24 57 T3 PF0/AN4 25 56 T2 AN3 26 55 T1 AN2 27 54 T0 PE0/INT0 (ENV-DET) 3 4 A2/D2 2 A13 3 A14 PI7/SI0 PC6/RTO6 VDD 79 NC PI6/SO0 2 A15 80 PC7/RTO7 A12 1 A7/D7 PB0 1 32 31 30 25 9 A1/D1 A0/D0 23 11 NC RD A10 24 10 12 22 13 21 E/P I/T MON RST C1 C2 NC GND SYNC WR 14 15 16 17 18 19 20 28 53 AVSS 29 52 PE1/EC0/INT2 AVDD 30 51 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG EXTAL XTAL VSS RST MP PG2/DPG PG3/PBCTL/EC1 PG4/SYNC0/EC2 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AN1 AVREF Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –3– CXP88100A EPROM Read Timing (Ta=–20 to +75°C, VDD=4.5 to 5.5V, VSS=0V) Item Symbol Pin Address → data input delay time tACC A0 to A15 D0 to D7 Address → data hold time tIH A0 to A15 D0 to D7 Min. Max. Unit 75 ns 0 ns 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD D0 to D7 Input data 0.2VDD Products List Products Mask product Piggyback/evaluator product CXP CXP CXP CXP CXP CXP CXP 88132 88140 88152 88160 88216 88220 88224 CXP88100A-U01Q 100-pin plastic QFP 100-pin ceramic PQFP Option item Package ROM capacity Pull-up resistor for reset pin Input circuit format∗1 Pull-down resistor for high voltage drive pin 32K bytes 40K bytes 52K bytes 60K bytes 16K bytes 20K bytes 24K bytes EPROM 60Kbytes Existent/Non-existent Existent CMOS schmitt/TTL schmitt TTL schmitt Existent/Non-existent Existent∗2 ∗1 On PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin. ∗2 Not exist on PD0/S0 to PD7/S7. –4– CXP88100A Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking Pin 1 index LCC type EPROM Pin 1 marking Note) CPU probe Note) Evaluation cap should be connected to CPU probe. Package Outline Unit: mm 100PIN PQFP (CERAMIC) 18.7 PIN NO. 1 INDEX 16.3 ± 0.2 INDEX 100 81 81 80 PIN No. 1 INDEX 1 80 0.65 ± 0.05 1 100 0.3 ± 0.08 14.22 18.12 ± 0.2 1.27 ± 0.13 12.02 0.7 1.0 0.3 6.0 30 51 1.3 ± 0.3 51 31 50 9.48 11.66 30 50 31 0.45 15.58 ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL 0.50 ± 0.25 10.44 MAX –5– CERAMIC SONY CODE PQFP-100C-L01 LEAD TREATMENT GOLD PLATING EIAJ CODE AQFP100-C-0000-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 5.7g JEDEC CODE + 0.05 0.15 – 0.02 3.57 ± 0.36 24.7 22.3 ± 0.25 4.5