ICX055AL 1/3-inch CCD Image Sensor for CCIR B/W Camera For the availability of this product, please contact the sales office. Description The ICX055AL is an interline CCD solid-state image sensor suitable for CCIR 1/3-inch B/W video cameras. High sensitivity is achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system, and an electronic shutter with variable chargestorage time. 16 pin DIP (Plastic) Features • High sensitivity (+3dB compare with ICX045BLA) and low dark current • Continuous variable-speed shutter 1/50s (Typ.), 1/120s to 1/10000s • Low smear • Excellent antiblooming characteristics • Horizontal register: 5V drive • Reset gate: 5V drive AAAAA AAAAA AAAAA AAAAA Pin 1 V 7 Pin 9 H 1 14 30 Optical black position Device Structure (Top View) • Optical size: 1/3-inch format • Number of effective pixels: 500 (H) × 582 (V) approx. 290K pixels • Number of total pixels: 537 (H) × 597 (V) approx. 320K pixels • Interline CCD image sensor • Chip size: 6.00mm (H) × 4.96mm (V) • Unit cell size: 9.8µm (H) × 6.3µm (V) • Optical black: Horizontal (H) direction: Front 7 pixels, Rear 30 pixels Vertical (V) direction: Front 14 pixels, Rear 1 pixel • Number of dummy bits: Horizontal 16 Vertical 1 (even field only) • Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92832F66-ST ICX055AL VSS VGG GND Vφ1 Vφ2 Vφ3 Vφ4 8 7 6 5 4 3 2 1 Vertical register VOUT Block Diagram and Pin Configuration (Top View) Note Horizontal register 11 12 13 14 15 GND SUB VL RG NC Hφ1 : Photo sensor 16 Hφ2 10 VDD Note) 9 Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 9 VDD Output amplifier drain supply 2 Vφ3 Vertical register transfer clock 10 GND GND 3 Vφ2 Vertical register transfer clock 11 SUB Substrate (Overflow drain) 4 Vφ1 Vertical register transfer clock 12 VL Protective transistor bias 5 GND GND 13 RG Reset gate clock 6 VGG Output amplifier gate bias 14 NC 7 VSS Output amplifier source 15 Hφ1 Horizontal register transfer clock 8 VOUT Signal output 16 Hφ2 Horizontal register transfer clock Absolute Maximum Ratings Item Ratings Unit –0.3 to +55 V VDD, VOUT, VSS – GND –0.3 to +18 V VDD, VOUT, VSS – SUB –55 to +10 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +20 V Vφ1, Vφ2, Vφ3, Vφ4 – SUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V Hφ1, Hφ2, RG, VGG – GND –10 to +15 V Hφ1, Hφ2, RG, VGG – SUB –55 to +10 V VL – SUB –65 to +0.3 V Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL –0.3 to +30 V RG – VL –0.3 to +24 V VGG, Vss, Hφ1, Hφ2 – VL –0.3 to +20 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate voltage SUB – GND Supply voltage Vertical clock input voltage *1 +27V (Max.) when clock width<10µs, clock duty factor<0.1%. –2– Remarks ∗1 ICX055AL Bias Conditions Item Symbol Min. Typ. Max. Unit Output amplifier drain voltage VDD 14.55 15.0 15.45 V Output amplifier gate voltage VGG 1.75 2.0 2.25 V Output amplifier source VSS Substrate voltage adjustment range VSUB 9.0 18.5 V Fluctuation range after substrate voltage adjustment ∆VSUB –3 +3 % Reset gate clock voltage adjustment range VRGL 1.0 4.0 V Fluctuation range after reset gate clock voltage adjustment ∆VRGL –3 +3 % Grounded with 680Ω resistor ±5% ∗1 ∗1 ∗2 VL Protective transistor bias Remarks DC Characteristics Item Symbol Min. Typ. Max. Unit 3 Remarks Output amplifier drain current IDD mA Input current IIN1 1 µA ∗3 Input current IIN2 10 µA ∗4 ∗1 Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is ±3%. VSUB code VRGL code one character indication one character indication ↑ ↑ VRGL code VSUB code Code and optimal setting correspond to each other as follows. VRGL code 1 2 3 4 5 6 7 Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VSUB code E Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 f G h J K L m N P Q R S T U V W X Y Z <Example> “5L” → VRGL = 3.0V VSUB = 12.0V ∗2 VL setting is the VVL voltage of the vertical transfer clock waveform. ∗3 1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested are grounded. 2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin. 3) Current to each pin when 15V is applied sequentially to RG, Hφ1, Hφ2 and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin. 4) Current to VL pin when 30V is applied to Vφ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied to RG pin or when, 20V is applied to VGG, Vss, Hφ1 and Hφ2 pins, while VL pin is grounded. However, GND and SUB pins are left open. ∗4 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. –3– ICX055AL Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –9.0 –8.5 –8.0 V 2 VVL = (VVL3 + VVL4) /2 VφV 7.8 8.5 9.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) 0.1 V 2 Symbol |VVH1 – VVH2| Remarks VVH = (VVH1 + VVH2) /2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling Horizontal transfer clock voltage VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 Reset gate clock voltage VφRG 4.5 5.0 5.5 V 4 ∗1 0.8 V 4 Low-level coupling 24.5 V 5 VRGLH – VRGLL Substrate clock voltage VφSUB 22.5 23.5 ∗1 The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Symbol Min. Typ. Max. Unit Waveform diagram VRGL –0.2 0 0.2 V 4 VφRG 8.5 9.0 9.5 V 4 –4– Remarks ICX055AL Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit CφV1, CφV3 1500 pF CφV2, CφV4 820 pF CφV12, CφV34 470 pF CφV23, CφV41 230 pF CφV13 150 pF CφV24 230 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 47 pF Capacitance between horizontal transfer clocks CφHH 47 pF Capacitance between reset gate clock and GND CφRG 5 pF Capacitance between substrate clock and GND CφSUB 320 pF R1, R3 51 Ω R2, R4 100 Ω Vertical transfer clock ground resistor RGND 15 Ω Horizontal transfer clock series resistor RφH 10 Ω Reset gate clock series resistor RφRG 40 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vφ1 Remarks Vφ2 CφV12 R1 R2 RφH RφH Hφ1 CφV1 Hφ2 CφHH CφV2 CφV41 CφV23 CφH1 CφH2 CφV13 CφV24 CφV4 RGND CφV3 R4 R3 CφV34 Vφ4 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RφRG RGφ CφRG Reset gate clock equivalent circuit –5– ICX055AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 –6– VVL ICX055AL (3) Horizontal transfer clock waveform tr twh tf 90% VφH twl 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl Point A VφRG RG waveform VRGL + 0.5V VRGLH VRGL VRGLL Hφ1 waveform 10% VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL –7– ICX055AL (5) Substrate clock waveform 100% 90% φM VφSUB VSUB 10% 0% tr twh φM 2 tf Clock Switching Characteristics Item Symbol twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT 2.3 2.5 Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Hφ Horizontal transfer clock Hφ1 Horizontal transfer clock Hφ2 Reset gate clock φRG 11 Substrate clock φSUB 1.5 2.0 0.5 0.5 41 38 42 75 15 ∗2 During readout 10 15 ns During imaging 0.012 0.012 5.6 0.012 0.012 µs During parallelserial µs conversion 79 6.5 4.5 ns 5.6 15 12 µs 0.25 µs ∗1 0.015 37 Unit Remarks 0.5 ∗1 When vertical transfer clock driver CXD1250 is used. ∗2 tf ≥ tr – 2ns –8– 0.5 µs During drain charge ICX055AL Image Sensor Characteristics Item (Ta = 25°C) Symbol Min. Typ. Sensitivity S 420 500 Saturation signal Vsat 630 Smear Sm Unit Measurement method mV 1 mV 2 0.007 % 3 Video signal shading SH 20 % 4 Zone 0, I 25 % 4 Zone 0 to II' Dark signal Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 2 % 7 Lag Lag 0.5 % 8 0.005 Max. Zone Definition of Video Signal Shading 500 (H) 9 6 9 H 8 V 10 H 8 Zone 0, Ι Zone ΙΙ, ΙΙ' V 10 582 (V) 8 Ignored region Effective pixel region –9– Remarks Ta = 60°C ICX055AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 [mV] 50 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 × × × 100 [%] (1/10V method conversion value) 200 500 10 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. – 10 – ICX055AL 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/200) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD SG1 Light Strobe light timing Signal output 200mV Output – 11 – Vlag (lag) RG Hφ1 Hφ2 XV4 XSG2 XV3 XSG1 XV1 XV2 22 /10V 47k 10k 0.1 10/16V 100k 11 10 2SA1175 12 13 8 9 14 7 15 16 5 CXD1250 17 4 6 19 18 2 3 22/20V 22/16V 1/35V 0.01 1 2 0.1 680 9 0.01 2SK523 3.9k 100 1500p 3.3/16V 15k 0.1 47k 15k 47/6.3V 3.3/20V 39k 270k 2SC2785× 3 67 8 ICX055 (BOTTOM VIEW) 4 5 3 27k 180k 27k 16 15 14 13 12 11 10 Vφ4 XSUB Vφ3 Hφ1 Hφ2 20 100k 56k NC 1 1/35V Vφ2 1/6.3V Vφ1 RG 10/20V SUB 5V 1/35V VGG 0.1 GND VL VOUT 15V VSS GND – 12 – VDD Drive Circuit 1M CCD OUT [∗A] –8.5V ICX055AL ICX055AL Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 800 1000 900 Wave Length [nm] Sensor Readout Clock Timing Chart HD V1 2.5 V2 Odd Field V3 V4 38.5 1.2 1.5 2.5 2.0 0.3 V1 V2 Even Field V3 V4 Unit: µs – 13 – – 14 – CLP1 OUT CCD V4 V3 V2 V1 SG2 SG1 HD BLK VD FLD 582 581 625 1 2 3 4 5 620 Drive Timing Chart (Vertical sync) 2 4 6 15 1 3 5 2 4 6 1 3 5 315 582 581 330 1 3 5 7 2 4 6 8 335 1 3 5 7 2 4 6 8 ICX055AL 340 325 320 310 25 20 10 – 15 – SUB CLP1 V4 V3 V2 V1 XSHD XSHP RG H2 H1 BLK HD 15 10 500 1 2 3 5 495 490 Drive Timing Chart (Horizontal sync) ICX055AL 7 1 2 3 5 15 16 1 2 3 5 10 1 2 3 5 30 25 20 ICX055AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 16 – – 17 – 1.2 0.69 ~ ~ Plastic GOLD PLATING 42 ALLOY 0.9g PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 0.3 M 1.27 9.2 10.3 12.2 ± 0.1 H ~ 2.5 0.46 0.3 A 1.2 2.5 8.4 (For the first pin only) V 6.1 D B' 9.5 11.4 ± 0.1 3.1 2.5 0.5 PACKAGE STRUCTURE B 5.7 C 1 8 11.6 16 9 2.5 2-R0.5 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.1, 5.7) ± 0.15mm. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. 16pin DIP (450mil) 11.43 Unit: mm 3.35 ± 0.15 1.27 3.5 ± 0.3 0° to 9° 0.25 Package Outline ICX055AL