CXD3406GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor Description The CXD3406GA is a timing generator and CCD signal processor IC for the ICX252/262 CCD image sensor. Features • Timing generator functions • Horizontal drive frequency 12 to 18MHz (Base oscillation frequency 24 to 36MHz) • Supports frame readout/draft (sextuple speed)/ AF (Auto focus drive) • High-speed/low-speed shutter function • Horizontal and vertical drivers for CCD image sensor • CCD signal processor functions • Correlated double sampling • Programmable gain amplifier (PGA) allows gain adjustment over a wide range (–6 to +42dB) • 10-bit A/D converter • Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint 96 pin LFLGA (Plastic) Absolute Maximum Ratings • Supply voltage VSS – 0.3 to +7.0 VDDa, VDDb, VDDc, VDDd VDDe, VDDf, VDDg VSS – 0.3 to +4.0 VL –10.0 to VSS VH VL – 0.3 to +26.0 • Input voltage (analog) VIN VSS – 0.3 to VDD + 0.3 • Input voltage (digital) VI • Output voltage VO1 VO2 VO3 • Operating temperature Topr • Storage temperature Tstg Applications Digital still cameras Structure Silicon gate CMOS IC V VSS – 0.3 to VDD + 0.3 V VSS – 0.3 to VDD + 0.3 VL – 0.3 to VSS + 0.3 VL – 0.3 to VH + 0.3 V V V –20 to +75 °C –55 to +125 °C Recommended Operating Conditions • Supply voltage VDDb 3.0 to 5.5 Applicable CCD Image Sensors ICX252 (1/1.8", 3240K pixels) ICX262 (1/1.8", 3240K pixels) V V V V VDDa, VDDc, VDDd 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 VDDe, VDDf, VDDg 3.0 to 3.6 • Operating temperature Topr –20 to +75 V V V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Z02A26 CXD3406GA DVSS2 E2 F2 F3 DVSS1 B5 DVDD2 DVDD1 A3 A4 B4 DVSS3 TEST5 TEST3 A5 C4 SEN2 SSI2 SCK2 AVSS5 AVSS4 AVSS3 B8 B6 B9 A6 C5 TEST4 A1 A2 C7 D8 D7 AVDD4 AVDD3 C1 C2 C3 NC NC Block Diagram E3 F1 C4 C8 AVDD5 A9 Serial Port Register DAC AVSS6 A8 C7 B7 C8 A7 B3 D0 (LSB) B2 D1 B1 D2 C3 D3 C9 C6 C2 D4 CDS CCDIN C9 PGA ADC Latch C1 D5 AVDD1 E9 D3 D6 AVDD2 E8 D2 D7 AVSS1 D9 D1 D8 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 E1 Dummy Pixel Auto Zero Preblanking Black Level Auto Zero G1 G2 G3 L3 H1 XRS H7 H2 VDD4 H8 H3 VDD2 K7 J3 RG K8 VSS2 K9 L1 VDD3 H9 K1 Pulse Generator H1 J8 J1 H2 J9 VSS3 J7 ID N9 Latch D9 (MSB) ADCLKI CLPOBI CLPDMI VSS4 ADCLK CLPOB CLPDM VSS5 OSCI OSCO CKI J2 CKO 1/2 K2 MCKO Selector N8 SNCSL WEN M9 L2 VH M5 Serial Port Register V Driver SSI1 M1 SCK1 N1 SEN1 VM L4 VL M6 Selector L8 –2– K3 L7 N3 VDD1 VDD5 VSS6 VSS1 L9 VD N2 M2 HD SUB V4 V3B V3A N6 N4 N7 V2 L5 N5 M4 L6 V1B TEST2 TEST1 RST M8 M3 M7 V1A SSG SSGSL CXD3406GA Pin Configuration (Top View) A NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 B D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 C D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D D8 D7 D6 C1 C2 AVSS1 E D9 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 F DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI G ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP H ADCLK CLPOB CLPDM XRS VDD4 VDD3 J CKI CKO VSS5 VSS3 H1 H2 K OSCO MCKO VDD5 VDD2 RG VSS2 L OSCI SSI1 VSS4 VM V1A V3A VSS1 SSGSL VDD1 M SCK1 VD TEST1 V2 VH VL TEST2 RST WEN N SEN1 HD VSS6 V4 V1B V3B SUB SNCSL ID 1 2 3 4 5 6 7 8 9 –3– CXD3406GA Pin Description Pin No. Symbol I/O Description A1 NC — No connected. A2 NC — No connected. A3 SCK2 I CCD signal processor block serial interface clock input. (Schmitt trigger) A4 SSI2 I CCD signal processor block serial interface data input. (Schmitt trigger) A5 TEST3 I CCD signal processor block test input 3. Connect to DVSS. A6 AVSS4 — CCD signal processor block analog GND. A7 C8 — Capacitor connection. A8 AVSS6 — CCD signal processor block analog GND. A9 AVDD5 — CCD signal processor block analog power supply. B1 D2 O ADC output. B2 D1 O ADC output. B3 D0 O ADC output (LSB). B4 SEN2 I CCD signal processor block serial interface enable input. (Schmitt trigger) B5 TEST5 I CCD signal processor block test input 5. Connect to DVDD. B6 AVDD4 — CCD signal processor block analog power supply. B7 C7 — Capacitor connection. B8 AVDD3 — CCD signal processor block analog power supply. B9 AVSS3 — CCD signal processor block analog GND. C1 D5 O ADC output. C2 D4 O ADC output. C3 D3 O ADC output. C4 TEST4 I CCD signal processor block test input 4. Connect to DVSS. C5 AVSS5 — CCD signal processor block analog GND. C6 C9 — Capacitor connection. C7 C3 — Capacitor connection. C8 C4 — Capacitor connection. C9 CCDIN I CCD output signal input. D1 D8 O ADC output. D2 D7 O ADC output. D3 D6 O ADC output. D7 C1 — Capacitor connection. D8 C2 — Capacitor connection. D9 AVSS1 — CCD signal processor block analog GND. E1 D9 O ADC output (MSB). E2 DVDD1 — CCD signal processor block digital power supply. (Power supply for ADC) –4– CXD3406GA Pin No. Symbol I/O Description E3 DVSS1 — CCD signal processor block digital GND. (GND for ADC) E7 AVSS2 — CCD signal processor block analog GND. E8 AVDD2 — CCD signal processor block analog power supply. E9 AVDD1 — CCD signal processor block analog power supply. F1 DVSS2 — CCD signal processor block digital GND. F2 DVSS3 — CCD signal processor block digital GND. F3 DVDD2 — CCD signal processor block digital power supply. F7 PBLKI I Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) F8 XSHDI I CCD data level sample-and-hold pulse input. (Schmitt trigger) F9 XSHPI I CCD precharge level sample-and-hold pulse input. (Schmitt trigger) G1 ADCLKI I Clock input for analog/digital conversion. (Schmitt trigger) G2 CLPOBI I CCD optical black signal clamp pulse input. (Schmitt trigger) G3 CLPDMI I CCD dummy signal clamp pulse input. (Schmitt trigger) G7 PBLK O Pulse output for horizontal and vertical blanking period pulse cleaning. G8 XSHD O CCD data level sample-and-hold pulse output. G9 XSHP O CCD precharge level sample-and-hold pulse output. H1 ADCLK O Clock output for analog/digital conversion. H2 CLPOB O CCD optical black signal clamp pulse output. H3 CLPDM O CCD dummy signal clamp pulse output. H7 XRS O Sample-and-hold pulse output for analog/digital conversion phase alignment. H8 VDD4 — Timing generator block digital power supply. (Power supply for CDS block) H9 VDD3 — Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2) J1 CKI I Inverter input. J2 CKO O Inverter output. J3 VSS5 — Timing generator block digital GND. J7 VSS3 — Timing generator block digital GND. J8 H1 O CCD horizontal register clock output. J9 H2 O CCD horizontal register clock output. K1 OSCO O Inverter output for oscillation. When not used, leave open or connect a capacitor. K2 MCKO O System clock output for signal processor IC. K3 VDD5 — Timing generator block digital power supply. (Power supply for common logic block) K7 VDD2 — Timing generator block digital power supply. (Power supply for RG) K8 RG O CCD reset gate pulse output. K9 VSS2 — Timing generator block digital GND. L1 OSCI I Inverter input for oscillation. When not used, fix to low. –5– CXD3406GA Pin No. Symbol I/O Description Timing generator block serial interface data input. Schmitt trigger input/No protective diode on power supply side. L2 SSI1 I L3 VSS4 — Timing generator block digital GND. L4 VM — Timing generator block digital GND. (GND for vertical driver) L5 V1A O CCD vertical register clock output. L6 V3A O CCD vertical register clock output. L7 VSS1 — Timing generator block digital GND. L8 SSGSL L9 VDD1 — M1 SCK1 I M2 VD M3 TEST1 I Timing generator block test input 1. Normally fix to GND. M4 V2 O CCD vertical register clock output. M5 VH — Timing generator block 15.0V power supply. (Power supply for vertical driver) M6 VL — Timing generator block –7.5V power supply. (Power supply for vertical driver) M7 TEST2 I I/O Internal SSG enable. High: Internal SSG valid, Low: External SYNC valid (With pull-down resistor) Timing generator block digital power supply.(Power supply for common logic block) Timing generator block serial interface clock input. Schmitt trigger input/No protective diode on power supply side. Vertical sync signal input/output. I Timing generator block test input 2. Normally fix to GND. (With pull-down resistor) (With pull-down resistor) M8 RST I Timing generator block reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side M9 WEN O Memory write timing pulse output. N1 SEN1 I Timing generator block serial interface strobe input. Schmitt trigger input/No protective diode on power supply side N2 HD I/O Horizontal sync signal input/output. N3 VSS6 — Timing generator block digital GND. N4 V4 O CCD vertical register clock output. N5 V1B O CCD vertical register clock output. N6 V3B O CCD vertical register clock output. N7 SUB O CCD electronic shutter pulse output. N8 SNCSL I Control input used to switch sync system. High: CKI sync, Low: MCKO sync N9 ID O Vertical direction line identification pulse output. –6– (With pull-down resistor) CXD3406GA Electrical Characteristics Timing Generator Block Electrical Characteristics DC Characteristics Item Pins Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 VDD2 VDD3 VDD4 VDD1, VDD5 Input voltage 1∗1 RST Input voltage 2∗2 SSI1, SCK1, SEN1 Input voltage 3∗3 TEST1, TEST2 Input voltage 4∗4 SNCSL, SSGSL Input/output voltage VD, HD Symbol (Within the recommended operating conditions) Conditions VDDa VDDb VDDc VDDd Vi + Vi – Vi + Vi – VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Max. Unit 3.0 3.0 3.0 3.0 0.8VDDd 3.3 3.3 3.3 3.3 3.6 5.5 3.6 3.6 V V V V V V V V V V V V V 0.8VDDd 0.2VDDd 0.7VDDd 0.2VDDd 0.7VDDd 0.3VDDd 0.8VDDd 0.2VDDd Feed current where IOH = –1.2mA VDDd – 0.8 Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA VDDb – 0.8 Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA VDDa – 0.8 Pull-in current where IOL = 2.4mA H1, H2 Output voltage 2 RG Feed current where IOH = –3.3mA Output voltage 3 XSHP, XSHD, VOH4 XRS, PBLK, CLPOB, CLPDM, VOL4 ADCLK Output voltage 4 CKO Output voltage 5 MCKO Output voltage 6 ID, WEN Output current 1 V1A, V1B, V3A, V3B, V2, V4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL IOSH Feed current where IOH = –6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = –8.25V V1A/B, V2, V3A/B, V4 = –0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = –8.25V SUB = 14.75V SUB Typ. 0.2VDDd Output voltage 1 Output current 2 Min. 0.4 0.4 V VDDc – 0.8 0.4 Pull-in current where IOL = 2.4mA ∗1 ∗2 ∗3 ∗4 0.4 V V V V V V V VDDd – 0.8 0.4 VDDd – 0.8 0.4 VDDd – 0.8 0.4 10.0 –5.0 5.0 –7.2 5.4 –4.0 V V V V V V V mA mA mA mA mA mA This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC. These input pins are schmitt trigger inputs. These input pins are with pull-down resistor in the IC. These input pins are with pull-down resistor in the IC and they do not have protective diode of the power supply side in the IC. Note) The above table indicates the condition for 3.3V drive. –7– CXD3406GA Inverter I/O Characteristics for Oscillation Item Pins Symbol Logical Vth OSCI Input voltage OSCI Output voltage OSCO Feedback resistor OSCI, OSCO RFB Oscillation frequency OSCI, OSCO f (Within the recommended operating conditions) Min. Conditions Typ. LVth Max. VDDd/2 VIH V 0.7VDDd V VIL 0.3VDDd VOH Feed current where IOH = –3.6mA VOL Pull-in current where IOL = 2.4mA VIN = VDDd or VSS VDDd – 0.8 500k Unit V V 2M 20 0.4 V 5M Ω 50 MHz Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Pins Logical Vth Input voltage Symbol Conditions Min. LVth CKI Input amplitude Typ. VDDd/2 VIH V 0.3VDDd fmax 50MHz sine wave Unit V 0.7VDDd VIL VIN Max. 0.3 V Vp-p Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is the input amplitude characteristics in the case of input through a capacitor. Switching Characteristics Item Rise time Fall time Output noise voltage (VH = 15.0V, VM = GND, VL = –7.5V) Symbol Conditions Min. Typ. Max. Unit TTLM VL to VM 200 350 500 ns TTMH VM to VH 200 350 500 ns TTLH VL to VH 30 60 90 ns TTML VM to VL 200 350 500 ns TTHM VH to VM 200 350 500 ns TTHL VH to VL 30 60 90 ns VCLH 1.0 V VCLL 1.0 V VCMH 1.0 V VCML 1.0 V Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. 3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor. –8– CXD3406GA Switching Waveforms TTMH TTHM VH V1A (V1B, V3A, V3B) TTLM 90% 90% 10% 10% TTML VM 90% 90% 10% 10% TTML TTLM VL VM 90% 90% V2 (V4) 10% 10% TTLH TTHL 90% VL VH 90% SUB 10% 10% VL Waveform Noise VM VCMH VCML VCLH VCLL VL –9– – 10 – C1 R1 R1 C2 R1 C1 C2 C2 C2 C1 C2 3300pF 30Ω C2 C1 C2 C2 C1 C2 C2 R2 C2 R2 C1 C2 C1 C2 560pF 10Ω R1 C2 R1 C3 820pF C3 C4 D2 AVDD5 AVSS6 C8 AVSS4 TEST3 SSI2 SCK2 NC NC C6 CXD3406GA PBLKI V3A L6 VSS1 30pF N9 ID N8 SNCSL L7 N7 SUB V1A VM L5 L4 N2 HD N1 SEN1 M9 WEN M8 RST M7 TEST2 N6 V3B N5 V1B N4 V4 M3 TEST1 215pF C6 10pF A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6 C5 F2 F3 F7 F8 F9 E9 E2 E8 D8 D7 D3 D2 D1 C9 C8 C7 AVDD2 C2 C1 D6 D7 D8 CCDIN C4 C3 DVSS1 DVDD1 F1 E3 DVSS2 E7 D9 AVSS2 AVSS1 AVDD1 ADCLKI G1 DVSS3 AVDD4 M2 VD D1 C2 C7 DVDD2 AVSS3 M1 SCK1 D0 C2 VSS6 VDD1 SSI1 L9 MCKO XSHDI RG SSGSL VSS2 L8 VDD2 H1 OSCI XSHPI OSCO ADCLK H2 E1 D9 VDD5 CLPOBI G2 H1 M6 VL VSS3 CLPDMI G3 CKI M5 VH VDD3 M4 V2 VSS5 SEN2 R1 C6 CKO TEST5 R1 C5 C5 VDD4 N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7 C4 XRS AVDD3 –7.5V C6 CLPDM D5 +3.3V CLPOB D4 +15.0V VSS4 D3 VD CKI XSHP TEST4 HD Serial interface data XSHD AVSS5 PBLK C9 Measurement Circuit CXD3406GA CXD3406GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDDd SSI1 0.2VDDd 0.8VDDd SCK1 ts1 SEN1 th1 0.2VDDd ts3 0.8VDDd SEN1 ts2 (Within the recommended operating conditions) Definition Symbol ts1 th1 ts2 ts3 Min. Typ. Max. Unit SSI1 setup time, activated by the rising edge of SCK1 20 ns SSI1 hold time, activated by the rising edge of SCK1 20 ns SCK1 setup time, activated by the rising edge of SEN1 20 ns SEN1 setup time, activated by the rising edge of SCK1 20 ns Serial interface clock internal loading characteristics (1) Example: During frame mode VD HD V1A Enlarged view HD 0.2VDDd V1A th1 ts1 0.8VDDd SEN1 0.2VDDd ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period. (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit SEN1 setup time, activated by the falling edge of HD 0 ns SEN1 hold time, activated by the falling edge of HD 102 µs – 11 – CXD3406GA Serial interface clock internal loading characteristics (2) Example: During frame mode VD HD Enlarged view VD 0.2VDDd HD ts1 SEN1 th1 0.8VDDd 0.2VDDd ∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD. (Within the recommended operating conditions) Definition Symbol ts1 th1 Min. Typ. Max. Unit SEN1 setup time, activated by the falling edge of VD 0 ns SEN1 hold time, activated by the falling edge of VD 200 ns Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD3406GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3406GA and controlled at the rising edge of SEN1. See "Description of Operation". SEN1 0.8VDDd Output signal tpdPULSE (Within the recommended operating conditions) Symbol Definition Min. tpdPULSE Output signal delay, activated by the rising edge of SEN1 – 12 – 5 Typ. Max. Unit 100 ns CXD3406GA RST loading characteristics 0.8VDDd RST 0.2VDDd tw1 (Within the recommended operating conditions) Definition Symbol tw1 Min. RST pulse width Typ. Max. Unit ns 35 VD and HD loading characteristics VD, HD 0.2VDDd 0.2VDDd ts1 th1 0.8VDDd MCKO MCKO load capacitance = 10pF (Within the recommended operating conditions) Symbol ts1 th1 Definition Min. Typ. Max. Unit VD and HD setup time, activated by the rising edge of MCKO 20 ns VD and HD hold time, activated by the rising edge of MCKO 5 ns Output variation characteristics MCKO 0.8VDDd WEN, ID tpd1 WEN and ID load capacitance = 10pF (Within the recommended operating conditions) Symbol tpd1 Definition Min. Time until the above outputs change after the rise of MCKO 20 – 13 – Typ. Max. Unit 60 ns CXD3406GA CCD Signal Processor Block Electrical Characteristics DC Characteristics Item (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Pins Conditions Symbol Min. Typ. Max. Unit Supply voltage 1 DVDD1 VDDe 3.0 3.3 3.6 V Supply voltage 2 DVDD2 VDDf 3.0 3.3 3.6 V AVDD1, AVDD2, Supply voltage 3 AVDD3, AVDD4, AVDD5 VDDg 3.0 3.3 3.6 V Analog input capacitance CCDIN CIN 15 pF 1.8 V Input voltage SCK2, SSI2, VI + SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, VI – CLPOBI, CLPDMI, PBLKI 1.1 V A/D clock duty ADCLKI 50 % Output voltage D0 to D9 VOH Feed current where IOH = –2.0mA VOL Pull-in current where IOL = 2.0mA Analog Characteristics Item VDDe – 0.9 V 0.4 V (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol Conditions Min. Typ. Max. Unit CCDIN input voltage amplitude VIN PGA gain = 0dB, output full scale PGA maximum gain Gmax PGA gain setting data = "3FFh" 42 dB PGA minimum gain Gmin PGA gain setting data = "000h" –6 dB 10 bit 900 ADC resolution 1100 mV ADC maximum conversion rate Fc max ADC integral non-linearity error EL PGA gain = 0dB ±1.0 ±5.0 LSB ADC differential non-linearity error ED PGA gain = 0dB ±0.5 ±1.0 LSB Signal-to-noise ratio SNR∗1 CCDIN input connected to GND via a coupling capacitor PGA gain = 0dB CCDIN input voltage clamp level CLP CCD optical black signal clamp level OB 18 OBLVL = "8h" PGA gain = 0dB ∗1 SNR = 20 log (full-scale voltage/rms noise) – 14 – MHz 62 dB 1.5 V 32 LSB CXD3406GA AC Characteristics AC characteristics between the serial interface clocks 0.8VDD SSI2 0.2VDD 0.8VDD SCK2 ts1 SEN2 th1 0.2VDD ts3 0.8VDD SEN2 ts2 ∗ The setting values are reflected to the operation 5 or 6 ADCLKI clocks after the serial data is loaded at the rise of SEN2. (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Symbol tp1 ts1 th1 ts2 ts3 Definition Min. Typ. Max. Unit SCK2 clock period 100 ns SSI2 setup time, activated by the rise of SCK2 30 ns SSI2 hold time, activated by the rise of SCK2 30 ns SCK2 setup time, activated by the rise of SEN2 30 ns SEN2 setup time, activated by the rise of SCK2 30 ns – 15 – CXD3406GA CDS/ADC Timing Chart N N+1 N+2 N+3 CCDIN XSHPI XSHDI tw1 ADCLKI DL D0 to D9 N – 10 N–9 N–8 N–7 ∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0". (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C) Definition Symbol tw1 DL Min. ADCLKI clock period Typ. 54 Max. Unit ns ADCLKI clock duty 50 % Data latency 9 clocks Preblanking Timing Chart PBLKI 11 Clocks ADCLKI 11 Clocks All "0" D0 to D9 – 16 – CXD3406GA Description of Operation Pulses output from the CXD3406GA's timing generator block are controlled mainly by the RST pin and by the serial interface data. The Pin Status Table is shown below, and the details of serial interface control are described on page 19 and thereafter. Pin Status Table Pin No. Symbol — D3 D6 — NC — D7 C1 — A3 SCK2 — D8 C2 — A4 SSI2 — D9 AVSS1 — A5 TEST3 — E1 D9 — A6 AVSS4 — E2 DVDD1 — A7 C8 — E3 DVSS1 — A8 AVSS6 — E7 AVSS2 — A9 AVDD5 — E8 AVDD2 — B1 D2 — E9 AVDD1 — B2 D1 — F1 DVSS2 — B3 D0 — F2 DVSS3 — B4 SEN2 — F3 DVDD2 — B5 TEST5 — F7 PBLKI — B6 AVDD4 — F8 XSHDI — B7 C7 — F9 XSHPI — B8 AVDD3 — G1 ADCLKI — B9 AVSS3 — G2 CLPOBI — C1 D5 — G3 CLPDMI — C2 D4 — G7 PBLK ACT C3 D3 — G8 XSHD C4 TEST4 — G9 C5 AVSS5 — C6 C9 C7 Pin No. Symbol A1 NC A2 CAM SLP STB RST STB RST L L H ACT L L ACT XSHP ACT L L ACT H1 ADCLK ACT L L ACT — H2 CLPOB ACT L L H C3 — H3 CLPDM ACT L L H C8 C4 — H7 XRS ACT L L ACT C9 CCDIN — H8 VDD4 — D1 D8 — H9 VDD3 — D2 D7 — J1 CKI ACT ACT – 17 – CAM ACT SLP ACT CXD3406GA Pin No. Symbol CAM SLP STB RST Pin No. Symbol J2 CKO ACT ACT L ACT L9 VDD1 J3 VSS5 — M1 J7 VSS3 — M2 SCK1 VD∗1 J8 H1 ACT L L ACT M3 TEST1 J9 H2 ACT L L ACT M4 V2 K1 OSCO ACT ACT ACT ACT M5 VH — K2 MCKO ACT ACT L ACT M6 VL — K3 VDD5 — M7 TEST2 — K7 VDD2 — M8 RST ACT K8 RG M9 WEN K9 VSS2 N1 L1 OSCI ACT ACT ACT ACT N2 SEN1 HD∗1 L2 SSI1 ACT ACT ACT DIS N3 VSS6 L3 VSS4 — N4 V4 ACT L4 VM — N5 V1B L5 V1A ACT VH VH VM N6 L6 V3A ACT VH VH VL L7 VSS1 L8 SSGSL ACT L L ACT — — ACT ACT ACT ACT CAM SLP STB RST — ACT ACT ACT DIS ACT L L H VM VM ACT ACT L ACT L L L ACT ACT ACT DIS ACT L L H VM VM VL ACT VH VH VM V3B ACT VH VH VL N7 SUB ACT VH VH VL N8 SNCSL ACT ACT ACT ACT N9 ID ACT L L L — ACT VM — ∗1 It is for output. For input, all items are "ACT". Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output level, and H a high output level in the controlled status. Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6), respectively, in the controlled status. – 18 – CXD3406GA Timing Generator Block Serial Interface Control The CXD3406GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value. Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the rising edge of SEN1. SSI1 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 SCK1 SEN1 There are two categories of timing generator block serial interface data: CXD3406GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). The details of each data are described below. – 19 – CXD3406GA Control Data Data Symbol Function Data = 0 Data = 1 RST D00 to D07 CHIP Chip enable 10000001 → Enabled Other values → Disabled All 0 D08 to D09 CTG Category switching See D08 to D09 CTG. All 0 D10 to D12 MODE Drive mode switching See D10 to D12 MODE. All 0 D13 to D14 SMD Electronic shutter mode switching See D13 to D14 SMD. All 0 D15 PTSG Internal SSG output pattern switching D16 to D23 CDAT AF drive control data NTSC equivalent PAL equivalent See D16 to D23 CDAT. 0 All 0 D24 to D33 — — — — All 0 D34 — — — — 1 D35 — — — — 0 D36 to D37 LDAD D38 to D39 STB D40 to D47 1 ADCLK logic phase switching See D36 to D37 LDAD. 0 Standby control — See D38 to D39 STB. — — – 20 – — All 0 All 0 CXD3406GA Shutter Data Data Function Symbol Data = 0 Data = 1 RST D00 to D07 CHIP Chip enable 10000001 → Enabled Other values → Disabled All 0 D08 to D09 CTG Category switching See D08 to D09 CTG. All 0 D10 to D19 SVD Electronic shutter vertical period specification See D10 to D19 SVD. All 0 D20 to D31 SHD Electronic shutter horizontal period specification See D20 to D31 SHD. All 0 D32 to D41 SPL High-speed shutter position specification See D32 to D41 SPL. All 0 D42 to D47 — — — – 21 – — All 0 CXD3406GA Detailed Description of Each Data Shared data: D08 to D09 CTG [Category] Of the data provided to the CXD3406GA by the timing generator block serial interface, the CXD3406GA loads D10 and subsequent data to each data register as shown in the table below according to the combination of D08 and D09 . D09 D08 Description of operation 0 0 Loading to control data register 0 1 Loading to shutter data register 1 X Test mode Note that the CXD3406GA can apply these categories consecutively within the same vertical period. However, care should be taken as the data is overwritten if the same category is applied. Control data: D10 to D12 MODE [Drive mode] The CXD3406GA timing generator block drive mode can be switched as follows. However, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of VD. Description of operation D12 D11 D10 0 0 0 Draft mode (sextuple speed: default) 0 0 1 Frame mode (A field readout) 0 1 0 Frame mode (B Field readout) 0 1 1 Frame mode 1 0 X AF1 mode 1 1 X AF2 mode Control data: D15 PTSG [Internal SSG output pattern] The CXD3406GA internal SSG output pattern can be switched as follows. However, the drive mode bits are loaded to the CXD3406GA and reflected at the falling edge of VD. D15 Description of operation 0 NTSC equivalent pattern 1 PAL equivalent pattern The VD period in each pattern is defined as follows for each drive mode. NTSC equivalent pattern PAL equivalent pattern Frame mode Draft mode AF1 mode AF2 mode 918H + 1716ck 945H∗1 262H + 1144ck 131H + 572ck 65H + 1430ck 314H + 1568ck 157H + 784ck 78H + 1536ck ∗1 Only 944H and 945H are 1208ck period. See the Timing Charts for the actual operation. – 22 – CXD3406GA Control data: D36 to D37 LDAD [ADCLK logic phase] This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO. D37 D36 Degree of adjustment (°) 0 0 0 0 1 90 1 0 180 1 1 270 Control data: D38 to D39 STB [Standby] The operating mode of the timing generator block is switched as follows. However, the standby bits are loaded to the CXD3406GA and control is applied immediately at the rising edge of SEN1. D39 D38 Symbol Operating mode X 0 CAM Normal operating mode 0 1 SLP Sleep mode 1 1 STB Standby mode See the Pin Status Table for the pin status in each mode. – 23 – CXD3406GA Control data: [AF drive] The CXD3406GA controls the drive of the vertical cut-out area of the line in AF1/AF2 mode by using control data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and cannot support operation such as electrical image stabilization. The AF drive bits are loaded to the CXD3406GA and reflected at the falling edge of VD. As shown in the figure below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then normal transfer is performed equivalent to draft mode from the frame shift to the stage specified by the serial interface data to the timing of the falling edge of the next VD. Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for its application. VD High-speed sweep Normal transfer Frame shift V1A Vck MODE 0 4 0 CDAT 00h FFh 00h The number of high-speed sweep are different according to the selected mode. They are specified as follows. AF1 mode: 138 stages (0 to 7H) AF2 mode: 208 stages (0 to 11H) The frame shift data is expressed as shown in the table below using D16 to D23 CDAT. MSB LSB D23 D22 0 1 ↓ 6 D21 D20 D19 D18 1 0 1 0 D17 D16 0 1 ↓ 9 CDAT is expressed as 69h . Its definition area is specified as follows. AF1 mode: 00h ≤ CDAT ≤ FFh (11 to 23H) AF2 mode: 00h ≤ CDAT ≤ FFh (14 to 27H) – 24 – CXD3406GA Control data/shutter data: [Electronic shutter] The CXD3406GA realizes various electronic shutter functions by using control data D13 to D14 SMD and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL. These functions are described in detail below. First, the various modes are shown below. These modes are switched using control data D13 to D14 SMD. D14 D13 0 0 0 1 1 0 1 1 Description of operation Electronic shutter stopped mode High-speed/low-speed shutter mode HTSG control mode The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example. However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC. MSB LSB D31 D30 X 0 ↓ 1 D29 D28 D27 D26 0 1 1 1 ↓ C D25 D24 D23 D22 0 0 0 0 ↓ 3 D21 D20 1 1 SHD is expressed as 1C3h . [Electronic shutter stopped mode] During this mode, all shutter data items are invalid. SUB is not output in this mode, so the shutter speed is the accumulation time for one field. [High-speed/low-speed shutter mode] During this mode, the shutter data items have the following meanings. Symbol Data Description SVD D10 to D19 Number of vertical periods specification (000h ≤ SVD ≤ 3FFh) SHD D20 to D31 Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh) SPL D32 to D41 Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh) The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished. The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of horizontal periods applied to SHD can be considered as (number of SUB pulses – 1). However, in the frame mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same mode is repeated. But this change may not occur because of flickerless depending on the conditions during low-speed shutter. Note) The bit data definition area is assured in terms of the CXD3406GA functions, and does not assure the CCD characteristics. – 25 – CXD3406GA VD SVD SHD V1A SUB WEN SMD 01 SVD 002h 000h SHD 10Fh 050h 01 Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the low-speed shutter period. In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods. SPL VD SVD SHD V1A SUB WEN SMD 10 SPL 001h 000h SVD 002h 000h SHD 10Fh 0A3h 01 Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. Using this function, it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. – 26 – CXD3406GA [HTSG control mode] During this mode, all shutter data items are invalid. The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure. VD V1A Exposure time SUB Vck WEN SMD 11 01 – 27 – 01 – 28 – WEN ID CLPDM CLPOB PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD 1548 1546 1544 1542 810 918 C 1 High-speed sweep block A 29 34 810 918 C 1 High-speed sweep block B 28 B Field 34 2 4 6 8 2 4 6 8 10 12 • ICX252/262 Frame mode 1 3 5 7 1 3 5 7 9 11 13 15 A Field Applicable CCD image sensor MODE 1549 1547 1545 1543 1541 1539 ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck period only for 944H and 945H. 1550 Chart-1 Vertical Direction Timing Chart CXD3406GA – 29 – WEN ID CLPDM CLPOB PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD D D 525 532 537 544 549 527 534 539 546 • ICX252/262 Draft mode 6 3 10 15 22 27 34 4 1 8 13 20 25 32 261 262 1 2 Applicable CCD image sensor MODE ∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. ∗ VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units. 6 3 10 15 22 27 34 4 1 8 13 20 25 32 261 262 1 2 525 532 537 544 549 527 534 539 546 Chart-2 Vertical Direction Timing Chart CXD3406GA – 30 – WEN ID CLPDM CLPOB PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD ∗ ∗ ∗ ∗ High-speed sweep block D 8 6 4 G 10 Frame shift block F 131 1 High-speed sweep block D 8 6 4 G 10 Frame shift block • ICX252/262 AF1 mode 25 Applicable CCD image sensor MODE The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 138 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units. F 131 1 Chart-3 Vertical Direction Timing Chart 25 CXD3406GA – 31 – WEN ID CLPDM CLPOB PBLK CCD OUT V4 V3B V3A V2 V1B V1A SUB HD VD ∗ ∗ ∗ ∗ High-speed sweep block D 12 6 4 G 14 Frame shift block F 65 1 High-speed sweep block D 12 6 4 G 14 Frame shift block • ICX252/262 AF2 mode 29 Applicable CCD image sensor MODE The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component. 208 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift block. VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units. F 65 1 Chart-4 Vertical Direction Timing Chart 29 CXD3406GA – 32 – WEN ID CLPDM CLPOB PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD ∗ ∗ ∗ ∗ ∗ 10 47 52 52 52 50 70 70 90 99 110 110 110 128 138 148 150 157 174 172 198 198 200 250 • ICX252/262 Frame mode 100 Applicable CCD image sensor MODE HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. ID and WEN are output at this timing shown above at the position shown in Chart-1. (2288) 0 Chart-5 Horizontal Direction Timing Chart CXD3406GA – 33 – WEN ID CLPDM CLPOB PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD ∗ ∗ ∗ ∗ ∗ 10 47 52 52 52 50 61 57 71 66 70 75 79 84 88 97 93 102 106 110 110 120 133 111 124 115 140 147 138 151 129 142 150 156 174 172 198 198 200 • ICX252/262 Draft/AF1/AF2 mode 100 Applicable CCD image sensor MODE 250 HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. ID and WEN are output at this timing shown above at the position shown in Charts-2, 3 and 4. (2288) 0 Chart-6 Horizontal Direction Timing Chart CXD3406GA – 34 – WEN ID CLPDM CLPOB PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD ∗ ∗ ∗ ∗ ∗ 52 52 52 50 70 71 71 #1 81 81 100 100 110 110 129 129 139 138 #2 139 150 158 158 168 168 172 187 187 197 #3 197 200 216 216 226 226 245 255 250 245 • ICX252/262 Frame mode 100 Applicable CCD image sensor MODE #4 255 274 274 HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck(#1038). (2288) 0 Chart-7 Horizontal Direction Timing Chart (High-speed sweep: C) CXD3406GA – 35 – WEN ID CLPDM CLPOB PBLK SUB V4 V3A/B V2 V1A/B H2 H1 MCKO HD ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 10 47 52 52 52 52 50 64 71 64 71 71 83 83 90 90 102 109 105 110 #1 102 109 121 121 128 128 140 140 140 147 147 150 159 159 166 166 178 172 178 185 185 197 197 204 200 204 216 219 216 223 #2 223 235 235 242 242 • ICX252/262 AF1/AF2 mode 100 Applicable CCD image sensor MODE 254 250 254 261 261 273 273 280 HD of this chart indicates the actual CXD3406GA load timing. The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. SUB is output at this timing shown above when output is controlled by the serial interface data. WEN is output at this timing shown above at the position shown in Chart-3 and 4. High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2 mode. Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and can specify up to #255 for both of AF1/AF2 mode. ID is output at the timing shown with dotted line during frame shift. (2288) 0 Chart-8 Horizontal Direction Timing Chart (High-speed sweep: F) (Frame shift: G) CXD3406GA [B Field] [A Field] – 36 – V4 V3B V3A V2 V1B V1A V4 V3B V3A V2 V1B V1A HD 241 211 181 148 157 Logic alignment portion [B] [A] • ICX252/262 (2288) 0 148 157 128 1310 1280 1250 1190 1160 1130 1100 128 90 99 110 70 52 ∗ HD of this chart indicates the actual CXD3406GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. (2288) 0 Frame mode 52 Applicable CCD image sensor 70 MODE 90 99 110 Chart-9 Horizontal Direction Timing Chart CXD3406GA V4 V3B V3A V2 V1B V1A HD [D] 1160 1130 1100 1070 1040 1010 Draft/AF1/AF2 mode 1430 1400 1370 1340 1310 1280 1250 1220 1190 • ICX252/262 (2288) 0 Applicable CCD image sensor ∗ HD of this chart indicates the actual CXD3406GA load timing. ∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD. ∗ The HD fall period should be between approximately 2.9 to 9.5µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing. (2288) 0 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 MODE 52 57 61 66 70 75 79 84 88 93 97 102 106 111 115 120 124 129 133 138 142 147 151 156 Chart-10 Horizontal Direction Timing Chart CXD3406GA – 37 – – 38 – XRS XSHD XSHP RG H2 H1 MCKO ADCLK CKO CKI HD' HD MODE 52 • ICX252/262 172 Applicable CCD image sensor ∗ HD' indicates the HD which is the actual CXD3406GA load timing. ∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse. ∗ The logical phase of ADCLK can be specified by the serial interface data. 1 Chart-11 High-Speed Phase Timing Chart CXD3406GA – 39 – 050h 050h SHD B 050h 01 0 B C 050h 01 0 C D 050h 01 0 E 000h 00 3 E 000h 00 3 E 01 0 050h Open F • ICX252/262 Draft → Frame → Draft Close Applicable CCD image sensor MODE ∗ This chart is a driving timing chart example of electronic shutter normal operation. ∗ Data exposed at D includes blooming component. For details, see the CCD image sensor Data Sheet. ∗ The CXD3406GA does not generate the pulse to control mechanical shutter operation. ∗ The switching timing of the drive mode and the electronic shutter data is not the same. 01 01 SMD 0 A 0 A MODE CCD OUT Exposure time Mechanical shutter SUB V4 V3B V3A V2 V1B V1A VD Chart-12 Vertical Direction Sequence Chart 050h 01 0 F CXD3406GA CXD3406GA CCD Signal Processor Block Serial Interface Control The CXD3406GA's CCD signal processor block basically loads the CCD signal processor block serial interface data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the operation 6 ADCLKI clocks after that. CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode. 00 SSI2 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 SCK2 SEN2 There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain setting data, OB clamp level setting data, and input pulse polarity setting data. Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then transmit the next category. The detail of each data are described below. Standby Control Data Data Symbol Function D00 TEST Test code D01 to D03 CTG Category switching D04 to D14 FIXED D15 STB Data = 0 Data = 1 Set to 0. D01 to D03 CTG — Set to All 0. Standby control Normal operating mode Standby mode Data = 0 Data = 1 PGA Gain Setting Data Data Symbol Function D00 TEST Test code Set to 0. D01 to D03 CTG Category switching D04 to D05 FIXED D06 to D15 GAIN D01 to D03 CTG — Set to All 0. PGA gain setting data See D06 to D15 GAIN. – 40 – CXD3406GA OB Clamp Level Setting Data Data Symbol Function D00 TEST Test code D01 to D03 CTG Category switching D04 to D11 FIXED D12 to D15 OBLVL Data = 0 Data = 1 Set to 0. D01 to D03 CTG — Set to All 0. OB clamp level setting data See D12 to D15 OBLVL. Input Pulse Polarity Setting Data Data Symbol Function D00 TEST Test code D01 to D03 CTG Category switching D04 to D12 FIXED D13 to D15 POL Data = 0 Data = 1 Set to 0. D01 to D03 CTG — Set to All 0. Input pulse polarity setting data Set to All 0. – 41 – CXD3406GA Detailed Description of Each Data Shared data: D01 to D03 CTG [Category] Of the data provided to the CXD3406GA by the CCD signal processor block serial interface, the CXD3406GA loads D04 and subsequent data to each data register as shown in the table below according to the combination of D01 to D03 . D01 D02 D03 Description of operation 0 0 0 Loading to standby control data register 0 0 1 Loading to PGA gain setting data register 0 1 0 Loading to OB clamp level setting data register 0 1 1 Loading to input pulse polarity setting data register 1 X X Access prohibited Standby control data: D15 STB [Standby] The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor block is in standby mode, only the serial interface is valid. D15 Description of operation 0 Normal operating mode 1 Standby mode PGA gain setting data: D06 to D15 GAIN [PGA gain] The CXD3406GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by using PGA gain setting data D06 to D15 GAIN. The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN. MSB LSB D06 0 ↓ 1 D07 D08 D09 1 1 1 ↓ C D10 D11 D12 D13 0 0 0 0 ↓ 3 D14 D15 1 1 GAIN is expressed as 1C3h . For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting values are –6dB, 0dB, +20dB, +34dB and +42dB. – 42 – CXD3406GA OB clamp level setting data: D12 to D15 OBLVL [OB clamp level] The CXD3406GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal processor block control data D12 to D15 OBLVL. The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL. MSB LSB D12 D13 0 1 ↓ 6 D14 D15 1 0 OBLVL is expressed as 6h . For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values are 0LSB, 4LSB, 32LSB and 60LSB. – 43 – SUB V4 V3B V3A V2 V1B V1A RG H2 H1 C4 C3 C2 N7 N4 N6 L5 M4 N5 L5 K8 J9 J8 C8 C7 D8 D7 J1 XSHPI OSCO XSHDI K1 PBLKI L1 CLPOB CLPDM PBLK XSHP M3 M7 A5 C4 B5 TG/CDS/PGA/ADC CXD3406GA ADCLKI B7 A7 C6 L2 N1 M1 A4 B4 A3 G1 C9 0.1µF CLPOBI SNCSL SSGSL L8 Controller RST N8 WEN ID HD VD MCKO CKO D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) NC NC M8 M9 N9 N2 M2 K2 J2 E1 D1 D2 D3 C1 C2 C3 B1 B2 B3 A1 A2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. This block diagram illustrates connections with each circuit block, and is not an actual circuit diagram. See the CCD image sensor data sheet for an example of specific circuit connections with the CCD image sensor. 240pF 390pF 390pF 1µF C1 CKI C9 TEST2 CLPDMI OSCI XSHD TEST3 1µF TEST1 ADCLK G9 G8 G7 H3 H2 H1 SSI1 F9 F8 F7 G3 G2 SEN1 CCDIN TEST4 C7 0.1µF SCK1 CCDOUT TEST5 C8 0.1µF SSI2 CCD ICX252/262 SEN2 – 44 – SCK2 Application Circuit Block Diagram Signal Processor Block CXD3406GA CXD3406GA Notes on Operation 1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either before or at the same time as the VH pin power supply is started up. 15.0V t1 20% 0V 20% t2 –7.5V t2 ≥ t1 2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by initializing the serial data. 3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins. Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2 VDDf and 3 VDDg should be 0.1V or less. 5. The timing generator block and CCD signal processor block ground pins should use a shared ground which is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4, VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4, AVSS5 and AVSS6 should be 0.1V or less. 6. Do not perform serial communication with the CCD signal processor block during the effective image period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which are used by the CCD signal processor block, use of the dedicated ports is recommended. When using these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the effects on picture quality before use. – 45 – CXD3406GA Package Outline Unit: mm Oita Ass'y 0.2 96PIN LFLGA S A 8.0 1.3 MAX 0.2 0.2 S S B 12.0 0.10MAX 0.10 S X PIN 1 INDEX x4 S 0.15 0.5 φ0.08 M S A B N M L K J H G B (0.3) 0.5 0.5 (0.3) 0.8 F E D C B A 0.9 96 -φ0.45 ± 0.05 0.8 A 3 – φ0.50 1 2 3 4 5 6 7 8 9 0.8 0.5 1.2 0.9 (0.3) DETAIL X (0.3) PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE SONY CODE LFLGA-96P-02 TERMINAL TREATMENT EIAJ CODE P-LFLGA96-12X8-0.8 TERMINAL MATERIAL JEDEC CODE 0.2 HITACHI TOKYO Ass'y GOLD PLATING NICKEL PLATING 0.3 g PACKAGE MASS 96PIN LFLGA S A 8.0 1.3 MAX 0.2 0.2 S S B 12.0 0.10MAX 0.10 S X PIN 1 INDEX x4 0.9 (0.3) S 0.5 96 -φ0.45 ± 0.05 0.8 A N M L K J H G F E D C B DETAIL X φ0.08 M S A B B 0.8 0.9 (0.3) 0.15 3 – φ0.50 0.5 (0.3) 1 2 3 4 5 6 7 8 9 0.8 0.5 1.2 (0.3) 0.5 A PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE SONY CODE LFLGA-96P-051 TERMINAL TREATMENT NICKEL & GOLD PLATING EIAJ CODE P-LFLGA96-12.0X8.0-0.8 TERMINAL MATERIAL JEDEC CODE PACKAGE MASS – 46 – COPPER 0.3g Sony Corporation