ICX406AQF Diagonal 8.98mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras Description The ICX406AQF is a diagonal 8.98mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.98M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/3.33 second. Also, number of vertical pixels decimation allows output of 30 frames per second in high frame rate readout mode. This chip features an electronic shutter with variable charge-storage time. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. 20 pin SOP (Plastic) Features • Supprots frame readout • High horizontal and vertical resolution • Supports high frame rate readout mode: 30 frames/s, 25 frames/s, AF1 mode: 60 frames/s, 50 frames/s, AF2 mode: 120 frames/s, 100 frames/s • Square pixel • Horizontal drive frequency: 18MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current • Continuous variable-speed shutter • Excellent anti-blooming characteristics • Exit pupil distance recommended range –20 to –100mm • 20-pin high-precision plastic package Pin 1 2 V 12 16 Pin 11 H 56 Optical black position (Top View) Device Structure • Interline CCD image sensor • Total number of pixels: 2384 (H) × 1734 (V) approx. 4.13M pixels • Number of effective pixels: 2312 (H) × 1720 (V) approx. 3.98M pixels • Number of active pixels: 2308 (H) × 1712 (V) approx. 3.95M pixels diagonal 8.980mm • Number of recommended recording pixels: 2272 (H) × 1740 (V) approx. 3.87M pixels diagonal 8.875mm aspect ratio 4:3 • Chip size: 8.10mm (H) × 6.64mm (V) • Unit cell size: 3.125µm (H) × 3.125µm (V) • Optical black: Horizontal (H) direction: Front 16 pixels, rear 56 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 28 Vertical 1 (even fields only) • Substrate material: Silicon ∗ Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01331-PS ICX406AQF GND TEST TEST Vφ1B Vφ1A Vφ2 Vφ3B Vφ3A Vφ4 10 9 8 7 6 5 4 3 2 1 Vertical register VOUT Block Diagram and Pin Configuration (Top View) Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr Note) Horizontal register 17 φSUB CSUB 18 19 : Photo sensor 20 Hφ2 16 Hφ1 15 VL 14 GND φRG 13 Hφ1 12 Hφ2 11 VDD Note) Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 VDD Supply voltage 2 Vφ3A Vertical register transfer clock 12 φRG Reset gate clock 3 Vφ3B Vertical register transfer clock 13 Hφ2 Horizontal register transfer clock 4 Vφ2 Vertical register transfer clock 14 Hφ1 Horizontal register transfer clock 5 Vφ1A Vertical register transfer clock 15 GND GND 6 Vφ1B 16 φSUB 7 TEST Vertical register transfer clock Test pin∗1 17 CSUB Substrate clock Substrate bias∗2 8 TEST Test pin∗1 18 VL Protective transistor bias 9 GND GND 19 Hφ1 Horizontal register transfer clock 10 VOUT Signal output 20 Hφ2 Horizontal register transfer clock ∗1 Leave this pin open. ∗2 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. –2– ICX406AQF Absolute Maximum Ratings Item Ratings Unit VDD, VOUT, φRG – φSUB –40 to +12 V Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB –50 to +15 V Vφ2, Vφ4, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V CSUB – φSUB –25 to V VDD, VOUT, φRG, CSUB – GND –0.3 to +22 V Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +6.5 V Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL –0.3 to +28 V Vφ2, Vφ4, Hφ1, Hφ2, GND – VL –0.3 to +15 V to +15 V Hφ1 – Hφ2 –6.5 to +6.5 V Hφ1, Hφ2 – Vφ4 –10 to +16 V Storage temperature –30 to +80 °C Guaranteed temperature of performance –10 to +60 °C Operating temperature –10 to +75 °C Against φSUB Against GND Against VL Voltage difference between vertical clock input pins Between input clock pins ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply. –3– Remarks ∗1 ICX406AQF Bias Conditions Symbol Item Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Supply voltage VDD Protective transistor bias VL Substrate clock φSUB ∗2 Reset gate clock φRG ∗2 Remarks ∗1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Min. Typ. Max. Unit IDD 3.0 7.0 10.0 mA Supply current Remarks Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Waveform Diagram Min. Typ. Max. Unit VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.0 –7.5 –7.0 V 2 VVL = (VVL3 + VVL4)/2 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Symbol Remarks VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.9 V 2 High-level coupling VVHL 0.9 V 2 High-level coupling VVLH 0.9 V 2 Low-level coupling VVLL 0.7 V 2 Low-level coupling VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 VCR 0.8 2.5 V 3 VφRG 3.0 3.3 5.25 V 4 VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling 23.5 V 5 VφSUB 21.5 22.5 –4– Cross-point voltage ICX406AQF Clock Equivalent Circuit Constants Item Symbol Min. Typ. Max. Unit Remarks CφV1A, CφV3A 1200 pF CφV1B, CφV3B 4700 pF CφV2, CφV4 3300 pF CφV1A2, CφV3A4 470 pF CφV1B2, CφV3B4 560 pF CφV23A, CφV41A 150 pF CφV23B, CφV41B 220 pF CφV1A3A 39 pF CφV1B3B 220 pF CφV1A3B, CφV1B3A 56 pF CφV24 82 pF CφV1A1B, CφV3A3B 68 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 36 pF Capacitance between horizontal transfer clocks CφHH 91 pF Capacitance between reset gate clock and GND CφRG 8 pF Capacitance between substrate clock and GND CφSUB 1000 pF Vertical transfer clock series resistor R1A, R1B, R2, R3A, R3B, R4 62 Ω Vertical transfer clock ground resistor RGND 18 Ω Horizontal transfer clock series resistor RφH 15 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ2 R2 CφV1A3A CφV23B CφV23A Vφ3A R3A CφV24 CφV1A2 Vφ1A R1A CφV1B2 CφV1A CφV1A1B CφV1B3A CφV1B CφV41A Vφ1B RφH CφV2 CφV3A Hφ2 RφH RφH CφHH Hφ1 CφV3A3B CφV1A3B CφV3B Hφ2 CφH1 R1B CφV4 CφV41B RφH Hφ1 CφH2 CφV3A4 R3B Vφ3B CφV3B4 RGND CφV1B3B R4 Vφ4 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –5– ICX406AQF Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1A, Vφ1B Vφ3A, Vφ3B VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVHH VVHH VVHH VVH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVHL VVLH VVL2VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –6– VVL ICX406AQF (3) Horizontal transfer clock waveform tr tf twh Hφ2 90% VCR VφH twl VφH 2 10% Hφ1 VHL two Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. (4) Reset gate clock waveform tr twh tf VRGH RG waveform twl VφRG Point A VRGLH VRGL VRGLL VRGLm VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval with twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB φM 2 10% 0% VSUB (A bias generated within the CCD) tr twh –7– tf ICX406AQF Clock Switching Characteristics (Horizontal drive frequency: 18MHz) twh Symbol Item VT Vertical transfer clock Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 3.10 3.33 tf Unit Remarks 0.5 µs During readout 250 ns When using CXD3400N 0.5 15 Hφ1 14 19.5 14 19.5 8.5 14 8.5 14 Hφ2 14 19.5 14 19.5 8.5 14 8.5 14 Reset gate clock φRG Substrate clock tr Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock Horizontal transfer clock twl φSUB 7 10 37 4 Symbol Horizontal transfer clock Hφ1, Hφ2 ns 5 1.6 3.56 Item ns tf ≥ tr – 2ns 0.5 0.5 µs During drain charge two Unit Min. Typ. Max. 12 19.5 Remarks ns Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics) 1.0 G B 0.9 R 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 450 500 550 Wave Length [nm] –8– 600 650 700 ICX406AQF Image Sensor Characteristics (horizontal drive frequency: 18MHz) (Ta = 25°C) Min. Typ. Max. Unit Measurement method Sg 180 220 285 mV 1 R Rr 0.35 0.50 0.65 1 B Rb 0.40 0.55 0.70 1 Saturation signal Vsat 380 Smear Sm Video signal shading SHg Dark signal Vdt Dark signal shading Item Symbol G Sensitivity Sensitivity comparison Remarks 1/30s accumulation mV 2 dB 3 % 4 16 mV 5 Ta = 60°C, 3.33 frame/s ∆Vdt 8 mV 6 Ta = 60°C, 3.33 frame/s, ∗2 Line crawl G Lcg 3.8 % 7 Line crawl R Lcr 3.8 % 7 Line crawl B Lcb 3.8 % 7 Lag Lag 0.5 % 8 –85 –81.2 –72 –68.0 20 25 Ta = 60°C Frame readout mode∗1 High frame rate readout mode Zone 0 and I Zone 0 to II' ∗1 After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing vertical register sweep operation. ∗2 Excludes vertical dark signal shading caused by vertical register high-speed transfer. Zone Definition of Video Signal Shading 2312 (H) 2 2 4 V 10 H 8 H 8 Zone 0, I 1720 (V) 4 Zone II, II' V 10 Ignored region Effective pixel region Measurement System CCD signal output [∗A] CCD C.D.S AMP S/H Gr/Gb channel signal output [∗B] S/H R/B channel signal output [∗C] Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1. –9– ICX406AQF Image Sensor Characteristics Measurement Method Measurement conditions (1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions, and the frame readout mode is used. (2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channnel signal output of the measurement system. Color coding of this image sensor & Readout B2 B1 Gb B Gb B R Gr R Gr Gb B Gb B R Gr R Gr A2 A1 The primary color filters of this image sensor are arranged in the layout shown in the figure on the left (Bayer arrangement). Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. For frame readout, the A1 and A2 lines are output as signals in the A field, and the B1 and B2 lines in the B field. Horizontal register Color Coding Diagram – 10 – ICX406AQF Readout modes 1. Readout modes list Mode name Frame readout mode High frame rate readout mode AF1 mode AF2 mode Frame rate Number of effective output lines NTSC mode 3.33 frame/s 1720 (Odd 860, Even 860) PAL mode 3.57 frame/s 1720 (Odd 860, Even 860) NTSC mode 30 frame/s 215 PAL mode 25 frame/s 215 NTSC mode 60 frame/s 97 PAL mode 50 frame/s 119 NTSC mode 120 frame/s 35 PAL mode 100 frame/s 46 2. Frame readout mode, high frame rate readout mode Frame readout mode 1st field VOUT High frame rate readout mode 2nd field Gr 17 R Gr 17 R Gr 17 R 16 Gb B 16 Gb B 16 Gb B R Gr 15 R Gr 15 R Gr 15 14 Gb B 14 Gb B 14 Gb B R Gr Gb B 13 R Gr 13 R Gr 13 12 Gb B 12 Gb B 12 11 R Gr 11 R Gr 11 R Gr 10 Gb B 10 Gb B 10 Gb B 9 R Gr 9 R Gr 9 R Gr 8 Gb B 8 Gb B 8 Gb B 7 R Gr 7 R Gr 7 R Gr Gb B 6 Gb B 6 Gb B 6 5 R Gr 5 R Gr 5 R Gr Gb B Gr 4 Gb B 4 Gb B 4 3 R Gr 3 R Gr 3 R 2 Gb B 2 Gb B 2 Gb B 1 R Gr 1 R Gr 1 R Gr VOUT VOUT Note) Blacked out portions in the diagram indicate pixels which are not read out. 1. Frame readout mode In this mode, all pixel signals are divided into two fields and output. All pixel signals are read out independently, making this mode suitable for high resolution image capturing. 2. High frame rate readout mode Output is performed at 30 frames per second by reading out 4 pixels for every 16 vertical pixels and adding 2 pixels in the horizontal CCD. The number of output lines is 215 lines. This readout mode emphasizes processing speed over vertical resolution. – 11 – ICX406AQF 3. AF1 mode, AF2 mode The AF modes increase the frame rate by cutting out a portion of the picture through high-speed elimination of the top and bottom of the picture in high frame rate readout mode. AF1 allows 1/60s and 1/50s output, and AF2 allows 1/120s and 1/100s output, so these modes are effective for raising the auto focus (AF) speed. Top frame shift region Cut-out region Bottom high-speed sweep region – 12 – Number of effective lines in high frame rate readout mode 215 ICX406AQF Definition of standard imaging conditions (1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. (2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (3)Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diagram. 1. G Sensitivity, sensitivity comparison Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screen, and substitute the values into the following formulas. VG = (VGr + VGb) /2 Sg = VG × 100 [mV] 30 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula. ( Sm = 20 × log Vsm ÷ Gra + Gba + Ra + Ba 1 1 × × 4 500 10 ) [dB] (1/10V method conversion value) 4. Video signal shading Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value (Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the following formula. SHg = (Grmax – Grmin) /150 × 100 [%] – 13 – ICX406AQF 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the values into the following formula. Lci = ∆Gli × 100 [%] (i = r, g, b) Gai 8. Lag Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) × 100 [%] VD V1A/V1B Light Strobe light timing Gr signal output 150mV Output – 14 – Vlag (lag) ICX406AQF Drive Circuit –7.5V 15V 3.3V 100k 0.1 1/35V 1 20 XSUB 2 19 XV3 3 18 XSG3B 4 17 XSG3A 5 0.1 16 CXD3400N XV1 6 15 XSG1B 7 14 XSG1A 8 13 XV4 9 12 XV2 10 11 0.1 Vφ3B Vφ2 Vφ1A 7 8 9 10 GND Vφ4 6 CCD OUT VOUT 5 TEST 4 Vφ1B 3 TEST 2 Vφ3A 2SC4250 1 4.7k ICX406 (BOTTOM VIEW) VR1 (2.7k) VDD φRG Hφ2 Hφ1 GND φSUB CSUB VL VSUB Cont. Hφ1 Hφ2 3.3/20V 0.01 20 19 18 17 16 15 14 13 12 11 Hφ2 Hφ1 φRG 0.1 Substrate bias control signal VSUB Cont. Substrate bias φSUB pin voltage 0.1 200k Mechanical shutter mode tf ≈ 4ms tr ≈ 2ms 3.3/16V 0.1 GND Internally generated value VSUB Notes) Substrate bias control 1. The saturation signal level decreases when exposure is performed using the mechanical shutter, so control the substrate bias. 2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting a 2.7kΩ grounding registor to the CCD CSUB pin. Drive timing precautions 1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shitter, so do not ground the connected 2.7kΩ resistor. 2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the substrate bias control signal is not set to high level 10ms before entering the exposure period and the 2.7kΩ resistor connected to the CSUB pin is not grounded. 3. The blooming signal generated during exposure in mechanical shutter mode is swept by providing two fields or more of idle transfer through vertical register high-speed sweep transfer from the time the mechanical shutter closes until sensor readout is performed. However, note that the VL potential and the φSUB pin DC voltage sag at this time. – 15 – Drive Timing Chart (Vertical Sequence) Act. High Frame Rate Readout Mode → Frame Readout Mode/Electronic Shutter Normal Operation High frame rate readout mode Frame readout mode Exposure operation High frame rate readout mode VD V1A V1B V2 V3A – 16 – V3B V4 SUB A B B C D E TRG Mechanical shutter OPEN CLOSE OPEN VSUB Cont. A signal output A signal output B signal output B signal output C signal output (ODD) C signal output (EVEN) Output after frame readout D signal output E signal output Note) The B output signal contain a blooming component and should therefore not be used. Apply 20 or more electronic shutter pulses at the start of exposure for the recording image. If less than 20 pulses are applied, the electronic shutter may occur a discharge error. ICX406AQF CCD OUT Drive Timing Chart (Vertical Sync) NTSC/PAL Frame Readout Mode NTSC: 3.33 frame/s, PAL: 3.57 frame/s Exposure period All pixels output period VD 1890 2026 1 1 2 2 3 3 1887 1955 1888 1956 942 943 942 943 1028 1096 83 83 1022 1090 76 77 76 77 "c" 1020 1088 73 73 "a" 1018 1086 10 10 "c" 954 1022 955 1023 1 2 3 PAL 945 1013 946 1014 NTSC 1 2 3 HD "b" V1A/V1B V2 V4 SUB TRG Mechanical shutter OPEN CLOSE OPEN 1718 1720 2 4 6 8 10 12 2 4 6 8 10 CCD OUT 1717 1719 VSUB Cont. 1 3 5 7 9 11 1 3 5 7 9 – 17 – V3A/V3B Note) The 1013H and 2026H horizontal period in NTSC mode are 1672clk, the 945H and 1890H horizontal period in PAL mode are 464clk. ICX406AQF Drive Timing Chart (Readout) NTSC/PAL Frame Readout Mode "a" Enlarged NTSC: #76 PAL: #76 NTSC: #77 PAL: #77 60 317 1200 1260 2669 1 317 60 2669 1 H1 1292 V1A/V1B 188 156 252 V2 220 V3A/V3B 1104 1202 124 284 V4 – 18 – "b" Enlarged NTSC: #1088 PAL: #1020 1136 NTSC: #1089 PAL: #1021 V1A/V1B V2 V3A/V3B 1168 V4 ICX406AQF Drive Timing Chart (High-speed Sweep Operation) NTSC/PAL Frame Readout Mode "c" Enlarged 194837clk = 73 lines HD 1 60 V1A/V1B – 19 – V2 V3A/V3B V4 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 #1 #2 #3 #4 28 28 28 28 #1739 ICX406AQF Drive Timing Chart (Horizontal Sync) NTSC/PAL Frame Readout Mode 317 345 361 257 1 28 1 16 60 2669 1 5 3 364 Ignored pixel 2 bits Ignored pixel 2 bits 56 1 1 CLK H1 H2 RG – 20 – SHP SHD 1 V1A/V1B 32 1 1 129 96 1 96 1 1 160 V3A/V3B 1 97 160 1 V4 1 1 64 1 SUB 65 1 96 V2 1 108 33 64 1 85 ICX406AQF Drive Timing Chart (Vertical Sync) NTSC/PAL High Frame Rate Readout Mode NTSC: 30 frame/s, PAL: 25 frame/s VD "d" 9 10 9 10 270 226 1 1 218 218 9 10 9 10 PAL 270 226 1 1 2 2 3 3 4 4 5 5 NTSC 218 218 HD "d" V1A V1B V2 V3B 10 5 14 21 30 37 46 53 62 69 78 85 94 1 6 1 10 17 26 33 42 49 58 65 74 81 90 1706 1710 1713 1717 1 6 1 10 17 26 33 42 49 58 65 74 81 90 CCD OUT 10 5 14 21 30 37 46 53 62 69 78 85 94 V4 1706 1710 1713 1717 – 21 – V3A ICX406AQF Note) The 226H and 225H horizontal period in NTSC mode are 1372clk, the 270H in PAL mode is 2039clk. Drive Timing Chart (Readout) NTSC/PAL High Frame Rate Readout Mode "d" Enlarged #1 #2 V1A 1260 60 317 1356 1416 1136 2669 1 317 60 2669 1 H1 68 68 V1B 1202 1324 84 V2 – 22 – 1200 V3A 1104 1292 60 V3B 60 1168 V4 1358 76 ICX406AQF Drive Timing Chart (Horizontal Sync) NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode 317 345 361 257 1 28 1 16 60 2669 1 5 3 364 Ignored pixel 2 bits Ignored pixel 2 bits 56 1 1 CLK H1 H2 RG – 23 – SHP SHD 1 8 V1A/V1B 1 1 24 V2 1 1 V3A/V3B 1 16 24 24 1 24 24 1 1 1 1 108 24 24 1 24 24 1 1 1 17 40 40 24 1 1 1 1 1 1 SUB 24 33 40 40 40 24 1 1 1 1 1 24 40 40 40 40 1 1 1 1 1 1 40 40 40 1 1 1 24 1 V4 40 24 25 40 1 9 64 1 85 ICX406AQF Drive Timing Chart (Vertical Sync) NTSC/PAL AF1 Mode NTSC: 60 frame/s, PAL: 50 frame/s VD "g" "e" 9 10 9 10 113 1 106 128 "f" 135 1 9 10 113 1 2 3 4 5 PAL 9 10 NTSC 135 1 2 3 4 5 HD "g" "e" "f" V1A V1B V2 V3B 469 478 485 494 469 478 485 494 465 474 481 490 465 474 481 490 10 6 10 469 478 485 494 465 474 481 490 PAL 6 10 CCD OUT 1226 1230 1233 1237 469 478 485 494 465 474 481 490 NTSC 1402 1406 1409 1413 10 6 V4 6 – 24 – V3A ICX406AQF Note) The 113H horizontal period in NTSC mode is 1372clk, the 135H horizongal period in PAL mode is 2354clk. Drive Timing Chart (Vertical Sync) NTSC/PAL AF2 Mode NTSC: 120 frame/s, PAL: 100 frame/s VD "e" 9 10 9 10 57 1 47 58 "h" 68 1 9 10 57 1 2 3 4 5 PAL "i" 9 10 NTSC 68 1 2 3 4 5 HD "i" "e" "h" V1A V1B V2 V3B 10 725 734 741 750 6 721 730 737 746 10 725 734 741 750 721 730 737 746 PAL 6 CCD OUT 986 990 993 997 725 734 741 750 721 730 737 746 725 734 741 750 721 730 737 746 NTSC 1073 1077 1082 1086 10 6 10 V4 6 – 25 – V3A ICX406AQF Note) The 57H horizontal period in NTSC mode is 686clk, the 68H horizontal period in PAL mode is 1177clk. Drive Timing Chart (Readout) NTSC/PAL AF1 Mode, AF2 Mode "e" Enlarged V1A 1260 1456 1520 317 1356 1416 1136 60 2669 1 317 60 2669 1 H1 68 68 V1B 1480 1544 – 26 – 1202 1324 1472 1536 84 V2 1496 1560 1200 1104 1292 1488 1552 60 V3A V3B 60 1448 1512 1168 1358 1504 1568 V4 76 1464 1528 ICX406AQF Drive Timing Chart NTSC/PAL AF1 Mode "f" Enlarged 16014clk = 6 lines HD 1 60 V1A/V1B V2 V3A/V3B – 27 – V4 #1 #2 #3 #4 #228 8 8 8 8 8 8 8 8 ICX406AQF Drive Timing Chart NTSC/PAL AF1 Mode "g" Enlarged 16014clk = 6 lines NTSC: 107H PAL: 129H NTSC: 113H PAL: 135H NTSC: 1H PAL: 1H HD 1 60 V1A/V1B V2 – 28 – V3A/V3B V4 #1 #2 #3 #4 #244 8 8 8 8 8 8 8 8 ICX406AQF Drive Timing Chart NTSC/PAL AF2 Mode "h" Enlarged 24021clk = 9 lines HD 1 60 V1A/V1B V2 V3A/V3B – 29 – V4 #1 #2 #3 #4 #356 8 8 8 8 8 8 8 8 ICX406AQF Drive Timing Chart NTSC/PAL AF2 Mode "i" Enlarged 24021clk = 9 lines NTSC: 48H PAL: 59H NTSC: 57H PAL: 68H NTSC: 1H PAL: 1H HD 1 60 V1A/V1B V2 – 30 – V3A/V3B V4 #1 #2 #3 #4 #364 8 8 8 8 8 8 8 8 ICX406AQF ICX406AQF Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N 50N 1.2Nm Plastic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 31 – ICX406AQF c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same. Structure A Structure B Package Chip Metal plate (lead frame) Cross section of lead frame The cross section of lead frame can be seen on the side of the package for structure A. – 32 – Package Outline Unit: mm 20 pin SOP 0.25 A 6.9 11 20 20 11 0.8 1.7 14.0 ± 0.15 C 0˚ to 1.7 10˚ H 1 1.7 1.7 V 6.0 9.0 0.5 ~ 2.5 B 12.0 ± 0.1 10.9 ~ 2.5 (0.6) D 0.15 10 12.7 10 1 0.5 2.5 10.0 0.8 ~ 1. “A” is the center of the effective image area. 2.4 – 33 – 1.0 ± 0.1 B' 0.3 1.27 0.3 M 2.9 ± 0.15 13.8 ± 0.1 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.9, 6.0) ± 0.075mm. 5. The rotation angle of the effective image area relative to H and V is ±0.7˚. PACKAGE STRUCTURE 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm. Plastic LEAD TREATMENT GOLD PLATING 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm. LEAD MATERIAL 42 ALLOY 8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5. PACKAGE MASS 0.95g DRAWING NUMBER AS-B7-03(E) 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. ICX406AQF Sony Corporation PACKAGE MATERIAL