ICX409AL Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras Description The ICX409AL is an interline CCD solid-state image sensor suitable for CCIR B/W video cameras with a diagonal 6mm (Type 1/3) system. Compared with the conventional product ICX059CL, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is suitable for applications such as surveillance cameras, automotive cameras, etc. Features • High sensitivity (+5dB compared with the ICX059CL) • Low smear (–15dB compared with the ICX059CL) • High D range (+5dB compared with the ICX059CL) • High S/N • High resolution and low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter • No voltage adjustment (Reset gate and substrate bias are not adjusted.) • Reset gate: 5V drive • Horizontal register: 5V drive 16 pin DIP (Plastic) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 2 V 3 Pin 9 H 12 40 Optical black position (Top View) Device Structure • Interline CCD image sensor • Image size: Diagonal 6mm (Type 1/3) • Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels • Total number of pixels: 795 (H) × 596 (V) approx. 470K pixels • Chip size: 5.59mm (H) × 4.68mm (V) • Unit cell size: 6.50µm (H) × 6.25µm (V) • Optical black: Horizontal (H) direction : Front 3 pixels, rear 40 pixels Vertical (V) direction : Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon ∗Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (HoleAccumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00612A14-PS NC GND Vφ1 Vφ2 Vφ3 Vφ4 8 7 6 5 4 3 2 1 Vertical Register NC Block Diagram and Pin Configuration (Top View) VOUT ICX409AL Note) Horizontal Register 9 10 11 12 13 14 15 16 VDD GND φSUB VL φRG NC Hφ1 Hφ2 Note) Pin Description Pin No. Symbol Description Pin No. : Photo sensor Description Symbol 1 Vφ4 Vertical register transfer clock 9 VDD Supply voltage 2 Vφ3 Vertical register transfer clock 10 GND GND 3 Vφ2 Vertical register transfer clock 11 φSUB Substrate clock 4 Vφ1 Vertical register transfer clock 12 VL Protective transistor bias 5 GND GND 13 φRG Reset gate clock 6 NC 14 NC 7 NC 15 Hφ1 Horizontal register transfer clock 8 VOUT 16 Hφ2 Horizontal register transfer clock Signal output Absolute Maximum Ratings Item Against φSUB Against GND Against VL Ratings Unit VDD, VOUT, φRG – φSUB –40 to +8 V Vφ1, Vφ3 – φSUB –50 to +15 V Vφ2, Vφ4, VL – φSUB –50 to +0.3 V Hφ1, Hφ2, GND – φSUB –40 to +0.3 V VDD, VOUT, φRG – GND –0.3 to +20 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –10 to +18 V Hφ1, Hφ2 – GND –10 to +6 V Vφ1, Vφ3 – VL –0.3 to +28 V Vφ2, Vφ4, Hφ1, Hφ2, GND – VL –0.3 to +15 V to +15 V Voltage difference between vertical clock input pins Between input clock pins Hφ1 – Hφ2 –6 to +6 V –14 to +14 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Hφ1, Hφ2 – Vφ4 ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Remarks ∗1 ICX409AL Bias Conditions Symbol Item Supply voltage VDD Protective transistor bias VL Substrate clock φSUB Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Remarks ∗2 ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. DC Characteristics Item Symbol Supply current Min. IDD Typ. Max. Unit 4 6 mA Remarks Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.0 –7.0 –6.5 V 2 VVL = (VVL3 + VVL4)/2 VφV 6.3 7.0 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Symbol Substrate clock voltage VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.3 V 2 High-level coupling VVHL 0.3 V 2 High-level coupling VVLH 0.3 V 2 Low-level coupling VVLL 0.3 V 2 Low-level coupling VφH 4.75 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 4.5 5.0 5.5 V 4 Input through 0.1µF capacitance VRGLH – VRGLL 0.4 V 4 Low-level coupling VRGL – VRGLm 0.5 V 4 Low-level coupling VφRG Reset gate clock voltage Remarks VRGH VDD +0.3 VDD +0.6 VDD +0.9 V 4 VφSUB 21.0 22.0 23.5 V 5 –3– ICX409AL Clock Equivalent Circuit Constant Symbol Item Min. Typ. Max. Unit CφV1, CφV3 1500 pF CφV2, CφV4 1000 pF CφV12, CφV34 820 pF CφV23, CφV41 330 pF CφV13 120 pF CφV24 100 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 75 pF Capacitance between horizontal transfer clocks CφHH 22 pF Capacitance between reset gate clock and GND CφRG 5 pF Capacitance between substrate clock and GND CφSUB 270 pF R1, R3 100 Ω R2, R4 150 Ω Vertical transfer clock ground resistor RGND 68 Ω Horizontal transfer clock series resistor RφH 15 Ω Reset gate clock series resistor RφRG 50 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vφ1 Remarks Vφ2 CφV12 R1 R2 RφH RφH Hφ2 Hφ1 CφV1 CφHH CφV2 CφV41 CφV23 CφH1 CφH2 CφV13 CφV24 CφV4 RGND CφV3 R4 R3 CφV34 Vφ4 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RφRG RGφ CφRG Reset gate clock equivalent circuit –4– ICX409AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –5– VVL ICX409AL (3) Horizontal transfer clock waveform tr twh tf 90% twl VφH 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl Point A VφRG RG waveform VRGLH VRGL VRGLL VRGLm Hφ1 waveform VφH/2 [V] VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB 10% 0% VSUB (A bias generated within the CCD) tr twh –6– φM 2 tf ICX409AL Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 Readout clock Horizontal transfer clock twl twh 0.5 µs 0.5 26 28.5 26 28.5 6.5 9.5 6.5 9.5 Hφ2 26 28.5 26 28.5 6.5 9.5 6.5 9.5 During Hφ1 parallel-serial Hφ2 conversion 5.38 0.01 0.01 5.38 0.01 0.01 51 3 3 Reset gate clock φRG 11 Substrate clock φSUB 1.5 1.8 13 During readout 250 ns ∗1 15 Hφ1 During imaging Unit Remarks µs ns 0.5 0.5 ns ∗2 µs During drain charge ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V]. Item Horizontal transfer clock Symbol Hφ1, Hφ2 two Min. Typ. 22 26 Max. Unit Remarks ns ∗3 ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. –7– ICX409AL Image Sensor Characteristics Item (Ta = 25°C) Symbol Min. Typ. Sensitivity S 680 850 Saturation signal Vsat 1000 Smear Sm Video signal shading SH Dark signal Max. Unit Measurement method mV 1 mV 2 –93 dB 3 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II' Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 2 % 7 Lag Lag 0.5 % 8 –110 Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 Zone 0, I Zone II, II' V 10 582 (V) 6 Ignored region Effective pixel region –8– Remarks Ta = 60°C ICX409AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 20 × log 1 YSm 1 × × 10 200 500 [dB] (1/10V method conversion value) –9– ICX409AL 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/200) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD V1 Light Strobe light timing Signal output 200mV Output – 10 – Vlag (lag) RG Hφ1 Hφ2 XV4 XSG2 XV3 XSG1 XV1 XV2 XSUB CXD1267AN 16 5 13 12 11 8 9 10 22/20V 14 7 15 17 4 6 19 18 22/16V 0.1 1/20V 100k 1/35V ICX409 (BOTTOM VIEW) 8 7 6 5 4 3 2 1 0.1 Vφ4 Hφ2 16 15 14 13 12 11 10 NC 2 Vφ2 Vφ3 Hφ1 φRG 3 100k Vφ1 VL 20 GND φSUB 1 NC NC 15V VOUT GND – 11 – 9 VDD Drive Circuit 3.3/20V 0.01 2200p 3.9k 2SK523 100 3.3/16V 1M [∗A] CCD OUT –7.0V ICX409AL ICX409AL Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 700 600 800 900 1000 Wave Length [nm] Sensor Readout Clock Timing Chart V1 2.6 V2 Odd Field V3 V4 33.6 1.5 2.6 2.6 2.6 0.2 V1 V2 Even Field V3 V4 Unit : µs – 12 – – 13 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 581 582 625 1 2 3 4 5 620 Drive Timing Chart (Vertical Sync) 15 24 6 1 3 5 2 4 6 1 3 5 315 582 581 330 1 3 5 2 4 6 335 1 3 5 2 4 6 ICX409AL 340 325 320 310 25 20 10 – 14 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 30 20 10 750 752 1 3 5 745 Drive Timing Chart (Horizontal Sync) ICX409AL 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 ICX409AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) AAAA AAAA AAAA AAAA AAAA AAAA Cover glass 50N 50N 1.2Nm Plastic package Compressive strength – 15 – Torsional strength ICX409AL b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. – 16 – – 17 – 1.2 2.5 0.69 ~ ~ DRAWING NUMBER PACKAGE MASS LEAD MATERIAL LEAD TREATMENT PACKAGE MATERIAL 0.3 M 1.27 9.2 10.3 12.2 ± 0.1 H AS-C2.2-01(E) 0.90g 42 ALLOY GOLD PLATING Plastic V 6.1 ~ 2.5 0.46 0.3 A 1.2 2.5 8.4 (For the first pin only) 0.5 PACKAGE STRUCTURE B 5.7 D B' C 1 8 11.6 16 9 2.5 2-R0.5 9. The notches on the bottom of the package are used only for directional index, they must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 50µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (6.1, 5.7) ± 0.15mm. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. 16pin DIP (450mil) 9.5 11.4 ± 0.1 3.1 Unit: mm 3.35 ± 0.15 1.27 3.5 ± 0.3 0° to 9° 0.25 11.43 Package Outline ICX409AL Sony Corporation