ILX103A 3000-pixel CCD Linear Image Sensor (B/W) Description The ILX103A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. Features • Number of effective pixels: 3000 pixels • Pixel size: 7µm × 200µm (7µm pitch) • S/H output • Built-in timing generator and clock-drivers • Output amplifier gain switching function (2-level: switching gain ratio 1:4) • SIP small package • Clock frequency: 500kHz (Typ.), 100kHz (Min.), 1MHz (Max.) 10 9 5 Driver Readout gate CCD analog shift register CCD analog shift register Readout gate Driver 13 Timing generator Readout gate pulse generator Shutter pulse generator 14 11 12 1 2 Vgg Vout 3 6 Output Amplifier 4 NC NC NC GND SWG T1 φCLK VDD Vgg VDD Vout GND GND φROG VDD 9 10 11 12 13 14 15 16 φSHUT 8 SWG 7 D24 D25 1 3000 GND 6 D54 D55 S1 S2 S3 VDD 5 T1 VDD 4 S2999 S3000 D56 3 φCLK GND D65 2 φROG VDD V °C °C φSHUT 6 –10 to +60 –30 to +80 Pin Configuration (Top View) 1 15 Internal Structure GND Absolute Maximum Ratings • Supply voltage VDD • Operating temperature • Storage temperature 16 pin SIP (Ceramic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98X48A91-PS ILX103A Pin Description Pin No. Symbol Description 1 VDD Power supply 2 GND GND 3 Vout Signal output 4 Vgg Output circuit gate bias 5 φCLK Clock pulse input 6 SWG Control (Output circuit amplification factor ×4/×1) 7 NC NC 8 NC NC 9 φROG Readout gate pulse input 10 φSHUT Electrical shutter pulse input 11 GND GND 12 VDD Power supply 13 T1 TEST (Connect to GND with 1000pF capacitor) 14 VDD Power supply 15 GND GND 16 NC NC Mode Description Output circuit gain Pin 6 SWG High VDD Low GND Recommended Voltage Item Min. Typ. Max. Unit VDD 4.5 5.0 5.5 V Input Pin Capacity Item Symbol Min. Typ. Max. Unit Input capacity of φCLK pin CφCLK — 10 — pF Input capacity of φROG pin CφROG — 10 — pF Input capacity of φSHUT pin CφSHUT — 10 — pF –2– ILX103A Electro-optical Characteristics (Analog Characteristic) (Note 1) Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Output circuit gain low mode Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 52.5 75 97.5 V/(lx · s) Note 2 Sensitivity 2 R2 — 925 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 5.0 10.0 % Note 4 Saturation output voltage VSAT 0.6 0.8 — V — Dark voltage average VDRK — 2.5 6.0 mV Note 5 Dark signal nonuniformity DSNU — 5.0 12.0 mV Note 6 Image lag IL — 5.0 — % Note 7 Dynamic range DR — 320 — — Note 8 Saturation exposure SE — 0.01 — lx · s Note 9 5V current consumption IVDD — 7.0 17.0 mA — Total transfer efficiency TTE 92.0 97.0 — % — Output impedance ZO — 250 — Ω — Offset level VOS — 2.5 — V Note 10 Note) 1. In accordance with the given electro-optical characteristics, the even black level is defined as the average value of D24, D25 to D53. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. Light source: LED λ = 660nm 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = 5. 6. 7. 8. 9. 10. (VMAX – VMIN)/2 VAVE × 100 [%] The maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. Integration time is 10ms. The difference between the maximum and average values and the difference between the minimum and average values of the dark output voltage is calculated. The larger value is defined as dark signal nonuniformity. Integration time is 10ms. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. DR = VSAT/VDRK When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in proportion to optical integration time. SE = VSAT/R1 Vos is defined as indicated below. D51 D52 D53 D54 Vout VOS GND –3– D55 S1 –4– 0 5 0 5 0 VOUT φCLK φSHUT φROG 5 –1 0 1 2 3100 or more clock pulses are required. 1-Line output period (3066 pixels) Dummy signal (10 pixels) S2997 S2998 S2999 S3000 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 Effective picture elements signal (3000 pixels) D53 D54 D55 S1 S2 S3 S4 Optical black (30 pixels) D21 D22 D23 D24 Dummy signal (55 pixels) D1 D2 D3 D4 D0 Clock Timing Diagram ILX103A ILX103A Input Clock Voltage Condition Item Min. Typ. Max. Unit VIH 3.0 VDD 5.5 V VIL 0.0 — 0.1 V ∗ This is applied to the all external pulses. (φCLK, φROG, φSHUT) φCLK Timing (For all modes) t1 t2 φCLK t3 t4 Item Symbol φCLK pulse rise/fall time φCLK pulse Duty∗1 t1, t2 — Min. Typ. Max. Unit 0 10 100 ns 40 50 60 % Min. Typ. Max. Unit 1/8τ 1/4τ 3/8τ ns 1/8τ 1/4τ 3/8τ ns 0 10 100 ns 6τ 10τ 20τ ns ∗1 100 × t4/ (t3 + t4) φROG, φCLK Timing φROG t6 φCLK t7 t5 t9 Item φROG, φCLK pulse timing 1 φROG, φCLK pulse timing 2 φROG pulse rise/fall time φROG pulse period t8 Symbol t5 t9 t6, t8 t7 Note) τ is the period of φCLK. –5– ILX103A φSHUT, φCLK Timing φSHUT t11 t12 t13 t15 φCLK t14 Item Symbol φSHUT pulse rise/fall time t11, t13 t12 t14 t15 φSHUT pulse period φSHUT, φCLK pulse timing 1 φSHUT, φCLK pulse timing 2 Min. Typ. Max. Unit 0 10 100 ns 4000 5000 — ns 150 200 250 ns 150 200 250 ns Min. Typ. Max. Unit — 230 — ns Note) The high periods of φROG and φSHUT are separated for 10τ or more. φCLK Output Signal Timing ∗1 ∗2 φCLK t16 Vout Item φCLK-Vout output delay time1 Symbol t16 ∗1 fck = 500kHz, φCLK Duty = 50%, φCLK rise/fall time = 10ns ∗2 is data period. –6– ILX103A 5V NC 8 GND NC 7 VDD NC 6 ∗2 SWG 5 T1 φCLK 4 VDD Vgg 3 GND Vout 2 φSHUT GND 1 φROG VDD Application Circuit (Output gain low mode)∗1 9 10 11 12 13 14 15 16 0.01µ 1000p 1µ/16V Signal output 22µ/10V 3kΩ 2SA1175 φCLK φROG φSHUT ∗1 This circuit diagram is the case when output circuit gain is low. ∗2 Connect T1 (Pin 13) to GND with 1000pF capacitor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– ILX103A Example of Representative Characteristics (VDD = 5V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 10 9 Relative sensitivity 8 7 6 5 4 3 2 1 0 400 500 600 800 700 900 1000 Wavelength [nm] Output voltage vs. Temperature characteristics (Standard characteristics) 10 Output voltage rate 5 1 0.5 0.1 0.05 0.01 –10 0 10 20 30 Ta – Ambient temperature [°C] –8– 40 50 60 ILX103A Offset level vs. Temperature characteristics (Standard characteristics) Offset level vs. VDD characteristics (Standard characteristics) 5 Ta = 25°C ∆Vos ~ – –2.1mV/°C ∆Ta 4 VOS – Offset level [V] VOS – Offset level [V] 5 3 2 1 0 –10 0 10 30 20 40 50 3 2 ∆Vos ~ – 0.49 ∆VDD 1 0 4.5 60 5 5.5 Ta – Ambient temperature [°C] VDD [V] Supply current vs. VDD characteristics (Standard characteristics) Output voltage vs. Integration time (Standard characteristics) 14 10 Ta = 25°C 12 Output voltage rate IVDD – Supply current [mA] 4 10 8 6 4 5 2 0 4.5 5 1 5.5 10 50 τ – Integration time [ms] VDD [V] –9– 100 ILX103A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-SIP Packages The following points should be observed when handling and installing cer-SIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.5mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N 0.9Nm (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 10 – ILX103A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. – 11 – – 12 – 1.27 V 1 H Cer-SIP TIN PLATING 42 ALLOY 1.3g LS-D4(E) LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER No.1 Pixel PACKAGE MATERIAL PACKAGE STRUCTURE 2.23 ± 0.3 4.65 ± 0.8 Unit: mm 5.08 21.0 (7µm × 3000Pixels) 30.3 ± 0.3 16 0.4 0.3 M 5.0 ± 0.2 0.25 2.4 3.2 ± 0.5 1.325 ± 0.3 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 1.6 ± 0.3mm. 16pin SIP 4.2 4.0 Package Outline ILX103A