ILX523A 2700 pixel CCD Linear Sensor (B/W) Description The ILX523A is a reduction type CCD linear sensor designed for facsimile, scanner and OCR use. This sensor reads A3 size documents at a density of 200 DPI (Dot Per Inch). In addition, this can be directly driven at 5V logic and operate on single 12V power supply for easy use. D33 S1 S2 Pin Configuration (Top View) φ1 9 14 φ2 NC 10 13 NC 2700 12 NC φROG 9 φ1 14 φ2 VDD 20 φS/H 4 φROG 11 GND 15 NC VOUT 16 NC NC 8 2 NC 7 1 17 NC • Output Amplifier • Sample-and-Hold Circuit • Feed Through Level Clamp Circuit 18 φRS NC 6 18 NC 5 φRS 19 T1 T1 20 VDD φS/H 4 Timing Generator NC 3 21 NC AA AA 22 NC 1 19 VSS 2 D14 D15 VOUT 1 11 Timing Generator V °C °C Read Out gate CCD Analog Shift Register S2699 S2700 D34 Absolute Maximum Ratings 15 • Supply voltage VDD • Operating temperature –10 to +60 • Storage temperature –30 to +80 Block Diagram D39 Features • Number of effective pixels: 2700 pixels • Pixel size: 11µm × 11µm (11µm pitch) • Ultra low lag/High Sensitivity • Built-in Feed through suppression circuit • Built-in Sample-and-hold circuit • Maximum data rate: 5MHz • Single 12V power supply 22 pin DIP (Cer-DIP) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97442A78 ILX523A Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 VOUT Signal output 12 NC NC 2 GND GND 13 NC NC 3 NC NC 14 φ2 Transfer pulse 2 4 φS/H Sample-and-Hold pulse 15 NC NC 5 NC NC 16 NC NC 6 NC NC 17 NC NC 7 NC NC 18 φRS Reset gate pulse 8 NC NC 19 T1 Test pin (Open) 9 φ1 Transfer pulse 1 20 VDD 12V power supply 10 NC NC 21 NC NC 11 φROG Read out gate pulse 22 NC NC Note) Connect Pin 4 to GND when not using internal sample-and-hold circuit. Recommended Pin Voltage Item Min. Typ. Max. Unit VDD 11.4 12.0 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacitance of φ1 Cφ1 — 300 — pF Input capacitance of φ2 Cφ2 — 300 — pF Input capacitance of φROG CφROG — 10 — pF Input capacitance of φRS CφRS — 10 — pF Input capacitance of φS/H CφS/H — 10 — pF — 1.0 5.0 MHz Data Rate — –2– ILX523A Electrooptical Characteristics (Ta = 25°C, VDD = 12V, data rate = 1MHz, mode without S/H (Pin 4 = GND), light source = 3200K, IR cut filter CM-500S (t = 1.0mm) used) Item Symbol Min. Typ. Max. Unit Remarks 66.5 95 123.5 V/(lx · s) Note 1 Sensitivity R1 Sencitivity nonuniformity PRNU — 2.0 10.0 % Note 2 Saturation output voltage VSAT 2.0 2.5 — V — Dark voltage average VDRK — 2.0 8.0 mV Note 3 Dark signal nonuniformity DSNU — 7.0 14.0 mV Note 3 Image Lag IL — 0.02 — % Note 4 Dynamic range DR — 1250 — — Note 5 Saturation exposure SE — 0.02 — lx · s Note 6 Supply current IVDD — 15.0 25.0 mA — Total transfer efficiency TTE 92.0 98.0 — % — Output impedance ZO — 300 — Ω — Offset level VOS — 7.4 — V Note 7 Notes) 1. For the sensitivity test, light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. The output signal amplitude for test is 1V. PRNU = (VMAX – VMIN)/2 VAVE × 100 [%] The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 3. Optical signal accumulated time stands at 10ms. 4. Output signal amplitude VOUT = 500mV. 5. Dynamic range is defined as follows. DR = VSAT VDRK When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. 6. Saturation exposure is defined as follows. SE = VSAT R1 7. VOS is defined as indicated below. VOUT D29 D30 D31 D32 VOS GND –3– AA AAA AAAAA D33 S1 –4– VOUT φRS φ2 φ1 0 5 0 5 0 5 1 2 3 D3 4 5 6 D12 D13 D11 D31 D14 D15 Optical black (18 pixels) D38 D36 D37 D34 D35 S2700 S2698 S2699 S2697 S3 S4 S2 Effective picture elements signal Dummy signal (6 pixels) (2700 pixels) S1 D32 D33 Note) 2750 or more clock pulses (φ1, φ2, φRS) are required. 1-line output period (2739 pixels) Dummy signal (33 pixels) D4 D2 D1 0 D6 φROG D5 5 2739 D39 Clock Timing Diagram (without internal sample-and-hold circuit) 1 2 ILX523A –5– VOUT φS/H φRS φ2 0 5 0 5 0 5 0 1 2 D2 φ1 3 4 D4 5 D3 0 5 6 D31 D15 Optical black (18 pixels) D14 D12 D13 D11 D38 D36 D37 D35 S2700 D34 S2698 S2699 S2697 S2 S3 S1 Effective picture elements signal Dummy signal (6 pixels) (2700 pixels) S4 D32 D33 Note) 2750 or more clock pulses (φ1, φ2, φRS, φS/H) are required. 1-line output period (2739 pixels) Dummy signal (33 pixels) D6 φROG D5 5 2739 D39 D1 Clock Timing Diagram (using internal sample-and-hold circuit) 1 2 ILX523A ILX523A Input Clock Waveform Conditions φ1, φ2, φRS, φS/H pulses related t1 5V t2 90% φ1 10% 0V 5V 90% φ2 10% 0V t5 t4 5V t6 90% φRS 50% 10% 0V t10 t3 t8 t11 t9 5V 90% φS/H 50% 10% 0V t7 VOUT (without internal sample-and-hold circuit) 10% t13 t12 t19 VOUT (using internal sample-and-hold circuit) φROG, φ1 pulses related t17 5V t18 90% φROG 50% 10% 0V t14 t16 t15 5V φ1 50% 0V –6– ILX523A Cross point φ1 and φ2 φ1 5V φ2 0V 2.0V (Min.) 2.0V (Min.) Input Clock Waveform Conditions Symbol Item Min. Typ. Max. Unit 100 ns 200 ns 350 ns φ1, φ2 rise/fall time t1, t2 0 φRS pulse low level period t3 20 50 80∗1 φ1, φ2 – φRS pulse timing t4 25 200∗1 φRS rise/fall time t5, t6 0 φS/H pulse low level period t7 φ1, φ2 – φS/H pulse timing 40 ns 20 10 80∗1 200 ns t8 70 200∗1 350 ns φRS – φS/H pulse timing t9 15 — — ns φS/H rise/fall time t10, t11 0 10 40 ns t12 — 40 — ns t13 — 20 — ns t19 — 20 — ns φROG pulse high level period t14 500 1000 — ns φ1 – φROG pulse timing t15, t16 500 1000 — ns φROG rise/fall time t17, t18 0 50 100 ns High level 4.5 5 5.5 V Low level 0 — 0.5 V Signal output delay time Inpuyt clock pulse voltage ∗1 Recommended conditions for data rate = 1MHz. –7– –8– 74HC04 Connect Pin 4 to GND or φROG when not using internal sample-and-hold circuit. φ2 φROG φ1 φS/H φRS 0.01µ 10µ/16V 5V Output signal 10kΩ 3 4 7 6 5 8 9 10 11 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2SC2785 2 1 12 13 14 15 16 17 18 19 20 21 10µ/16V 22 0.01µ 12V NC VOUT NC GND VDD NC T1 φS/H φRS NC NC NC NC NC NC NC φ2 φ1 NC NC NC φROG Application Circuit ILX523A ILX523A Example of Representative Characteristics (VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 10 9 8 Relative sensitivity 7 6 5 4 3 2 1 0 400 500 600 700 800 900 1000 Wavelength [nm] Dark signal output temperature characteristics (standard characteristics) 100 50 Output voltage rate 10 5 1 0.5 0.1 0.05 0.01 –10 0 10 20 30 Ta – Ambient temperature [°C] –9– 40 50 60 ILX523A Offset level vs. VDD characteristics (Standard characteristics) 12 12 10 10 VOS – Offset level [V] VOS – Offset level [V] Offset level vs. Temperature characteristics (Standard characteristics) 8 ∆Vos ∆Ta 6 –5mV/ °C 4 2 6 ∆Vos ∆VDD 0.8 4 2 0 –10 0 10 20 30 40 50 0 11.4 60 11.6 11.8 12.0 12.2 12.4 Ta – Ambient temperature [°C] VDD [V] Supply current vs. VDD characteristics (Standard characteristics) Output voltage vs. Integration time (Standard characteristics) 12.6 10 20 15 Output voltage rate IvDD – Supply current [mA] 8 10 5 5 1 0 11.4 11.6 11.8 12.0 12.2 12.4 12.6 10 50 τ – Integration time [ms] VDD [V] – 10 – 100 ILX523A Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing Cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N (2) (3) 0.9Nm (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 11 – ILX523A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. – 12 – 5.0 ± 0.5 – 13 – V H 6.73 ± 0.8 1 22 41.6 ± 0.5 Cer-DIP TIN PLATING 42 ALLOY 5.2g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 2.54 No.1 Pixel 40.2 11 12 0.51 22pin DIP (400mil) 29.7 (11µm × 2700Pixels) PACKAGE MATERIAL PACKAGE STRUCTURE 4.0 ± 0.5 Unit: mm 10.0 ± 0.5 9.0 0.3 M 3.65 4.45 ± 0.5 Package Outline 0.25 0° to 9° (AT STAND OFF) 10.16 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm. ILX523A