ILX532A 7500-pixel CCD Linear Sensor (B/W) Description The ILX532A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600DPI, at high speed. 28 pin DIP (Cer-DIP) Features • Number of effective pixels: 7500 pixels • Pixel size: 7µm × 7µm (7µm pitch) • Clamp circuit are on-chip • Signal output phase of two-output simultaneous-output (alternate-output is available) • Ultra high sensitivity/Ultra low lag • Max Data Rate: 40MHz • Single 12V power supply • Input Clock Pulse: CMOS 5V drive • Package: 28 pin Cer-DIP (400mil) φ1-ODD 10 19 GND φROG 12 NC 14 7500 15 NC φROG 12 11 10 9 16 4 16 GND φ2-ODD φ1-ODD VDD φROG pulse generator GND 19 17 18 20 VDD 17 VDD VOUT-EVEN 24 NC 13 φ2-EVEN φ1-EVEN 18 φ1-EVEN VDD 11 GND 20 φ2-EVEN 3 9 φLH-ODD φ2-ODD 2 21 NC φRS-ODD 8 1 NC GND φCLP-ODD 22 NC Output amplifier 7 5 NC VOUT-ODD 23 VDD Read out gate 6 CCD analog shift register VGG 6 24 VOUT-EVEN VGG 5 Read out gate VOUT-ODD CCD analog shift register 25 VDD Output amplifier 4 23 GND VDD 26 φLH-EVEN 25 3 VDD φLH-ODD 26 2 27 27 φRS-EVEN φRS-ODD 28 1 φCLP-EVEN φRS-EVEN φLH-EVEN 28 φCLP-EVEN 1 D25 D26 φCLP-ODD D74 S1 S2 Pin Configuration (Top View) S7499 S7500 D75 V °C °C D94 Absolute Maximum Ratings • Supply voltage VDD 15 • Operating temperature –10 to +60 • Storage temperature –30 to +80 Block Diagram Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98344-PS ILX532A Pin Description Pin No. Symbol Pin No. 1 φCLP-ODD Clock pulse input (odd pixel) 15 NC NC 2 φRS-ODD Clock pulse input (odd pixel) 16 GND GND 3 φLH-ODD Clock pulse input (odd pixel) 17 VDD 12V power supply 4 GND GND 18 φ1-EVEN Clock pulse input (even pixel) 5 VOUT-ODD Signal out (odd pixel) 19 GND GND 6 VGG Output circuit gate bias 20 φ2-EVEN Clock pulse input (even pixel) 7 NC NC 21 NC NC 8 NC NC 22 NC NC 9 φ2-ODD Clock pulse input (odd pixel) 23 VDD 12V power supply 10 φ1-ODD Clock pulse input (odd pixel) 24 VOUT-EVEN Signal out (even pixel) 11 VDD 12V power supply 25 VDD 12V power supply 12 φROG Readout gate clock pulse input 26 φLH-EVEN Clock pulse input (even pixel) 13 NC NC 27 φRS-EVEN Clock pulse input (even pixel) 14 NC NC 28 φCLP-EVEN Clock pulse input (even pixel) Symbol Min. Typ. Max. Unit Cφ1, Cφ2 — 500 — pF CφLH — 10 — pF CφRS — 10 — pF CφCLP — 10 — pF CφROG — 10 — pF Description Symbol Description Recommended Supply Voltage Item VDD Min. Typ. Max. Unit 11.4 12 12.6 V Clock Characteristics Item Input capacity of φ1∗1, φ2∗1 Input capacity of φLH∗1 Input capacity of φRS∗1 Input capacity of φCLP∗1 Input capacity of φROG ∗1 It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD, φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP. Clock Frequency Symbol Min. Typ. Max. Unit φ1, φ2, φLH, φRS, φCLP fφ1, fφ2, fφLH, fφRS, fφCLP — 1 20 MHz Data rate fφR — 2 40 MHz Min. Typ. Max. Unit Low level — 0 0.1 V High level 4.75 5.0 5.25 V Input Clock Pulse Voltage Condition φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage –2– ILX532A Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 8.2 11 13.8 V/(lx · s) Note 2 Sensitivity 2 R2 — 25.1 — V/(lx · s) Note 3 Sensitivity nonuniformity PRNU — 4 10 % Note 4 Saturation output voltage VSAT 1.8 2.5 — V Note 5 Saturation exposure SE 0.13 0.23 — lx · s Note 6 Register imbalance RI — 1 7 % Note 7 Dark voltage average VDRK — 0.3 2.0 mV Note 8 Dark signal nonuniformity DSNU — 0.6 5.0 mV Note 9 Image lag IL — 0.02 — % Note 10 Supply current IVDD — 30 60 mA — Total transfer efficiency TTE 92 98 — % — Output impedance Zo — 150 — Ω — Offset level VOS — 6.5 — V Note 11 Notes) 1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. W lamp (2854K) 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. VOUT = 500mV (Typ.) PRNU = (VMAX – VMIN)/2 VAVE × 100 [%] 5. The maximum output of each odd and even pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. Use below the minimum value of the saturation output voltage. 6. Saturation exposure is defined as follows. 7. RI is defined as indicated bellow. RI = SE = VSAT R1 VOUT = 500mV (Typ.) | VODD-AVE – VEVEN-AVE | × 100 [%] VODD-AVE + VEVEN-AVE 2 ( ) Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE. Optical signal accumulated time τ int stands at 10ms. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms. 10. VOUT = 500mV (Typ.) 11. VOS is defined as indicated below. 8. 9. VOUT VOS GND –3– VOUT-EVEN VOUT-ODD S7497 S7498 S7495 S7496 S3 S4 S1 S2 D73 D74 D71 D72 D69 D70 D27 D28 D25 D26 D23 D24 D5 D6 D3 D4 D1 D2 1-line output period (7594 pixels) Note) The transfer pulses (φ1, φ2, φLH) must have more than 3797 cycles. Dummy signal (74 pixels) Optical black (48 pixels) S7499 S7500 φCLP-ODD 5 φCLP-EVEN 0 D75 D76 φRS-ODD 5 φRS-EVEN 0 D77 D78 φ2-ODD 5 φ2-EVEN 0 D79 D80 0 D81 D82 φ1-ODD φ1-EVEN 5 φLH-ODD 0 φLH-EVEN 1 D83 D84 5 2 D93 –4– D94 φROG 3 Clock Timing Chart 1 (simultaneous output) ILX532A 3797 ILX532A Clock Timing Chart 2 t4 t5 φROG t2 t6 φ1 φLH t7 t1 t3 φ2 Clock Timing Chart 3 t7 t6 φ1 φLH φ2 t10 t11 t9 φRS t8 t14 φCLP t15 t13 t12 t16 t17 VOUT Clock timing of φ1, φ2, φLH, φRS, φCLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output. –5– ILX532A Clock Timing Chart 4 Cross point φ1 and φ2 φ1 5V 1.5V (Min.) 1.5V (Min.) 2.0V (Min.) 1.5V (Min.) φ2 0V Cross point φLH and φ2 φ2 5V φLH 0V –6– 0 5 –7– VOUT-EVEN φCLP-EVEN φRS-EVEN VOUT-ODD φCLP-ODD φRS-ODD φ2-EVEN 0 0 5 5 0 5 0 5 0 5 φ1-EVEN 5 φLH-EVEN 0 φ2-ODD φ1-ODD 5 φLH-ODD 0 1 D70 D71 D69 D28 D27 D26 D24 D25 D23 Dummy signal (74 pixels) S7498 S7496 S7497 S7495 S4 S2 S3 D74 S1 D72 D73 1-line output period (7594 pixels) Optical black (48 pixels) D93 D84 D82 D83 D80 D81 D78 D79 D76 D77 S7500 D75 S7499 D5 D3 D1 Note) The transfer pulses (φ1, φ2, φLH) must have more than 3797 cycles. ∗1 Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN, φCLP-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD, φCLP-ODD for half a cycle. D2 0 2 D4 5 3 D6 φROG 3797 D94 Clock Timing Chart 5 (alternate output∗1) ILX532A ILX532A Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 — ns φROG pulse high level period t2 1000 1500 — ns φROG, φ1 pulse timing t3 1000 1500 — ns φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 20 60 ns φ1 pulse fall time/φ2 pulse rise time t7 0 60 ns φRS pulse high level period t8 10 20 200∗1 — ns — ns φRS, φCLP pulse timing t9 10 200∗1 φRS pulse rise time t10 0 10 30 ns φRS pulse fall time t11 0 30 ns φCLP pulse high level period t12 10 10 200∗1 — ns — ns φCLP, φLH pulse timing t13 5 50∗1 φCLP pulse rise time t14 0 10 30 ns φCL pulse fall time t15 0 10 30 ns t16 — 8 — ns t17 — 15 — ns Signal output delay time ∗1 These timing is the recommended condition under fφ1 = 1MHz. –8– VOUT-ODD 5.1kΩ IC1 0.1µF Tr1 7 6 2Ω 20 21 22 23 8 2Ω 19 φ2 9 φ1 10 17 18 11 φROG 12 15 16 IC1 13 14 0.1µF IC1: 74AC04 Tr1: 2SC2785 47µF 16V 12V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ∗1 Data rate fφR = 2MHz. VDD 100Ω 2 φCLP-ODD φCLP-EVEN φCLP φRS φLH 100Ω 5 4 3 φRS-EVEN φRS-ODD 1 24 25 φLH-EVEN φLH-ODD 27 φ2-ODD 26 GND 28 GND φ1-ODD 100Ω VOUT-EVEN VOUT-EVEN VDD Tr1 NC VGG NC NC φ2-EVEN NC φ1-EVEN VDD VDD φROG GND NC NC NC 5.1kΩ VOUT-ODD 100Ω –9– 100Ω Application Circuit∗1 ILX532A ILX532A Example of Representative Characteristics (VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) 1.0 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 500 600 700 800 900 1000 Wavelength [nm] Dark signal output temperature characteristics (Standard characteristics) Integration time output voltage characteristics (Standard characteristics) 10 Output voltage rate Output voltage rate 5 1 0.5 0.1 0 10 20 30 40 0.5 0.1 60 50 1 1 5 10 Ta – Ambient temperature [°C] τ int – integration time [ms] Offset level vs. VDD characteristics (Standard characteristics) Offset level vs. Temperature characteristics (Standard characteristics) 12 12 Ta = 25°C 10 Vos – Offset level [V] Vos – Offset level [V] 10 8 6 4 ∆Vos ∆VDD 6 4 ∆Vos ∆Ta 0.6 2 0 11.4 8 –2mV/°C 2 12.0 0 12.6 VDD [V] 0 10 20 30 40 50 Ta – Ambient temperature [°C] – 10 – 60 ILX532A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N 0.9Nm (2) (3) (4) c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 11 – ILX532A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. – 12 – – 13 – H 2.54 22 Cer-DIP TIN PLATING 42 ALLOY 8.8g LS-C5(E) LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER 16.5 68.0 16.5 52.5(7µmX7500pixels) PACKAGE MATERIAL 7 No. 1 Pixel PACKAGE STRUCTURE 1 V 28 10.12±0.5 71.00±0.8 8 21 0.46 28pin DIP (400mil) (AT STAND OFF) 10.16 3. The notches of the package must not be used for reference of fixing. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 1. The height from the bottom to the sensor surface is 2.4mm±0.3. 14 15 9.0 3.60 Unit: mm 10.0±0.5 4.40±0.5 5.0±0.5 4.0±0.5 0 to 9˚ 0.25 Package Outline ILX532A