ILX554A 2048-pixel CCD Linear Sensor (B/W) for Single 5V Power Supply Bar-code Reader For the availability of this product, please contact the sales office. Description The ILX554A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. NC 3 20 VDD SHSW 4 19 GND φCLK 5 18 NC NC 6 17 NC NC 7 16 NC NC 8 15 NC NC 9 14 NC NC 10 13 NC 12 NC 11 φROG SHSW 11 φCLK Mode selector VOUT φROG 1 2048 VDD NC GND 21 • Output amplifier • S/H circuit 2 D1 D2 NC 4 NC 5 22 1 20 1 D32 S1 S2 S3 VOUT 19 Pin Configuration (Top View) Clock-drivers V °C °C Readout gate • Operating temperature • Storage temperature 6 –10 to +60 –30 to +80 CCD analog shift register Absolute Maximum Ratings • Supply voltage VDD Clock pulse generator/ Sample-and-hold pulse generator Single 5V power supply Ultra-high sensitivity Built-in timing generator and clock-drivers Built-in sample-and-hold circuit Maximum clock frequency: 2MHz Readout gate pulse generator Block Diagram D39 D40 • • • • • 2048 pixels 14µm × 56µm (14µm pitch) S2046 S2047 S2048 D33 Features • Number of effective pixels: • Pixel size: 22 pin DIP (Cer-DIP) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00818-PS ILX554A Pin Description Pin No. Description Symbol Pin No. Symbol Description 1 VOUT Signal output 12 NC NC 2 NC NC 13 NC NC 3 NC NC 14 NC NC 4 SHSW Switch (with S/H or without S/H) 15 NC NC 5 φCLK Clock pulse input 16 NC NC 6 NC NC 17 NC NC 7 NC NC 18 NC NC 8 NC NC 19 GND GND 9 NC NC 20 VDD 5V power supply 10 NC NC 21 NC NC 11 φROG Readout gate pulse input 22 NC NC Mode Description Mode in use Pin 4 (SHSW) With S/H GND Without S/H VDD Recommended Supply voltage Item VDD Min. Typ. Max. Unit 4.5 5.0 5.5 V Input Clock voltage Condition∗1 Item Min. Typ. Max. Unit VIH 4.5 5.0 VDD V VIL 0 — 0.5 V ∗1 This is applied to the all pulses applied externally. (φCLK, φROG) Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φCLK CφCLK — 10 — pF Input capacity of φROG CφROG — 10 — pF –2– ILX554A Electro-optical Characteristics (Ta = 25°C, VDD = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Without S/H mode) Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 R1 180 240 300 V/(lx · s) Note 1 Sensitivity 2 R2 — 3500 — V/(lx · s) Note 2 Sensitivity nonuniformity PRNU — 5.0 10.0 % Note 3 Saturation output voltage VSAT 0.8 1.0 — V — Dark voltage average VDRK — 3.0 6.0 mV Note 4 Dark signal nonuniformity DSNU — 6.0 12.0 mV Note 4 Image lag IL — 1 — % Note 5 Dynamic range DR — 333 — — Note 6 Saturation exposure SE — 0.004 — lx · s Note 7 5V current consumption IVDD — 5.0 10 mA — Total transfer efficiency TTE 92 98.0 — % — Output impedance ZO — 250 — Ω — Offset level VOS — 2.85 — V Note 8 Note) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. Light sourse: LED λ = 660nm 3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = (VMAX – VMIN)/2 VAVE × 100 [%] The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. 4. Integration time is 10ms. 5. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. 6. DR = VSAT VDRK When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. 7. SE = VSAT R1 8. VOS is defined as indicated below. D D D SI Vout VOS GND –3– Clock Timing Diagram (without S/H mode) 5 φROG 1 2088 1 2 3 0 0 5 φCLK 0 D36 D37 D38 D39 D40 S2045 S2046 S2047 S2048 D33 D34 D35 D30 D31 D32 S1 S2 S3 S4 D10 D11 D12 D13 D14 D1 D2 D3 D4 D5 –4– VOUT∗ Optical black (18 pixels) Dummy signal (32 pixels) Effective picture elements signal (2048 pixels) Dummy signal (8 pixels) 1-line output period (2088 pixels) ∗ Without S/H mode (4 pin → VDD) Note) 2090 or more clock pulse are required. ILX554A Clock Timing Diagram (with S/H mode) 5 φROG 1 2088 1 2 3 0 0 5 φCLK S2045 S2046 S2047 S2048 D33 D34 D35 D36 D37 D38 D39 D40 D30 D31 D32 S1 S2 S3 S4 D11 D12 D13 D14 D0 D1 D2 D3 D4 D5 –5– D10 0 VOUT∗ Optical black (18 pixels) Dummy signal (33 pixels) Effective picture elements signal (2048 pixels) Dummy signal (8 pixels) 1-line output period (2089 pixels) ∗ With S/H mode (4 pin → GND) Note) 2090 or more clock pulse are required. ILX554A ILX554A φCLK Timing (For all modes) t1 t2 φCLK t3 Item φCLK pulse rise/fall time φCLK pulse duty∗1 t4 Symbol Min. Typ. Max. Unit t1, t2 0 10 100 ns — 40 50 60 % ∗1 100 × t4 / (t3 + t4) φROG, φCLK Timing t8 t6 φROG t7 φCLK t5 Item φROG, φCLK pulse timing 1 φROG, φCLK pulse timing 2 φROG pulse rise/fall time φROG pulse period t9 Symbol Min. Typ. Max. Unit t5 t9 t6, t8 t7 0 3000 — ns 1000 3000 — ns 0 10 — ns 1000 5000 — ns –6– ILX554A φCLK, VOUT Timing (Note 1) (Note 3) φCLK t10 t11 VOUT VOUT∗ (Note 2) t12 Item φCLK-VOUT 1 φCLK-VOUT 2 φCLK-VOUT∗ (with S/H) 3 Symbol Min. Typ. Max. Unit t10 t11 t12 20 100 250 ns 55 210 410 ns 20 150 250 ns Note 1) fck = 1MHz, φCLK pulse duty = 50%, φCLK pulse rise/fall time = 10ns Note 2) Output waveform when internal S/H is in use. Note 3) indicates the correspondence of clock pulse and data period. –7– ILX554A Example of Representative Characteristics Spectral sensitivity (Typ.) (Ta = 25˚C) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 800 700 900 Wavelength [nm] Dark voltage rate vs. Ambient temperature (Typ.) Dark voltage rate 10 1 0.1 0 10 20 30 40 50 Ta – Ambient temperature [˚C] –8– 60 1000 ILX554A Output voltage rate vs. Integration time (Typ.) Current consumption rate vs. Clock frequency (Typ.) 2.0 Current consumption rate Output voltage rate 10 1 0.1 1.5 1.0 0.5 0 1 10 100 0 Integration time [ms] Offset level vs. VDD (Typ.) 1.5 2.0 Offset level vs. Ambient temperature (Typ.) 3.2 3.1 3.1 3.0 3.0 Offset level [V] Offset level [V] 1.0 Clock frequency [MHz] 3.2 2.9 2.8 2.7 2.9 2.8 2.7 2.6 2.6 2.5 2.5 2.4 4.50 0.5 2.4 4.75 5.00 5.25 5.50 0 VDD [V] 20 40 Ambient temperature [˚C] –9– 60 ILX554A Application Circuit (Without S/H mode) Note) VDD 0.01µ 22µ/10V NC NC NC NC NC NC NC NC NC NC NC φROG 12 NC 13 φCLK 14 GND 15 SHSW 16 VDD 17 NC 18 NC 19 NC 20 NC 21 VOUT 22 1 2 3 4 5 6 7 8 9 10 11 100Ω 100Ω φCLK 3kΩ φROG VOUT Note) This circuit diagram is the case when internal S/H mode is not used. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – ILX554A Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an eath band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates use cartons treated for the prevention of static charges. 2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and installing this package. a) (1) Compressive strength: 39N/surface (Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N Lower ceramic layer (1) Low-melting glass 29N 29N 0.9Nm (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount image sensors, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. – 11 – ILX554A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. Use the output signal added 22500 pulses or above to φCLK clock pulse. – 12 – Package Outline Unit: mm 0˚ to 9˚ 22 pin DIP (400mil) 41.6 ± 0.5 6.46 ± 0.5 28.672 (14µm X 2048Pixels) V No.1 Pixel H 0.25 5.0 ± 0.3 10.0 ± 0.5 12 22 11 1 – 13 – 1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm. 4.35 ± 0.5 2.54 3.65 4.0 ± 0.5 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. 0.3 M 0.51 PACKAGE STRUCTURE Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.20g DRAWING NUMBER LS-A20(E) ILX554A Sony Corporation PACKAGE MATERIAL