LCX009AK
1.8cm (0.7-inch) NTSC/PAL Color LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX009AK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides fullcolor representation in NTSC/PAL mode. RGB dots
are arranged in a delta pattern featuring high picture
quality of no fixed color patterns, which is inherent in
vertical stripes and mosaic pattern arrangements.
Features
• The number of active dots: 180,000 (0.7-inch; 1.8cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 3.5% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL compatible
• Right/left inverse display function
Element Structure
• Dots
Total dots
: 827 (H) × 228 (V) = 188,556
Active dots
: 800 (H) × 225 (V) = 180,000
• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94212C64-PS
LCX009AK
VVDD
VSS
VST
VCK2
VCK1
EN
CLR
RGT
HST
HCK2
HCK1
HVDD
BLUE
RED
GREEN
COM
Block Diagram
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
H Level
Shifter
H Shift Register
V Shift Register
V Level
Shifter
CS
LC
COM
Pad
–2–
LCX009AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• H driver input pin voltage
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK1, VCK2
CLR, EN
• Video signal input pin voltage GREEN, RED, BLUE
• Operating temperature
Topr
• Storage temperature
Tstg
–1.0 to +17
–1.0 to +17
–1.0 to +17
V
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (Vss = 0V)
Supply voltage
HVDD
13.5 ± 0.5
V
VVDD
13.5 ± 0.5
V
Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
3.0V or more
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
COM
Common voltage of panel
9
RGT
Drive direction pulse for H shift
register (H: normal, L: reverse)
2
GREEN
Video signal (G) to panel
10
CLR
Improvement pulse
for uniformity
3
RED
Video signal (R) to panel
11
EN
Enable pulse for gate selection
4
BLUE
Video signal (B) to panel
12
VCK1
Clock pulse for
V shift register drive
5
HVDD
Power supply for H driver
13
VCK2
Clock pulse for
V shift register drive
6
HCK1
Clock pulse for
H shift register drive
14
VST
Start pulse for
V shift register drive
7
HCK2
Clock pulse for
H shift register drive
15
Vss
GND (H, V drivers)
8
HST
Start pulse for
H shift register drive
16
VVDD
Power supply for V driver
–3–
LCX009AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)
(1) Video signal input
From H driver
HVDD
Input
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
HCK1
250Ω
250Ω
Level conversion
circuit
(2-phase input)
HCK2
(3) HST
HVDD
250Ω
250Ω
Level conversion
circuit
(single-phase input)
2.5kΩ
Level conversion
circuit
(single-phase input)
Input
(4) RGT
HVDD
2.5kΩ
Input
(5) VCK1, VCK2
VVDD
2.5kΩ
2.5kΩ
VCK1
1kΩ
1kΩ
Level conversion
circuit
(2-phase input)
VCK2
(6) VST, CLR, EN
VVDD
2.5kΩ
Input
2.5kΩ
Level conversion
circuit
(single-phase input)
(7) COM
Input
LC
1MΩ
–4–
LCX009AK
Output voltage (inside panel)
Level Conversion Circuit
The LCX009AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit
voltage is stepped up to 13.5V. This level conversion circuit meets the specifications of a 3.0V to 5.0V power
supply of the externally-driven IC mainly. However, this circuit can operate even with a 12V power supply of
the IC.
1. I/O characteristics of level conversion circuit
HVDD
(For a single-phase input unit)
Example of single-phase
I/O characteristics
An example of the I/O voltage characteristics of a
level conversion circuit is shown in the figure to the
HVDD
2
right. The input voltage value that becomes half the
output voltage (after voltage conversion) is defined
as Vth.
The Vth value varies depending on the HVDD and
Vth
VVDD voltages.
Input voltage [V]
The Vth values under standard conditions are
indicated in the table below. (HST, VST, EN, CLR, and RGT in the case of a single-phase input)
HVDD = VVDD = 13.5V
Item
Vth voltage of circuit
Symbol
Min.
Typ.
Max.
Unit
Vth
0.35
1.50
2.70
V
Output voltage (inside panel)
(For a differential input unit)
An example of I/O voltage characteristics of a
level conversion circuit for a differential input is
shown in the figure to the right. Although the
characteristics, including those of the Vth voltage,
are basically the same as those for a singlephased input, the two-phased input phase is
defined. (Refer to clock timing conditions.)
HVDD
Example of differential
I/O characteristics
HVDD
2
2. Current characteristics at the input pin of level
conversion circuit
Vth
Input voltage [V]
VDD
A slight pull-in current is generated at the input
pin of the level conversion circuit. (The equivalent
circuit diagram is shown to the right.) The current
volume increases as the voltage at the input pin
decreases, and is maximized when the pin is
grounded.) (Electrical characteristics are defined
by the grounded input.)
Input pin current
0
Input pin voltage [V]
Output
10
0
Max. value
HCK1
input
Pull-in current
characteristics at the
input pin
HCK2
input
Level conversion equivalent circuit
–5–
LCX009AK
Input Signals
1. Input signal voltage conditions (Vss = 0V)
Symbol
Item
Min.
Typ.
Max.
Unit
(Low)
VHIL
–0.3
0.0
0.3
V
(High)
VHIH
3.0
5.0
5.5
V
(Low)
VVIL
–0.3
0.0
0.3
V
(High)
VVIH
3.0
5.0
5.5
V
Video signal center voltage
Video signal input range∗1
VVC
5.8
6.0
6.2
V
Vsig
VVC – 4.5
VVC + 4.5
V
Common voltage of panel
Vcom
VVC – 0.55 VVC – 0.40 VVC – 0.25
V
H driver input voltage
V driver input voltage
∗1 Video input signal should be symmetrical to VVC.
2. Clock timing conditions (Ta = 25°C)
Item
HST
HCK
CLR
VST
VCK
EN
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
30
Hst fall time
tfHst
30
Hst data set-up time
tdHst
–100
60
100
Hst data hold time
Hckn∗2 rise time
thHst
–200
–120
–50
trHckn
30
Hckn∗2 fall time
tfHckn
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Clr rise time
trClr
100
Clr fall time
tfClr
100
Clr pulse width
twClr
3400
3500
3600
Clr fall to Hst rise time
toHst
1850
1950
2050
Vst rise time
trVst
100
Vst fall time
tfVst
100
Vst data set-up time
tdVst
–50
32
50
Vst data hold time
Vckn∗2 rise time
thVst
–50
–32
–20
trVckn
100
Vckn∗2 fall time
tfVckn
100
Vck1 fall to Vck2 rise time
to1Vck
–20
0
20
Vck1 rise to Vck2 fall time
to2Vck
–20
0
20
En rise time
trEn
100
En fall time
tfEn
100
Vck2 rise to En fall time
tdVck2
–20
0
20
Vck1 rise to En rise time
tdVck1
–20
0
20
∗2 Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 2.75MHz, fVckn = 7.81kHz)
–6–
Unit
ns
µs
ns
LCX009AK
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
90%
10%
10%
tfHst
trHst
HST
∗3
Hst data set-up time
Conditions
tdHst
tfHst
50%
50%
Hst
Hck1
50%
Hst data hold time
50%
thHst
tdHst
Hckn*2
rise time
∗2
HCK
Hckn*2 fall time
tfHckn
Hck1 fall to
Hck2 rise time
to1Hck
10%
trHckn
∗3
Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns
90%
10%
Hckn
Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
50%
tfHckn
50%
Hck1
50%
tdHst = 60ns
thHst = –120ns
50%
Hck2
Hck1 rise to
Hck2 fall time
to2Hck
Clr rise time
trClr
to2Hck
to1Hck
90%
90%
Clr
10%
10%
Clr fall time
tfClr
Clr pulse width
twClr
Clr fall to
Hst rise time
toHst
trClr
tfClr
Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
CLR
Hst
Clr
50%
50%
twClr
–7–
50%
toHst
Hckn∗2
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX009AK
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
trVst
90%
Vst
Vst fall time
Conditions
90%
10%
10%
tfVst
trVst
VST
∗3
Vst data set-up time
tdVst
Vst data hold time
thVst
tfVst
50%
50%
Vst
50%
50%
Vck1
tdVst
Vckn*2
VCK
90%
trVckn
10%
Vckn
Vckn*2 fall time
tfVckn
Vck1 fall to
Vck2 rise time
to1Vck
10%
trVckn
∗3
50%
tfVckn
Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
50%
Vck1
50%
tdVst = 32µs
thVst = –32µs
50%
Vck2
Vck1 rise to
Vck2 fall time
to2Vck
En rise time
trEn
to2Vck
90%
to1Vck
10%
10%
90%
En
En fall time
tfEn
Vck2 rise to
En fall time
tdVck2
EN
tfEn
∗3
trEn
50%
tdVck1
50%
En
tdVck2
tdVck1
∗3 Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–8–
Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
50%
Vck2
50%
Vck1 rise to
En rise time
Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
thVst
90%
rise time
Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Vckn∗2
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
LCX009AK
Electrical Characteristics
(Ta = 25°C, HVDD = 13.5V, VVDD = 13.5V)
1. Horizontal drivers
Item
Symbol
Typ.
Max.
Unit
CHckn
5
10
pF
Hst
CHst
5
10
pF
Hck1
IHck1
–200
–60
µA
Hck1 = GND
Hck2
IHck2
–500
–260
µA
Hck2 = GND
Hst
IHst
–300
–100
µA
Hst = GND
Rgt
IRgt
–100
–15
µA
Rgt = GND
Input pin capacitance Hckn
Input pin current
Min.
Condition
Video signal input pin capacitance Csig
45
60
pF
Current consumption
3
4
mA
Typ.
Max.
Unit
CVckn
5
10
pF
Vst
CVst
5
10
pF
Vck1
IVck1
–100
–30
µA
Vck1 = GND
Vck2
IVck2
–400
–200
µA
Vck2 = GND
Vst
En
Clr
IVst,
IEn,
IClr
–100
–15
µA
Vst, En, Clr=GND
µA
Vckn: Vck1, Vck2 (7.87kHz)
IH
Hckn: Hck1, Hck2 (2.75MHz)
2. Vertical drivers
Item
Symbol
Input pin capacitance Vckn
Input pin current
Current consumption
Min.
IV
400
1000
Condition
3. Total power consumption of the panel
Item
Symbol
Min.
Total power consumption of the panel (NTSC) PWR
Typ.
Max.
Unit
45
70
mW
Max.
Unit
4. COM input resistance
Item
COM – Vss input resistance
Symbol
Min.
Typ.
Rcom
0.5
1
–9–
MΩ
LCX009AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Item
Contrast ratio
25°C
CR25
60°C
CR60
Optical transmittance
G
B
V90
V–T
characteristics
1
2
T
R
Chromaticity
Measurement
method
Symbol
V50
V10
Half tone color
reproduction range
ON time
Response time
OFF time
Flicker
Image retention time
Optimum Vcom voltage
Min.
Typ.
Max.
80
200
—
80
200
—
2.7
3.5
—
X
Rx
0.560
0.630
0.670
Y
Ry
0.300
0.345
0.390
X
Gx
0.275
0.310
0.347
Y
Gy
0.541
0.595
0.650
X
Bx
0.120
0.148
0.187
Y
By
0.040
0.088
0.122
3
Unit
—
%
CIE
standards
25°C
V90-25
1.1
1.6
2.2
60°C
V90-60
1.0
1.3
2.1
25°C
V50-25
1.5
2.0
2.5
60°C
V50-60
1.4
1.8
2.4
25°C
V10-25
2.2
2.7
3.2
60°C
V10-60
2.1
2.5
3.1
R vs. G
V50RG
—
–0.10
–0.25
B vs. G
V50BG
—
0.10
0.45
0°C
ton0
—
25
100
25°C
ton25
—
8
40
0°C
toff0
—
65
150
25°C
toff25
—
20
60
60°C
F
7
—
—
–40
dB
YT60
8
—
—
20
s
Vcomopt
9
5.45
5.60
5.75
V
60min.
4
5
6
– 10 –
V
V
ms
LCX009AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1)Driving voltage
HV DD = 13.5V, VVDD = 13.5V
VVC = 6.0V, Vcom = 5.6V
(2)Measurement temperature
25°C unless otherwise specified.
(3)Measurement point
One point in the center of screen unless otherwise specified.
(4)Measurement systems
Two types of measurement system are used as shown below.
(5)RGB input signal voltage (Vsig)
Vsig = 6 ± V AC (V)
(VAC: signal amplitude)
Back Light
∗ Measurement system Ι
Luminance
Meter
Measurement
Equipment
Back light: color temperature 6500K, +0.004uV (25°C)
∗ Back light spectrum (reference) is listed on another page.
3.5mm
LCD panel
∗ Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
L (Black)
... (1)
L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V
Both luminosities are measured by System I.
– 11 –
LCX009AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
L (White)
Luminance of Back Light
× 100 (%) ... (2)
L (White) is the same expression as defined in the 'Contrast Ratio' section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Raster
Signal amplitudes (VAC) supplied to each input
R input
G input
B input
R
0.5
4.5
4.5
G
4.5
0.5
4.5
B
4.5
4.5
0.5
5. Half Tone Color Reproduction Range
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V – T
characteristics of R, G and B. The differences of these V – T
characteristics are measured by System II. System II
defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formula (3) and (4)
respectively.
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
100
Transmittance [%]
4. V – T Characteristics
V – T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond
to the each voltage which defines 90%, 50% and 10%
of transmittance respectively.
Transmittance [%]
(Unit: V)
V50RG
V50BG
50
G raster
B raster
R raster
0
V50R V50B
V50G
VAC – Signal amplitude [V]
– 12 –
LCX009AK
6. Response Time
Response time ton and toff are defined by
the formula (5) and (6) respectively.
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal
4.5V
0.5V
6V
0V
Light transmission
output waveform
100%
90%
10%
0%
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
AC component
}
F (dB) = 20log {
DC component ... (7)
∗ R, G, B input signal condition for gray raster mode is given by
Vsig = 6 ± V50 (V)
where:V50 is the signal amplitude which gives 50% of
transmittance in V – T curve.
8. Image Retention Time
Image retention time is given by the following procedures:
Apply monoscope signal to the LCD panel for 60 minutes and then change monoscope signal∗ to gray scale
signal (Vsig = 6 ± VAC (V); VAC = 3 to 4V) so as to give the maximum image retention. Hold input signal VAC.
The time of the residual image to disappear gives the image retention time.
∗ Monoscope signal conditions:
Black level
Vsig = 6 ± 4.5 or 6 ± 2.0 (V)
4.5V
White level
(shown in the right figure)
2.0V
Vcom = 5.6V
6V
2.0V
4.5V
0V
Vsig waveform
– 13 –
LCX009AK
9. Method of Measuring the Optimum Vcom
There are two methods of measuring the optimum Vcom using the photoelectric element.
9-1. Method of Measuring Flicker
In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the
photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value at
this time is taken to be the optimum Vcom.
9-2. Method of Measuring Contrast
In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so
that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom.
Example of Back Light Spectrum (Reference)
0.4
0.3
0.2
0.1
0
400
500
600
Wave length 380 – 780 [nm]
– 14 –
700
LCX009AK
Description of Operation
1. Color Coding
Color filters are coded in a delta arrangement.
The shaded area is used for the dark border around the display.
Gate SW
dummy 1 to 4
R
G
B
Gate SW
R
G
B
Gate SW
R
G
B
Gate SW
dummy 5 to 8
Gate SW
R
G
B
R
G
B
R
2
B
Gate SW
G
B
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
G
B
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
B
R
G
R
G
B
B
R
Photo-shielding
B
R
G
G
B
R
G
B
R
B
G
B
R
G
R
B
R
G
B
R
G
B
R
B
G
G
B
R
G
R
G
B
R
G
B
B
R
G
B
R
G
B
R
G
R
B
R
G
B
G
R
G
B
R
B
G
B
R
G
R
B
R
G
B
G
R
G
B
R
R
G
1
R
G
225
Active area
R
827
14
800
– 15 –
13
228
R
LCX009AK
2. LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 225 gate lines sequentially in every single horizontal scanning period. A vertical shift register scans
the gate lines from the top to bottom of the panel.
• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by
controlling the enable and VCK1, VCK2 pins. The enable pin should be High when not in use.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuit,
applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period.
• Scanning direction of horizontal shift register can be switched with RGT pin.Scanning direction is left to right
for RGT pin at High level; and right to left for RGT pin at Low level.(These scanning directions are from a
front view.) Normally, set to High level.
• Vertical and horizontal drivers address one pixel, and then dot Thin Film Transistors (TFTs; two TFTs for one
dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 225 × 800 dots to
display a picture in a single vertical scanning period.
• Pixels are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot offset against
juxtaposed horizontal line. For this reason, 1.5-dot offset of a horizontal driver output pulse against horizontal
synchronized pulse is required to apply a video signal to each dot properly. 1 H reversed displaying mode is
required to apply video signal to the panel.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 8.5V. This pin should be
grounded when not in use.
• The video signal must be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle
are shown below.
Hck1 and Hck2 should be exchanged to display the left-direction horizontal scanning (RGT = Low level). This
exchange enables the center of the image to be fixed by eliminating offsets.
(1) Vertical display cycle
VD
Vst
Vck1
1
2
224
Vck2
Vertical display 225H (14.3ms)
(2) Horizontal display cycle (right-direction scanning)
BLK
Hst
270
Hck1
1
2
3
4
5
6
271
Hck2
Horizontal display cycle (48.4µs)
The horizontal display cycle consists of 800/3 = 267 clock pulses because of RGB simultaneous sampling∗.
∗ Refer to Description of Operation "3. RGB Simultaneous Sampling''
– 16 –
225
LCX009AK
3. RGB Simultaneous Sampling
Horizontal driver performs R, G and B signal sampling simultaneously, which requires the phase matching
between R, G, B signals to prevent horizontal resolution from deteriorating. The phase matching by an
external signal delaying circuit is needed before applying video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The LCX009 has a right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right-direction scanning (RGT = High level). For the left-direction scanning (RGT = Low level),
the phase setting should be inverted for B and G signals.
B
S/H
S/H
CKB
CKG
R
S/H
S/H
CKR
CKG
S/H
G
AC Amp
4
BLUE
AC Amp
3
RED
AC Amp
2
GREEN
LCX009AK
(1) Sample-and-hold (right-direction scanning)
CKG
<Phase relationship of delaying sample-and-hold pulses> (right-direction scanning)
HCKn
CKB
CKR
CKG
B
R
Delay
Delay
AC Amp
4
BLUE
Delay
AC Amp
3
RED
AC Amp
2
GREEN
G
– 17 –
LCX009AK
(2) Delay circuit (right-direction scanning)
LCX009AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
G
B
60
Transmittance [%]
40
20
0
400
500
600
Wavelength [nm]
– 18 –
700
LCX009AK
Color Display System Block Diagram (1)
An example of single-chip display system is shown below.
+12V
+5V
+13.5V
RED
Composite video
GREEN
Y/C
BLUE
Y/color difference
VCOM
LCD panel
NTSC/PAL
LCX009AK
CXA1854R
HST
HCK1
HCK2
VST
VCK1
VCK2
EN
CLR
(Refer to CXD1845R data sheet.)
RGT
– 19 –
LCX009AK
Color Display System Block Diagram (2)
An example of dual-chip display system is shown below.
+12V
+5V
+13.5V
RED
Composite video
Decoder/Driver
CXA1785AR
Y/C
GREEN
BLUE
Y/color difference
SYNC
Vcom
FRP
+5V
LCD Panel
NTSC/PAL
LCX009AK
Hst
Hck1
Hck2
Vst
TG
CXD2411R
Vck1
Vck2
En
Clr
(Refer to CXD2411R data sheet.)
Rgt
– 20 –
LCX009AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily
deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages.
– 21 –
LCX009AK
Package Outline
Unit: mm
18.4 ± 0.2
Thickness of the connector 0.3 ± 0.05
8.5 ± 0.05
1.3 ± 0.3
4
1
3
33.2 ± 0.8
5
6
Incident
light
Active Area
6
9.5 ± 0.25
(10.7)
Active Area
Reinforcing board 4.0 ± 0.5
1.0
4-R
2
21.0 ± 0.15
sc
CK1
No
1
(14.4)
11.0 ± 0.25
PIN16
3.0 ± 0.3
0.5 ± 0.15
× 15 = 7.5 ± 0.03
+ 0.04
0.35 – 0.03
0.5 ± 0.1
PIN1
F P C
2.9 ± 0.15
22.0 ± 0.15
P 0.5 ± 0.02
Description
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
6
Polarizing film
weight 2g
electrode (enlarged)
– 22 –