2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo FEATURES: • ROM + SRAM ROM/RAM Combo – SST30VR021: 256K x8 ROM + 128K x8 SRAM – SST30VR022: 256K x8 ROM + 256K x8 SRAM – SST30VR023: 256K x8 ROM + 32K x8 SRAM • ROM/RAM combo on a monolithic chip • Equivalent ComboMemory (Flash + SRAM): SST31LF021E for code development and pre-production • Wide Operating Voltage Range: 2.7-3.3V • Chip Access Time – SST30VR022 70 ns – SST30VR021/023 500 ns • Low Power Dissipation: – Standby: 3 µW (Typical) – Operating: 10 mW (Typical) • Fully Static Operation – No clock or refresh required • Three state Outputs • Packages Available – 32-pin TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR021/022/023 are ROM/RAM combo chips consisting of 2 Mbit Read Only Memory organized as 256 KBytes and Static Random Access Memory organized as 128, 256, and 32 KBytes. The SST30VR021/022/023 has an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR021/022/023 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. FUNCTIONAL BLOCK DIAGRAM RAMCS# OE# WE# OE# WE# Address Buffer RAM DQ7-DQ0 ROMCS# OE# AMS-A0 ROM Note: AMS = Most Significant Address ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380 1 Data Buffer ROMCS# Control Circuit RAMCS# 380 ILL B1.1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet A11 A9 A8 A13 A14 A17 RAMCS# VDD WE# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 380 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP TABLE 1: PIN DESCRIPTION Symbol Pin Name AMS1-A0 Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021 A17 for SST30VR022 A14 for SST30VR023 WE# Write Enable Input OE# Output Enable RAMCS# RAM Enable Input ROMCS# ROM Enable Input DQ7-DQ0 Data Input/Output VDD Power Supply VSS Ground T1.2 380 1. AMS = Most significant address ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 2 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on Any Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C OPERATING RANGE Range Commercial Extended AC CONDITIONS OF Ambient Temp VDD 0°C to +70°C 2.7-3.3V -20°C to +85°C 2.7-3.3V TEST Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . 0-VDD Input & Output Timing Reference Levels . . . . . . . VDD/2 Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 500 ns TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min Max Units VDD Supply Voltage 2.7 3.3 V VSS Ground 0 0 V VIH Input High Voltage 2.4 VDD + 0.5 V VIL Input Low Voltage -0.3 0.3 V T2.0 380 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 3.0 ± 0.3V Symbol Parameter Max Units IDD1 ROM Operating Supply Current 4.0+1.1(f)1 mA IDD2 RAM Operating Supply Current 2.5+1(f)1 mA ROMCS#=VIH, RAMCS#=VIL, II/O=Opens ISB Standby VDD Current 10 µA ROMCS#≥VDD-0.2V, RAMCS#≥VDD-0.2V VIN≥VDD-0.2V or VIN ≤0.2V ILI Input Leakage Current -1 1 µA VIN=VSS to VDD ILO Output Leakage Current -1 1 µA ROMCS#=RAMCS#=VIH or OE#=VIH or WE#=VIL, VI/O=VSS to VDD VOL Output Low Voltage 0.4 V IOL = 1.0 mA VOH Output High Voltage V IOH = -0.5 mA Min 2.2 Test Conditions ROMCS#=VIL, RAMCS#=VIH, VIN=VIH or VIL, II/O=Opens T3.3 380 1. f = Frequency of operation (MHz) = 1/cycle time ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 3 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 8 pF Input Capacitance VIN = 0V 6 pF CIN 1 T4.1 380 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 380 ILL F08.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 380 ILL F09.0 FIGURE 3: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 4 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR022-70 Min Max SST30VR021/023-500 Symbol Parameter TRC Read Cycle Time TAA Address Access Time TCO Chip Select to Output 70 500 ns TOE Output Enable to Valid Output 35 250 ns TLZ Chip Select to Low-Z Output 0 25 ns TOLZ Output Enable to Low-Z Output 0 25 ns THZ Chip Disable to High-Z Output 25 30 ns TOHZ Output Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 70 Min Max Units 500 ns 500 70 10 ns 15 ns T5.1 380 TRC Address TAA TOH Data Out Data Valid Previous Data Valid 380 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL) ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 5 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet TRC Address THZ(1,2) TAA TCO ROMCS# TLZ(2) TOHZ(1) TOE OE# TOLZ TOH High-Z Data Valid Data Out 380 ILL F03.0 Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED) ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 6 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet II. SRAM Operation (ROMCS# = VIH) TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR022-70 Min Max SST30VR021/023-500 Symbol Parameter TRC Read Cycle Time TAA Address Access Time 70 500 ns TCO Chip Select to Output 70 500 ns TOE Output Enable to Valid Output 35 250 ns TLZ Chip Select to Low-Z Output THZ Chip Disable to High-Z Output TOHZ Output Disable to High-Z Output TOH Output Hold from Address Change 70 Min Max 500 0 ns 25 25 ns 30 25 10 Units 30 15 ns ns ns T6.2 380 TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR022-70 Symbol Parameter Min Max SST30VR021/023-500 Min Max Units TWC Write Cycle Time 70 500 ns TCW Chip Select to End-of-Write 60 365 ns TAW Address Valid to End-of-Write 60 375 ns TAS Address Set-up Time 0 0 ns TWP Write Pulse Width 60 375 ns TWR Write Recovery Time 0 0 ns TWHZ Write to Output High-Z TDW Data to Write Time Overlap 30 TDH Data Hold from Write Time TOW End Write to Output Low-Z 30 80 ns 200 ns 0 0 ns 0 15 ns T7.1 380 ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 7 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet TRC Address TAA TOH Data Out Data Valid Previous Data Valid 380 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# = RAMCS# = VIL, WE# = VIH) TRC Address TAA TOE TOHZ(1) OE# THZ (1,2) TCO RAMCS# TLZ(2) TOH High-Z Data Valid Data Out Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. 4. Address valid prior to coincidence with RAMCS# transition low. 380 ILL F05.0 FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED) ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 8 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet TWC Address TAW TWR(4) TCW(2) RAMCS# TAS(3) TWP(1) TOH WE# TDH TDW High-Z Data Valid Data In TOW TWHZ(5) (7) High-Z (6) (8) Data Out 380 ILL F07.0 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE Address Inputs ROMCS#1 RAMCS#1 WE# OE# DQ0-DQ7 X2 Z Standby H Z Output Floating X H H X2 A17-A0 L H X2 A17-A0 L H X2 L Dout ROM Read Only AMS3-A0 are valid4 H L H H Z Output Floating Only AMS3-A0 are valid4 H L H L Dout RAM Read Only AMS3-A0 are valid4 H L L H Din RAM Write T8.4 380 1. 2. 3. 4. If is forbidden for ROMCS# pin and RAMCS# pin to be “0” at the same time X means Don’t Care. AMS = A16 for SST30VR021, A17 for SST30VR022, and A14 for SST30VR023 For SST30VR021: A17 must be fixed to “L” or “H” For SST30VR023: A15, A16, and A17 must be fixed to “L” or “H” ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 9 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet Device Speed SST30VR023 - XXX Suffix1 - X Suffix2 - XX - RXXXX C-Spec Number Package Modifier H = 32 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm) U = Die only Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Read Access Speed 70 = 70 ns 500 = 500 ns Device Density 021 = 2 Mbit ROM + 1 Mbit SRAM 022 = 2 Mbit ROM + 2 Mbit SRAM 023 = 2 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Combo SST30VR021 Valid combinations SST30VR021-500-C-WH SST30VR021-500-C-U1 SST30VR021-500-E-WH SST30VR022 Valid combinations SST30VR022-70-C-WH SST30VR022-70-C-U1 SST30VR022-70-E-WH SST30VR023 Valid combinations SST30VR023-500-C-WH SST30VR023-500-C-U1 SST30VR023-500-E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 10 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 11 380 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023 Data Sheet Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 12 380