8 Mbit / 16 Mbit (x8) Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 SST39LF/VF080 / 0163.0 & 2.7V 8Mb / 16Mb (x8) MPF memories Data Sheet FEATURES: • Organized as 1M x8 / 2M x8 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF080/016 – 2.7-3.6V for SST39VF080/016 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) – Standby Current: 4 µA (typical) – Auto Low Power Mode: 4 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Block-Erase Capability – Uniform 64 KByte blocks • Fast Read Access Time: – 55 ns for SST39LF080/016 – 70 and 90 ns for SST39VF080/016 • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 15 seconds (typical) for SST39LF/VF080 30 seconds (typical) for SST39LF/VF016 • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 40-lead TSOP (10mm x 20mm) – 48-ball TFBGA (6mm x 8mm) PRODUCT DESCRIPTION The SST39LF/VF080 and SST39LF/VF016 devices are 1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF080/016 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080/016 write (Program or Erase) with a 2.7-3.6V power supply. They conform to JEDEC standard pinouts for x8 memories. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. Featuring high performance Byte-Program, the SST39LF/ VF080 and SST39LF/VF016 devices provide a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST39LF/VF080 and SST39LF/VF016 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 396 1 To meet high density, surface mount requirements, the SST39LF/VF080 and SST39LF/VF016 are offered in 40lead TSOP and 48-ball TFBGA packaging. See Figures 1 and 2 for pinouts. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Device Operation are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF/VF080 and SST39LF/VF016 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte-command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. The SST39LF/VF080 and SST39LF/VF016 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high. Read The Read operation of the SST39LF/VF080 and SST39LF/VF016 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Chip-Erase Operation The SST39LF/VF080 and SST39LF/VF016 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Byte-Program Operation The SST39LF/VF080 and SST39LF/VF016 are programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads Write Operation Status Detection The SST39LF/VF080 and SST39LF/VF016 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 2 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Hardware Data Protection The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) Data# Polling (DQ7) The SST39LF/VF080 and SST39LF/VF016 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF080 and SST39LF/VF016 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. When the SST39LF/VF080 and SST39LF/VF016 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart. Common Flash Memory Interface (CFI) Toggle Bit (DQ6) The SST39LF/VF080 and SST39LF/VF016 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 8. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. Data Protection The SST39LF/VF080 and SST39LF/VF016 provide both hardware and software features to protect nonvolatile data from inadvertent writes. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 3 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Product Identification Product Identification Mode Exit/ CFI Mode Exit The Product Identification mode identifies the device as the SST39LF080, SST39VF080, SST39LF016, and SST39VF016 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Data 0000H BFH SST39LF/VF080 0001H D8H SST39LF/VF016 0001H D9H Manufacturer’s ID Device ID T1.2 396 FUNCTIONAL BLOCK DIAGRAM X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# OE# I/O Buffers and Data Latches Control Logic WE# DQ7 - DQ0 396 ILL B1.2 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 4 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet SST39LF/VF160 SST39LF/VF080 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 SST39LF/VF080 SST39LF/VF016 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Standard Pinout Top View Die Up A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 396 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP TOP VIEW (balls facing down) TOP VIEW (balls facing down) 5 4 3 2 1 A14 A13 A15 A9 A8 WE# NC NC A7 NC A18 A11 NC NC A6 A16 A17 NC 6 NC VSS 5 A12 A19 A10 DQ6 DQ7 NC DQ5 NC 4 VDD DQ4 3 NC DQ2 DQ3 VDD NC A5 DQ0 NC NC DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G 2 396 ILL F20.1 6 SST39LF/VF016 1 H A14 A13 A15 A16 A17 NC A9 A20 VSS A8 A11 A12 A19 A10 DQ6 DQ7 WE# NC NC NC DQ5 NC NC NC NC NC DQ2 DQ3 VDD NC A7 A18 A6 A5 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E DQ0 NC F VDD DQ4 NC DQ1 G 396 ILL F21.1 SST39LF/VF080 H FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 5 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 3.0-3.6V for SST39LF080/016 2.7-3.6V for SST39VF080/016 Unconnected pins. T2.3 396 1. AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# Read Program VIL VIL VIL VIH Address VIH DOUT AIN VIL DIN AIN VIL X1 Sector or Block address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH DQ Product Identification Software Mode See Table 4 T3.4 396 1. X can be VIL or VIH, but no other value. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 6 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle Addr1 Data 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data Addr1 Data Data AAH Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA2 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data 2AAAH 55H SAX3 30H 3 50H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 98H XXH F0H 5555H AAH 2AAAH 55H 5555H F0H Software ID Entry4,5 CFI Query Entry4 Software ID CFI Exit Exit6/ Software ID Exit6/ CFI Exit 10H T4.3 396 1. Address format A14-A0 (Hex), Addresses A15 - A19 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080. Addresses A15 - A20 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF016. 2. WA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016 4. The device does not remain in Software Product ID Mode if powered down. 5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST39LF/VF080 Device ID = D8H, is read with A0 = 1 SST39LF/VF016 Device ID = D9H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080 AND SST39LF/VF016 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 51H 52H 59H 01H 07H 00H 00H 00H 00H 00H 00H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.3 396 1. Refer to CFI publication 100 for more details. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 7 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39VF320/640 Address Data Data 1BH 27H1 VDD Min (Program/Erase) 30H1 DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 36H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 00H VPP min. (00H = no VPP pin) 1EH 00H VPP max. (00H = no VPP pin) 1FH 04H Typical time out for Byte-Program 2N µs (24 = 16 µs) 20H 00H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 04H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 06H Typical time out for Chip-Erase 2N ms (26 = 64 ms) 23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs) 24H 00H Maximum time out for buffer program 2N times typical 25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) T6.1 396 1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016 TABLE 7: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 14H 00H 00H 00H 00H 02H FFH 00H 10H 00H 0FH 00H 00H 01H FOR SST39LF/VF080 Data Device size = 2N Bytes (14H = 20; 220 = 1 MBytes) Flash Device Interface description; 0000H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 255 + 1 = 256 sectors (00FFH = 255) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 15 + 1 = 16 blocks (000FH = 15) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T7.0 396 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 8 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 8: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 15H 00H 00H 00H 00H 02H FFH 01H 10H 00H 1FH 00H 00H 01H FOR SST39LF/VF016 Data Device size = 2N Bytes (15H = 21; 221 = 2 MBytes) Flash Device Interface description; 0000H = x8-only asynchronous interface Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 511 + 1 = 512 sectors (01FFH = 511) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 31 + 1 = 32 blocks (001FH = 31) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T8.2 396 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 9 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR Range Ambient Temp VDD 0°C to +70°C 3.0-3.6V Commercial OPERATING RANGE FOR Range AC CONDITIONS OF SST39VF080/016 Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V Commercial Industrial SST39LF080/016 TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF080/016 Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080/016 See Figures 14 and 15 ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 10 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 9: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min VDD=VDD Max Read 15 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Program and Erase 20 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max All inputs=VIHC or VILC WE#=VIHC ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage 0.2 VDD-0.2 V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min T9.2 396 TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs TPU-WRITE 1 T10.1 396 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: CAPACITANCE Parameter CI/O 1 CIN1 (Ta = 25°C, f=1 Mhz, other pins open) Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T11.0 396 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 Endurance TDR1 Data Retention ILTH1 Latch Up Minimum Specification Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T12.1 396 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 11 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet AC CHARACTERISTICS TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V SST39LF080/016-55 Symbol Parameter Min Max FOR SST39VF080/016 SST39VF080/016-70 Min Max SST39VF080/016-90 Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time TAA Address Access Time 55 70 90 ns TOE Output Enable Access Time 30 35 45 ns TCLZ1 CE# Low to Active Output 0 0 0 ns TOLZ1 OE# Low to Active Output 0 0 0 ns TCHZ1 CE# High to High-Z Output 15 20 30 ns TOHZ1 OE# High to High-Z Output 15 20 30 ns TOH1 Output Hold from Address Change 55 70 55 0 90 ns 70 0 90 ns 0 ns T13.3 396 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Byte-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns CE# Pulse Width High 30 ns Data Setup Time 30 ns Data Hold Time 0 TCPH 1 TDS TDH 1 Min Max Units 20 µs ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 100 ms T14.0 396 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 12 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID HIGH-Z DATA VALID Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 396 ILL F02.1 FIGURE 3: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 396 ILL F03.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 13 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 AA 55 A0 SW0 SW1 SW2 DATA BYTE (ADDR/DATA) 396 ILL F04.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 396 ILL F05.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 6: DATA# POLLING TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 14 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet ADDRESS AMS-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 396 ILL F06.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 7: TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F08.2 Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 14) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 15 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA BAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 50 SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F09.2 Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 14) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F10.2 Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 14) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 16 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 TAA BF 90 SW2 Note: Device ID = D9H for SST39LF/VF016 D8H for SST39LF/VF080 FIGURE 11: SOFTWARE ID ENTRY AND Device ID 396 ILL F11.3 READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555 CE# OE# TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 TAA 98 SW2 396 ILL F12.0 FIGURE 12: CFI QUERY ENTRY AND READ ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 17 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 5555 2AAA AA 5555 55 F0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 SW2 396 ILL F13.0 FIGURE 13: SOFTWARE ID EXIT/CFI EXIT ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 18 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 396 ILL F14.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 396 ILL F15.1 FIGURE 15: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 19 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 396 ILL F16.1 FIGURE 16: BYTE-PROGRAM ALGORITHM ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 20 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 396 ILL F17.0 FIGURE 17: WAIT OPTIONS ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 21 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 98H Address: 5555H Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 396 ILL F18.1 FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 22 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Load data: 50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFH Sector erased to FFH Block erased to FFH 396 ILL F19.1 FIGURE 19: ERASE COMMAND SEQUENCE ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 23 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet PRODUCT ORDERING INFORMATION Device SST39VFxxx Speed - XX Suffix1 - XX Suffix2 - XX Package Modifier I = 40 leads K = 48 balls Package Type E = TSOP (10mm x 20mm) B3 = TFBGA (0.8mm pitch, 6mm x 8mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns Device Density 080 = 8 Megabit 016 = 16 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V Valid combinations for SST39LF080 SST39LF080-55-4C-EI SST39LF080-55-4C-B3K Valid combinations for SST39VF080 SST39VF080-70-4C-EI SST39VF080-90-4C-EI SST39VF080-70-4C-B3K SST39VF080-90-4C-B3K SST39VF080-70-4I-EI SST39VF080-90-4I-EI SST39VF080-70-4I-B3K SST39VF080-90-4I-B3K Valid combinations for SST39LF016 SST39LF016-55-4C-EI SST39LF016-55-4C-B3K Valid combinations for SST39VF016 SST39VF016-70-4C-EI SST39VF016-90-4C-EI SST39VF016-70-4C-B3K SST39VF016-90-4C-B3K SST39VF016-70-4I-EI SST39VF016-90-4I-EI SST39VF016-70-4I-B3K SST39VF016-90-4I-B3K Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 24 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 10.10 9.90 0.15 0.05 18.50 18.30 0.70 0.50 Note: 20.20 19.80 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 40.TSOP-EI-ILL.4 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM SST PACKAGE CODE: EI X ©2001 Silicon Storage Technology, Inc. 20MM S71146-03-000 6/01 25 396 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet BOTTOM VIEW 8.00 ± 0.20 5.60 TOP VIEW 0.80 6 6 5 5 4.00 4 4 6.00 ± 0.20 3 3 2 2 1 1 0.80 H G F E D C B A A B C D E F G H 0.45 ± 0.05 (48X) A1 CORNER A1 CORNER SIDE VIEW 1.10 ± 0.10 0.15 SEATING PLANE 48ba-TFBGA-B3K-6x8-450mic-ILL.0 0.35 ± 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM SST PACKAGE CODE: B3K X 8MM Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71146-03-000 6/01 26 396