8 Mbit (x8) Multi-Purpose Flash SST39VF088 SST39VF0882.7V 8Mb (x8) MPF memory Preliminary Specifications FEATURES: • Organized as 1M x8 • Single Voltage Read and Write Operations – 2.7-3.6V • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 12 mA (typical) – Standby Current: 4 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Block-Erase Capability – Uniform 64 KByte blocks • Fast Read Access Time: – 70 and 90 ns • Latched Address and Data • Fast Erase and Byte-Program – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 15 seconds (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 48-lead TSOP (12mm x 20mm) PRODUCT DESCRIPTION The SST39VF088 device is a 1M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF088 writes (Program or Erase) with a 2.7-3.6V power supply. It conforms to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39VF088 device provides a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF088 is offered in 48-lead TSOP packaging. See Figure 1 for pin assignments. The SST39VF088 device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since ©2003 Silicon Storage Technology, Inc. S71227-04-000 11/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Device Operation sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 8 and 9 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read Chip-Erase Operation The Read operation of the SST39VF088 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 2). The SST39VF088 provides a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 7 for timing diagram, and Figure 16 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Byte-Program Operation The SST39VF088 is programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 3 and 4 for WE# and CE# controlled Program operation timing diagrams and Figure 13 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39VF088 provides two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF088 offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command ©2003 Silicon Storage Technology, Inc. S71227-04-000 2 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Data# Polling (DQ7) Data Protection When the SST39VF088 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling timing diagram and Figure 14 for a flowchart. The SST39VF088 provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39VF088 provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39VF088 device is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle Bit timing diagram and Figure 14 for a flowchart. ©2003 Silicon Storage Technology, Inc. S71227-04-000 3 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Product Identification Product Identification Mode Exit The Product Identification mode identifies the device as the SST39VF088 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 10 for the Software ID Entry and Read timing diagram and Figure 15 for the Software ID Entry command sequence flowchart. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes and Figure 15 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Manufacturer’s ID Address Data 0000H BFH 0001H D8H Device ID SST39VF088 T1.0 1227 FUNCTIONAL BLOCK DIAGRAM X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# OE# I/O Buffers and Data Latches Control Logic WE# DQ7 - DQ0 1227 B1.0 ©2003 Silicon Storage Technology, Inc. S71227-04-000 4 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications A16 A15 A14 A13 A12 A11 A10 A9 NC NC WE# NC NC NC NC A19 A18 A8 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard Pinout Top View Die Up A17 NC VSS A0 DQ7 NC DQ6 NC DQ5 NC DQ4 VDD NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# VSS CE# A1 1227 48-tsop P01.0 FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 2.7-3.6V for SST39VF088 Unconnected pins. T2.0 1227 1. AMS = Most significant address AMS = A19 for SST39VF088 ©2003 Silicon Storage Technology, Inc. S71227-04-000 5 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN Erase VIL VIH VIL X1 Sector or Block address, XXH for Chip-Erase Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.0 1227 1. X can be VIL or VIH, but no other value. TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle Addr1 Data Addr1 Data Addr1 Data Addr1 Data Byte-Program AAAH AAH 555H 55H AAAH A0H WA2 Data Block-Erase AAAH AAH 555H 55H AAAH 80H AAAH Sector-Erase AAAH AAH 555H 55H AAAH 80H Chip-Erase AAAH AAH 555H 55H AAAH 80H Software ID Entry4,5 AAAH AAH 555H 55H AAAH 90H XXH F0H Software ID Exit6 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data AAH 555H 55H BAX3 30H AAAH AAH 555H 55H SAX3 50H AAAH AAH 555H 55H AAAH 10H T4.1 1227 1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence. 2. WA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines BAX for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39VF088 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0 SST39VF088 Device ID = D8H, is read with A0 = 1 6. Both Software ID Exit operations are equivalent ©2003 Silicon Storage Technology, Inc. S71227-04-000 6 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR Range Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V Commercial Industrial AC CONDITIONS OF SST39VF088 TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 11 and 12 ©2003 Silicon Storage Technology, Inc. S71227-04-000 7 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications TABLE 5: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1 Limits Symbol Parameter Min IDD Power Supply Current Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max Read2 15 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) VIH Input High Voltage 0.7VDD VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage 0.3 0.2 VDD-0.2 V VDD=VDD Max V VDD=VDD Max V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min T5.1 1227 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VDD = 3V. Not 100% tested. 2. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs TPU-WRITE 1 T6.0 1227 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE Parameter CI/O 1 CIN1 (Ta = 25°C, f=1 Mhz, other pins open) Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T7.0 1227 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T8.0 1227 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. ©2003 Silicon Storage Technology, Inc. S71227-04-000 8 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V SST39VF088-70 Symbol Parameter Min 70 Max SST39VF088-90 Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time 90 TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ1 CE# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns 70 ns 90 ns 1 CE# High to High-Z Output 20 30 ns TOHZ1 OE# High to High-Z Output 20 30 ns TCHZ TOH 1 Output Hold from Address Change 0 0 ns T9.0 1227 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns CE# Pulse Width High 30 ns Data Setup Time 30 ns Data Hold Time 0 TCPH 1 TDS TDH 1 20 µs ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 100 ms T10.0 1227 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71227-04-000 9 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID Note: AMS = Most significant address AMS = A19 for SST39VF088 1227 F02.1 FIGURE 2: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP AAA TAH ADDRESS AMS-0 555 AAA ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 1227 F03.2 Note: AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71227-04-000 10 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP AAA TAH ADDRESS AMS-0 555 AAA ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 AA 55 A0 SW0 SW1 SW2 DATA BYTE (ADDR/DATA) 1227 F04.2 Note: AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1227 F05.1 Note: AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 5: DATA# POLLING TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71227-04-000 11 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications ADDRESS AMS-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1227 F06.1 Note: AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 6: TOGGLE BIT TIMING DIAGRAM TSCE Six-byte Code for Chip-Erase AAA ADDRESS AMS-0 555 AAA AAA 555 AAA CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 1227 F07.2 Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71227-04-000 12 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications TBE Six-Byte Code for Block-Erase AAA ADDRESS AMS-0 555 AAA AAA 555 BAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088 1227 F08.2 FIGURE 8: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE Six-byte Code for Sector-Erase AAA ADDRESS AMS-0 555 AAA AAA 555 SAX CE# OE# TWP WE# AA DQ7-0 SW0 55 80 AA 55 50 SW1 SW2 SW3 SW4 SW5 1227 F09.2 Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10) AMS = Most significant address AMS = A19 for SST39VF088 FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71227-04-000 13 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY AAA ADDRESS A14-0 555 AAA 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 TAA BF 90 Device ID SW2 1227 F10.1 Note: Device ID = D8H for SST39VF088 FIGURE 10: SOFTWARE ID ENTRY AND READ ©2003 Silicon Storage Technology, Inc. S71227-04-000 14 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1227 F12.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1227 F13.0 FIGURE 12: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71227-04-000 15 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Start Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: A0H Address: AAAH Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1227 F14.0 FIGURE 13: BYTE-PROGRAM ALGORITHM ©2003 Silicon Storage Technology, Inc. S71227-04-000 16 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1227 F15.0 FIGURE 14: WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71227-04-000 17 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Software Product ID Entry Command Sequence Software ID Exit Command Sequence Load data: AAH Address: AAAH Load data: F0H Address: XXH Load data: 55H Address: 555H Wait TIDA Load data: 90H Address: AAAH Return to normal operation Wait TIDA 1227 F16.1 Read Software ID FIGURE 15: SOFTWARE ID COMMAND FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71227-04-000 18 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 80H Address: AAAH Load data: 80H Address: AAAH Load data: 80H Address: AAAH Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: AAH Address: AAAH Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 55H Address: 555H Load data: 10H Address: AAAH Load data: 50H Address: SAX Load data: 30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFH Sector erased to FFH Block erased to FFH 1227 F17.0 FIGURE 16: ERASE COMMAND SEQUENCE ©2003 Silicon Storage Technology, Inc. S71227-04-000 19 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications PRODUCT ORDERING INFORMATION SST 39 XX VF 088 XX XXXX - 70 - XXX - 4C XX EK - XXX E X Environmental Attribute E = non-Pb Package Modifier K = 48 leads Package Type E = TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 088 = 8 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash Valid combinations for SST39VF088 SST39VF088-70-4C-EK SST39VF088-70-4C-EKE SST39VF088-90-4C-EK SST39VF088-90-4C-EKE SST39VF088-70-4I-EK SST39VF088-70-4I-EKE SST39VF088-90-4I-EK SST39VF088-90-4I-EKE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. S71227-04-000 20 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 12.20 11.80 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0˚- 5˚ Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK X 0.70 0.50 1mm 48-tsop-EK-8 20MM TABLE 11: REVISION HISTORY Number Description Date 00 • Initial Release Mar 2003 01 • Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Table 4 on page 6 Apr 2003 02 • Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Figures 3 and 4 Jun 2003 03 • Auto Low Power feature references removed. (CE# toggled high achieves same effect.) Aug 2003 04 • 2004 Data Book Nov 2003 ©2003 Silicon Storage Technology, Inc. S71227-04-000 21 11/03 8 Mbit Multi-Purpose Flash SST39VF088 Preliminary Specifications Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71227-04-000 22 11/03