STP80NF10 STP80NF10FP N-CHANNEL 100V - 0.012Ω - 80A TO-220/TO-220FP LOW GATE CHARGE STripFET™II POWER MOSFET TYPE STP80NF10 STP80NF10FP ■ ■ ■ ■ VDSS RDS(on) ID 100 V 100 V < 0.015 Ω < 0.015 Ω 80 A 38 A TYPICAL RDS(on) = 0.012Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION 3 1 3 2 1 TO-220 DESCRIPTION This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value STP80NF10 Unit STP80NF10FP Drain-source Voltage (VGS = 0) 100 V Drain-gate Voltage (RGS = 20 kΩ) 100 V VGS Gate- source Voltage ±20 V ID(*) Drain Current (continuous) at TC = 25°C ID Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C 300 VDS VDGR IDM (l) PTOT Derating Factor dv/dt (1) Peak Diode Recovery voltage slope EAS (2) Single Pulse Avalanche Energy VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature (●) Pulse width limited by safe operating area (*) Limited by Package September 2002 80 38 A 66 27 A 320 152 A 45 W 0.3 W/°C 2 9 V/ns 360 mJ - 2500 – 55 to 175 V °C (1) I SD ≤80A, di/dt ≤300A/µs, VDD ≤ V (BR)DSS, Tj ≤ T JMAX. (2) Starting T j = 25°C, I D = 80A, VDD = 50V 1/9 STP80NF10/STP80NF10FP THERMAL DATA TO-220 TO-220FP 0.5 3.33 Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl °C/W ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) VGS = ±20V V(BR)DSS Min. Typ. Max. 100 Unit V VDS = Max Rating, TC = 125 °C 1 µA 10 µA ±100 nA Max. Unit ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 40 A Min. 2 Typ. 3 4 V 0.012 0.015 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) 2/9 Parameter Forward Transconductance Test Conditions VDS =25V , ID =40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 80 S 4300 pF Ciss Input Capacitance Coss Output Capacitance 600 pF Crss Reverse Transfer Capacitance 230 pF STP80NF10/STP80NF10FP ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD = 50V, ID = 40A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 80V, ID = 80A, VGS = 10V Typ. Max. Unit 40 ns 145 ns 140 23 51 189 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions Min. VDD = 50V, ID = 40A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) 134 115 ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Test Conditions Min. Typ. Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80A, VGS = 0 ISD = 80A, di/dt = 100A/µs, VDD = 50V, Tj = 150°C (see test circuit, Figure 5) Max. Unit 80 A 320 A 1.3 155 0.85 11 V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP80NF10/STP80NF10FP Thermal Impedence for TO-220 Output Characteristics Transconductance 4/9 Thermal Impedence for TO-220FP Transfer Characteristics Static Drain-source On Resistance STP80NF10/STP80NF10FP Gate Charge vs Gate-source Voltage Normalized Gate Thereshold Voltage vs Temp. Capacitance Variations Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP80NF10/STP80NF10FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP80NF10/STP80NF10FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP80NF10/STP80NF10FP TO-220FP MECHANICAL DATA mm. DIM. MIN. inch TYP MAX. MIN. 4.6 0.173 TYP. MAX. A 4.4 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 L2 0.409 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L7 L3 L6 F2 H G G1 F F1 L7 L2 8/9 L5 1 2 3 L4 STP80NF10/STP80NF10FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 9/9